target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7622-rfb1-ubi.dts

   1 /*
   2  * Copyright (c) 2018 MediaTek Inc.
   3  * Author: Ryder Lee <ryder.lee@mediatek.com>
   4  *
   5  * SPDX-License-Identifier: (GPL-2.0 OR MIT)
   6  */
   7
   8 /dts-v1/;
   9 #include <dt-bindings/input/input.h>
  10 #include <dt-bindings/gpio/gpio.h>
  11
  12 #include "mt7622.dtsi"
  13 #include "mt6380.dtsi"
  14
  15 / {
  16         model = "MT7622_MT7531 RFB";
  17         compatible = "mediatek,mt7622,ubi";
  18
  19         aliases {
  20                 serial0 = &uart0;
  21         };
  22
  23         chosen {
  24                 stdout-path = "serial0:115200n8";
  25                 bootargs = "earlycon=uart8250,mmio32,0x11002000 console=ttyS0,115200n1 swiotlb=512";
  26         };
  27
  28         cpus {
  29                 cpu@0 {
  30                         proc-supply = <&mt6380_vcpu_reg>;
  31                         sram-supply = <&mt6380_vm_reg>;
  32                 };
  33
  34                 cpu@1 {
  35                         proc-supply = <&mt6380_vcpu_reg>;
  36                         sram-supply = <&mt6380_vm_reg>;
  37                 };
  38         };
  39
  40         gpio-keys {
  41                 compatible = "gpio-keys";
  42
  43                 factory {
  44                         label = "factory";
  45                         linux,code = <BTN_0>;
  46                         gpios = <&pio 0 GPIO_ACTIVE_HIGH>;
  47                 };
  48
  49                 wps {
  50                         label = "wps";
  51                         linux,code = <KEY_WPS_BUTTON>;
  52                         gpios = <&pio 102 GPIO_ACTIVE_HIGH>;
  53                 };
  54         };
  55
  56         gsw: gsw@0 {
  57                 compatible = "mediatek,mt753x";
  58                 mediatek,ethsys = <&ethsys>;
  59                 #address-cells = <1>;
  60                 #size-cells = <0>;
  61         };
  62
  63         leds {
  64                 compatible = "gpio-leds";
  65
  66                 green {
  67                         label = "bpi-r64:pio:green";
  68                         gpios = <&pio 89 GPIO_ACTIVE_HIGH>;
  69                         default-state = "off";
  70                 };
  71
  72                 red {
  73                         label = "bpi-r64:pio:red";
  74                         gpios = <&pio 88 GPIO_ACTIVE_HIGH>;
  75                         default-state = "off";
  76                 };
  77         };
  78
  79         memory {
  80                 reg = <0 0x40000000 0 0x40000000>;
  81         };
  82
  83         reg_1p8v: regulator-1p8v {
  84                 compatible = "regulator-fixed";
  85                 regulator-name = "fixed-1.8V";
  86                 regulator-min-microvolt = <1800000>;
  87                 regulator-max-microvolt = <1800000>;
  88                 regulator-always-on;
  89         };
  90
  91         reg_3p3v: regulator-3p3v {
  92                 compatible = "regulator-fixed";
  93                 regulator-name = "fixed-3.3V";
  94                 regulator-min-microvolt = <3300000>;
  95                 regulator-max-microvolt = <3300000>;
  96                 regulator-boot-on;
  97                 regulator-always-on;
  98         };
  99
 100         reg_5v: regulator-5v {
 101                 compatible = "regulator-fixed";
 102                 regulator-name = "fixed-5V";
 103                 regulator-min-microvolt = <5000000>;
 104                 regulator-max-microvolt = <5000000>;
 105                 regulator-boot-on;
 106                 regulator-always-on;
 107         };
 108 };
 109
 110 &bch {
 111         status = "okay";
 112 };
 113
 114 &btif {
 115         status = "okay";
 116 };
 117
 118 &cir {
 119         pinctrl-names = "default";
 120         pinctrl-0 = <&irrx_pins>;
 121         status = "okay";
 122 };
 123
 124 &eth {
 125         status = "okay";
 126         gmac0: mac@0 {
 127                 compatible = "mediatek,eth-mac";
 128                 reg = <0>;
 129                 phy-mode = "2500base-x";
 130
 131                 fixed-link {
 132                         speed = <2500>;
 133                         full-duplex;
 134                         pause;
 135                 };
 136         };
 137
 138         gmac1: mac@1 {
 139                 compatible = "mediatek,eth-mac";
 140                 reg = <1>;
 141                 phy-mode = "rgmii";
 142
 143                 fixed-link {
 144                         speed = <1000>;
 145                         full-duplex;
 146                         pause;
 147                 };
 148         };
 149
 150         mdio: mdio-bus {
 151                 #address-cells = <1>;
 152                 #size-cells = <0>;
 153         };
 154 };
 155
 156 &gsw {
 157         mediatek,mdio = <&mdio>;
 158         mediatek,portmap = "llllw";
 159         mediatek,mdio_master_pinmux = <0>;
 160         reset-gpios = <&pio 54 0>;
 161         interrupt-parent = <&pio>;
 162         interrupts = <53 IRQ_TYPE_LEVEL_HIGH>;
 163         status = "okay";
 164
 165         port5: port@5 {
 166                 compatible = "mediatek,mt753x-port";
 167                 reg = <5>;
 168                 phy-mode = "rgmii";
 169                 fixed-link {
 170                         speed = <1000>;
 171                         full-duplex;
 172                 };
 173         };
 174
 175         port6: port@6 {
 176                 compatible = "mediatek,mt753x-port";
 177                 reg = <6>;
 178                 phy-mode = "sgmii";
 179                 fixed-link {
 180                         speed = <2500>;
 181                         full-duplex;
 182                 };
 183         };
 184 };
 185
 186 &i2c1 {
 187         pinctrl-names = "default";
 188         pinctrl-0 = <&i2c1_pins>;
 189         status = "okay";
 190 };
 191
 192 &i2c2 {
 193         pinctrl-names = "default";
 194         pinctrl-0 = <&i2c2_pins>;
 195         status = "okay";
 196 };
 197
 198 &mmc0 {
 199         pinctrl-names = "default", "state_uhs";
 200         pinctrl-0 = <&emmc_pins_default>;
 201         pinctrl-1 = <&emmc_pins_uhs>;
 202         status = "okay";
 203         bus-width = <8>;
 204         max-frequency = <50000000>;
 205         cap-mmc-highspeed;
 206         mmc-hs200-1_8v;
 207         vmmc-supply = <&reg_3p3v>;
 208         vqmmc-supply = <&reg_1p8v>;
 209         assigned-clocks = <&topckgen CLK_TOP_MSDC30_0_SEL>;
 210         assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
 211         non-removable;
 212 };
 213
 214 &mmc1 {
 215         pinctrl-names = "default", "state_uhs";
 216         pinctrl-0 = <&sd0_pins_default>;
 217         pinctrl-1 = <&sd0_pins_uhs>;
 218         status = "okay";
 219         bus-width = <4>;
 220         max-frequency = <50000000>;
 221         cap-sd-highspeed;
 222         r_smpl = <1>;
 223         cd-gpios = <&pio 81 GPIO_ACTIVE_LOW>;
 224         vmmc-supply = <&reg_3p3v>;
 225         vqmmc-supply = <&reg_3p3v>;
 226         assigned-clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>;
 227         assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
 228 };
 229
 230 &nandc {
 231         pinctrl-names = "default";
 232         pinctrl-0 = <&parallel_nand_pins>;
 233         status = "disabled";
 234 };
 235
 236 &nor_flash {
 237         pinctrl-names = "default";
 238         pinctrl-0 = <&spi_nor_pins>;
 239         status = "disabled";
 240
 241         flash@0 {
 242                 compatible = "jedec,spi-nor";
 243                 reg = <0>;
 244         };
 245 };
 246
 247 &pcie0 {
 248         pinctrl-names = "default";
 249         pinctrl-0 = <&pcie0_pins>;
 250         status = "okay";
 251 };
 252
 253 &pcie1 {
 254         pinctrl-names = "default";
 255         pinctrl-0 = <&pcie1_pins>;
 256         status = "okay";
 257 };
 258
 259 &pio {
 260         /* Attention: GPIO 90 is used to switch between PCIe@1,0 and
 261          * SATA functions. i.e. output-high: PCIe, output-low: SATA
 262          */
 263         asm_sel {
 264                 gpio-hog;
 265                 gpios = <90 GPIO_ACTIVE_HIGH>;
 266                 output-high;
 267         };
 268
 269         /* eMMC is shared pin with parallel NAND */
 270         emmc_pins_default: emmc-pins-default {
 271                 mux {
 272                         function = "emmc", "emmc_rst";
 273                         groups = "emmc";
 274                 };
 275
 276                 /* "NDL0","NDL1","NDL2","NDL3","NDL4","NDL5","NDL6","NDL7",
 277                  * "NRB","NCLE" pins are used as DAT0,DAT1,DAT2,DAT3,DAT4,
 278                  * DAT5,DAT6,DAT7,CMD,CLK for eMMC respectively
 279                  */
 280                 conf-cmd-dat {
 281                         pins = "NDL0", "NDL1", "NDL2",
 282                                "NDL3", "NDL4", "NDL5",
 283                                "NDL6", "NDL7", "NRB";
 284                         input-enable;
 285                         bias-pull-up;
 286                 };
 287
 288                 conf-clk {
 289                         pins = "NCLE";
 290                         bias-pull-down;
 291                 };
 292         };
 293
 294         emmc_pins_uhs: emmc-pins-uhs {
 295                 mux {
 296                         function = "emmc";
 297                         groups = "emmc";
 298                 };
 299
 300                 conf-cmd-dat {
 301                         pins = "NDL0", "NDL1", "NDL2",
 302                                "NDL3", "NDL4", "NDL5",
 303                                "NDL6", "NDL7", "NRB";
 304                         input-enable;
 305                         drive-strength = <4>;
 306                         bias-pull-up;
 307                 };
 308
 309                 conf-clk {
 310                         pins = "NCLE";
 311                         drive-strength = <4>;
 312                         bias-pull-down;
 313                 };
 314         };
 315
 316         eth_pins: eth-pins {
 317                 mux {
 318                         function = "eth";
 319                         groups = "mdc_mdio", "rgmii_via_gmac2";
 320                 };
 321         };
 322
 323         i2c1_pins: i2c1-pins {
 324                 mux {
 325                         function = "i2c";
 326                         groups =  "i2c1_0";
 327                 };
 328         };
 329
 330         i2c2_pins: i2c2-pins {
 331                 mux {
 332                         function = "i2c";
 333                         groups =  "i2c2_0";
 334                 };
 335         };
 336
 337         i2s1_pins: i2s1-pins {
 338                 mux {
 339                         function = "i2s";
 340                         groups =  "i2s_out_mclk_bclk_ws",
 341                                   "i2s1_in_data",
 342                                   "i2s1_out_data";
 343                 };
 344
 345                 conf {
 346                         pins = "I2S1_IN", "I2S1_OUT", "I2S_BCLK",
 347                                "I2S_WS", "I2S_MCLK";
 348                         drive-strength = <12>;
 349                         bias-pull-down;
 350                 };
 351         };
 352
 353         irrx_pins: irrx-pins {
 354                 mux {
 355                         function = "ir";
 356                         groups =  "ir_1_rx";
 357                 };
 358         };
 359
 360         irtx_pins: irtx-pins {
 361                 mux {
 362                         function = "ir";
 363                         groups =  "ir_1_tx";
 364                 };
 365         };
 366
 367         /* Parallel nand is shared pin with eMMC */
 368         parallel_nand_pins: parallel-nand-pins {
 369                 mux {
 370                         function = "flash";
 371                         groups = "par_nand";
 372                 };
 373         };
 374
 375         pcie0_pins: pcie0-pins {
 376                 mux {
 377                         function = "pcie";
 378                         groups = "pcie0_pad_perst",
 379                                  "pcie0_1_waken",
 380                                  "pcie0_1_clkreq";
 381                 };
 382         };
 383
 384         pcie1_pins: pcie1-pins {
 385                 mux {
 386                         function = "pcie";
 387                         groups = "pcie1_pad_perst",
 388                                  "pcie1_0_waken",
 389                                  "pcie1_0_clkreq";
 390                 };
 391         };
 392
 393         pmic_bus_pins: pmic-bus-pins {
 394                 mux {
 395                         function = "pmic";
 396                         groups = "pmic_bus";
 397                 };
 398         };
 399
 400         pwm7_pins: pwm1-2-pins {
 401                 mux {
 402                         function = "pwm";
 403                         groups = "pwm_ch7_2";
 404                 };
 405         };
 406
 407         wled_pins: wled-pins {
 408                 mux {
 409                         function = "led";
 410                         groups = "wled";
 411                 };
 412         };
 413
 414         sd0_pins_default: sd0-pins-default {
 415                 mux {
 416                         function = "sd";
 417                         groups = "sd_0";
 418                 };
 419
 420                 /* "I2S2_OUT, "I2S4_IN"", "I2S3_IN", "I2S2_IN",
 421                  *  "I2S4_OUT", "I2S3_OUT" are used as DAT0, DAT1,
 422                  *  DAT2, DAT3, CMD, CLK for SD respectively.
 423                  */
 424                 conf-cmd-data {
 425                         pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
 426                                "I2S2_IN","I2S4_OUT";
 427                         input-enable;
 428                         drive-strength = <8>;
 429                         bias-pull-up;
 430                 };
 431                 conf-clk {
 432                         pins = "I2S3_OUT";
 433                         drive-strength = <12>;
 434                         bias-pull-down;
 435                 };
 436                 conf-cd {
 437                         pins = "TXD3";
 438                         bias-pull-up;
 439                 };
 440         };
 441
 442         sd0_pins_uhs: sd0-pins-uhs {
 443                 mux {
 444                         function = "sd";
 445                         groups = "sd_0";
 446                 };
 447
 448                 conf-cmd-data {
 449                         pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
 450                                "I2S2_IN","I2S4_OUT";
 451                         input-enable;
 452                         bias-pull-up;
 453                 };
 454
 455                 conf-clk {
 456                         pins = "I2S3_OUT";
 457                         bias-pull-down;
 458                 };
 459         };
 460
 461         /* Serial NAND is shared pin with SPI-NOR */
 462         serial_nand_pins: serial-nand-pins {
 463                 mux {
 464                         function = "flash";
 465                         groups = "snfi";
 466                 };
 467         };
 468
 469         spic0_pins: spic0-pins {
 470                 mux {
 471                         function = "spi";
 472                         groups = "spic0_0";
 473                 };
 474         };
 475
 476         spic1_pins: spic1-pins {
 477                 mux {
 478                         function = "spi";
 479                         groups = "spic1_0";
 480                 };
 481         };
 482
 483         /* SPI-NOR is shared pin with serial NAND */
 484         spi_nor_pins: spi-nor-pins {
 485                 mux {
 486                         function = "flash";
 487                         groups = "spi_nor";
 488                 };
 489         };
 490
 491         /* serial NAND is shared pin with SPI-NOR */
 492         serial_nand_pins: serial-nand-pins {
 493                 mux {
 494                         function = "flash";
 495                         groups = "snfi";
 496                 };
 497         };
 498
 499         uart0_pins: uart0-pins {
 500                 mux {
 501                         function = "uart";
 502                         groups = "uart0_0_tx_rx" ;
 503                 };
 504         };
 505
 506         uart2_pins: uart2-pins {
 507                 mux {
 508                         function = "uart";
 509                         groups = "uart2_1_tx_rx" ;
 510                 };
 511         };
 512
 513         watchdog_pins: watchdog-pins {
 514                 mux {
 515                         function = "watchdog";
 516                         groups = "watchdog";
 517                 };
 518         };
 519 };
 520
 521 &pwm {
 522         pinctrl-names = "default";
 523         pinctrl-0 = <&pwm7_pins>;
 524         status = "okay";
 525 };
 526
 527 &pwrap {
 528         pinctrl-names = "default";
 529         pinctrl-0 = <&pmic_bus_pins>;
 530
 531         status = "okay";
 532 };
 533
 534 &sata {
 535         status = "disable";
 536 };
 537
 538 &sata_phy {
 539         status = "disable";
 540 };
 541
 542 &snfi {
 543         pinctrl-names = "default";
 544         pinctrl-0 = <&serial_nand_pins>;
 545         status = "okay";
 546
 547         spi_nand@0 {
 548                 #address-cells = <1>;
 549                 #size-cells = <1>;
 550                 compatible = "spi-nand";
 551                 spi-max-frequency = <104000000>;
 552                 reg = <0>;
 553
 554                 partitions {
 555                         compatible = "fixed-partitions";
 556                         #address-cells = <1>;
 557                         #size-cells = <1>;
 558
 559                         partition@0 {
 560                                 label = "Preloader";
 561                                 reg = <0x00000 0x0080000>;
 562                                 read-only;
 563                         };
 564
 565                         partition@80000 {
 566                                 label = "ATF";
 567                                 reg = <0x80000 0x0040000>;
 568                         };
 569
 570                         partition@c0000 {
 571                                 label = "Bootloader";
 572                                 reg = <0xc0000 0x0080000>;
 573                         };
 574
 575                         partition@140000 {
 576                                 label = "Config";
 577                                 reg = <0x140000 0x0080000>;
 578                         };
 579
 580                         factory: partition@1c0000 {
 581                                 label = "Factory";
 582                                 reg = <0x1c0000 0x0040000>;
 583                         };
 584
 585                         partition@200000 {
 586                                 label = "kernel";
 587                                 reg = <0x200000 0x400000>;
 588                         };
 589
 590                         partition@600000 {
 591                                 label = "ubi";
 592                                 reg = <0x600000 0x1C00000>;
 593                         };
 594
 595                         partition@2200000 {
 596                                 label = "User_data";
 597                                 reg = <0x2200000 0x4000000>;
 598                         };
 599                 };
 600         };
 601 };
 602
 603 &spi0 {
 604         pinctrl-names = "default";
 605         pinctrl-0 = <&spic0_pins>;
 606         status = "okay";
 607 };
 608
 609 &spi1 {
 610         pinctrl-names = "default";
 611         pinctrl-0 = <&spic1_pins>;
 612         status = "okay";
 613 };
 614
 615 &ssusb {
 616         vusb33-supply = <&reg_3p3v>;
 617         vbus-supply = <&reg_5v>;
 618         status = "okay";
 619 };
 620
 621 &u3phy {
 622         status = "okay";
 623 };
 624
 625 &uart0 {
 626         pinctrl-names = "default";
 627         pinctrl-0 = <&uart0_pins>;
 628         status = "okay";
 629 };
 630
 631 &uart2 {
 632         pinctrl-names = "default";
 633         pinctrl-0 = <&uart2_pins>;
 634         status = "okay";
 635 };
 636
 637 &watchdog {
 638         pinctrl-names = "default";
 639         pinctrl-0 = <&watchdog_pins>;
 640         status = "okay";
 641 };
 642
 643 &wmac {
 644         mediatek,mtd-eeprom = <&factory 0x0000>;
 645         status = "okay";
 646 };