1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 * Copyright (C) 2022 MediaTek Inc.
4 * Author: Sam.Shih <sam.shih@mediatek.com>
8 #include "mt7988a-rfb-spim-nand.dtsi"
9 #include <dt-bindings/pinctrl/mt65xx.h>
12 model = "MediaTek MT7988A DSA 10G SPIM-NAND RFB";
13 compatible = "mediatek,mt7988a-dsa-10g-spim-snand",
14 "mediatek,mt7988a-rfb-snand",
18 bootargs = "console=ttyS0,115200n1 loglevel=8 \
19 earlycon=uart8250,mmio32,0x11000000 \
24 reg = <0 0x40000000 0 0x40000000>;
29 pinctrl-0 = <&mdio0_pins>;
30 pinctrl-names = "default";
34 compatible = "mediatek,eth-mac";
36 phy-mode = "internal";
46 compatible = "mediatek,eth-mac";
48 phy-mode = "internal";
49 phy-connection-type = "internal";
54 compatible = "mediatek,eth-mac";
56 phy-mode = "10gbase-kr";
57 phy-connection-type = "10gbase-kr";
65 /* external Aquantia AQR113C */
66 phy0: ethernet-phy@0 {
68 compatible = "ethernet-phy-ieee802.3-c45";
69 reset-gpios = <&pio 72 1>;
70 reset-assert-us = <100000>;
71 reset-deassert-us = <221000>;
74 /* external Aquantia AQR113C */
75 phy8: ethernet-phy@8 {
77 compatible = "ethernet-phy-ieee802.3-c45";
78 reset-gpios = <&pio 71 1>;
79 reset-assert-us = <100000>;
80 reset-deassert-us = <221000>;
83 /* external Maxlinear GPY211C */
84 phy5: ethernet-phy@5 {
86 compatible = "ethernet-phy-ieee802.3-c45";
87 phy-mode = "2500base-x";
90 /* external Maxlinear GPY211C */
91 phy13: ethernet-phy@13 {
93 compatible = "ethernet-phy-ieee802.3-c45";
94 phy-mode = "2500base-x";
97 /* internal 2.5G PHY */
98 phy15: ethernet-phy@15 {
100 pinctrl-names = "i2p5gbe-led";
101 pinctrl-0 = <&i2p5gbe_led0_pins>;
102 compatible = "ethernet-phy-ieee802.3-c45";
103 phy-mode = "internal";
112 #address-cells = <1>;
118 phy-mode = "internal";
119 phy-handle = <&gsw_phy0>;
125 phy-mode = "internal";
126 phy-handle = <&gsw_phy1>;
132 phy-mode = "internal";
133 phy-handle = <&gsw_phy2>;
139 phy-mode = "internal";
140 phy-handle = <&gsw_phy3>;
146 phy-mode = "internal";
157 #address-cells = <1>;
160 gsw_phy0: ethernet-phy@0 {
161 compatible = "ethernet-phy-id03a2.9481";
163 phy-mode = "internal";
164 pinctrl-names = "gbe-led";
165 pinctrl-0 = <&gbe0_led0_pins>;
166 nvmem-cells = <&phy_calibration_p0>;
167 nvmem-cell-names = "phy-cal-data";
170 gsw_phy1: ethernet-phy@1 {
171 compatible = "ethernet-phy-id03a2.9481";
173 phy-mode = "internal";
174 pinctrl-names = "gbe-led";
175 pinctrl-0 = <&gbe1_led0_pins>;
176 nvmem-cells = <&phy_calibration_p1>;
177 nvmem-cell-names = "phy-cal-data";
180 gsw_phy2: ethernet-phy@2 {
181 compatible = "ethernet-phy-id03a2.9481";
183 phy-mode = "internal";
184 pinctrl-names = "gbe-led";
185 pinctrl-0 = <&gbe2_led0_pins>;
186 nvmem-cells = <&phy_calibration_p2>;
187 nvmem-cell-names = "phy-cal-data";
190 gsw_phy3: ethernet-phy@3 {
191 compatible = "ethernet-phy-id03a2.9481";
193 phy-mode = "internal";
194 pinctrl-names = "gbe-led";
195 pinctrl-0 = <&gbe3_led0_pins>;
196 nvmem-cells = <&phy_calibration_p3>;
197 nvmem-cell-names = "phy-cal-data";