1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 * Copyright (C) 2023 MediaTek Inc.
4 * Author: Sam.Shih <sam.shih@mediatek.com>
7 #include <dt-bindings/clock/mediatek,mt7988-clk.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/leds/common.h>
11 #include <dt-bindings/phy/phy.h>
12 #include <dt-bindings/pinctrl/mt65xx.h>
13 #include <dt-bindings/reset/mediatek,mt7988-resets.h>
14 #include <dt-bindings/thermal/thermal.h>
17 #define MT7988_TOPRGU_SGMII0_GRST 1
18 #define MT7988_TOPRGU_SGMII1_GRST 2
19 #define MT7988_TOPRGU_XFI0_GRST 12
20 #define MT7988_TOPRGU_XFI1_GRST 13
21 #define MT7988_TOPRGU_XFI_PEXTP0_GRST 14
22 #define MT7988_TOPRGU_XFI_PEXTP1_GRST 15
23 #define MT7988_TOPRGU_XFI_PLL_GRST 16
26 compatible = "mediatek,mt7988a";
27 interrupt-parent = <&gic>;
32 compatible = "mediatek,mt7988-cci",
33 "mediatek,mt8183-cci";
34 clocks = <&mcusys CLK_MCU_BUS_DIV_SEL>,
35 <&topckgen CLK_TOP_XTAL>;
36 clock-names = "cci", "intermediate";
37 operating-points-v2 = <&cci_opp>;
45 compatible = "arm,cortex-a73";
48 enable-method = "psci";
49 clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>,
50 <&topckgen CLK_TOP_XTAL>;
51 clock-names = "cpu", "intermediate";
52 operating-points-v2 = <&cluster0_opp>;
53 mediatek,cci = <&cci>;
57 compatible = "arm,cortex-a73";
60 enable-method = "psci";
61 clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>,
62 <&topckgen CLK_TOP_XTAL>;
63 clock-names = "cpu", "intermediate";
64 operating-points-v2 = <&cluster0_opp>;
65 mediatek,cci = <&cci>;
69 compatible = "arm,cortex-a73";
72 enable-method = "psci";
73 clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>,
74 <&topckgen CLK_TOP_XTAL>;
75 clock-names = "cpu", "intermediate";
76 operating-points-v2 = <&cluster0_opp>;
77 mediatek,cci = <&cci>;
81 compatible = "arm,cortex-a73";
84 enable-method = "psci";
85 clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>,
86 <&topckgen CLK_TOP_XTAL>;
87 clock-names = "cpu", "intermediate";
88 operating-points-v2 = <&cluster0_opp>;
89 mediatek,cci = <&cci>;
92 cluster0_opp: opp_table0 {
93 compatible = "operating-points-v2";
97 opp-hz = /bits/ 64 <800000000>;
98 opp-microvolt = <850000>;
102 opp-hz = /bits/ 64 <1100000000>;
103 opp-microvolt = <850000>;
107 opp-hz = /bits/ 64 <1500000000>;
108 opp-microvolt = <850000>;
112 opp-hz = /bits/ 64 <1800000000>;
113 opp-microvolt = <900000>;
118 cci_opp: opp_table_cci {
119 compatible = "operating-points-v2";
123 opp-hz = /bits/ 64 <480000000>;
124 opp-microvolt = <850000>;
128 opp-hz = /bits/ 64 <660000000>;
129 opp-microvolt = <850000>;
133 opp-hz = /bits/ 64 <900000000>;
134 opp-microvolt = <850000>;
138 opp-hz = /bits/ 64 <1080000000>;
139 opp-microvolt = <900000>;
143 clk40m: oscillator@0 {
144 compatible = "fixed-clock";
145 clock-frequency = <40000000>;
147 clock-output-names = "clkxtal";
151 compatible = "pwm-fan";
152 /* cooling level (0, 1, 2) : (0% duty, 50% duty, 100% duty) */
153 cooling-levels = <0 128 255>;
154 #cooling-cells = <2>;
155 #thermal-sensor-cells = <1>;
160 compatible = "arm,cortex-a73-pmu";
161 interrupt-parent = <&gic>;
162 interrupt = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
166 compatible = "arm,psci-0.2";
170 reg_1p8v: regulator-1p8v {
171 compatible = "regulator-fixed";
172 regulator-name = "fixed-1.8V";
173 regulator-min-microvolt = <1800000>;
174 regulator-max-microvolt = <1800000>;
179 reg_3p3v: regulator-3p3v {
180 compatible = "regulator-fixed";
181 regulator-name = "fixed-3.3V";
182 regulator-min-microvolt = <3300000>;
183 regulator-max-microvolt = <3300000>;
190 #address-cells = <2>;
193 /* 320 KiB reserved for ARM Trusted Firmware (BL31 and BL32) */
194 secmon_reserved: secmon@43000000 {
195 reg = <0 0x43000000 0 0x50000>;
201 compatible = "simple-bus";
203 #address-cells = <2>;
206 gic: interrupt-controller@c000000 {
207 compatible = "arm,gic-v3";
208 reg = <0 0x0c000000 0 0x40000>, /* GICD */
209 <0 0x0c080000 0 0x200000>, /* GICR */
210 <0 0x0c400000 0 0x2000>, /* GICC */
211 <0 0x0c410000 0 0x1000>, /* GICH */
212 <0 0x0c420000 0 0x2000>; /* GICV */
213 interrupt-parent = <&gic>;
214 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
215 interrupt-controller;
216 #interrupt-cells = <3>;
219 phyfw: phy-firmware@f000000 {
220 compatible = "mediatek,2p5gphy-fw";
221 reg = <0 0x0f100000 0 0x20000>,
222 <0 0x0f0f0018 0 0x20>;
225 infracfg: infracfg@10001000 {
226 compatible = "mediatek,mt7988-infracfg", "syscon";
227 reg = <0 0x10001000 0 0x1000>;
232 topckgen: topckgen@1001b000 {
233 compatible = "mediatek,mt7988-topckgen", "syscon";
234 reg = <0 0x1001b000 0 0x1000>;
238 watchdog: watchdog@1001c000 {
239 compatible = "mediatek,mt7988-wdt",
240 "mediatek,mt6589-wdt",
242 reg = <0 0x1001c000 0 0x1000>;
243 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
247 apmixedsys: apmixedsys@1001e000 {
248 compatible = "mediatek,mt7988-apmixedsys";
249 reg = <0 0x1001e000 0 0x1000>;
253 pio: pinctrl@1001f000 {
254 compatible = "mediatek,mt7988-pinctrl", "syscon";
255 reg = <0 0x1001f000 0 0x1000>,
256 <0 0x11c10000 0 0x1000>,
257 <0 0x11d00000 0 0x1000>,
258 <0 0x11d20000 0 0x1000>,
259 <0 0x11e00000 0 0x1000>,
260 <0 0x11f00000 0 0x1000>,
261 <0 0x1000b000 0 0x1000>;
262 reg-names = "gpio_base", "iocfg_tr_base",
263 "iocfg_br_base", "iocfg_rb_base",
264 "iocfg_lb_base", "iocfg_tl_base", "eint";
267 gpio-ranges = <&pio 0 0 84>;
268 interrupt-controller;
269 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
270 interrupt-parent = <&gic>;
271 #interrupt-cells = <2>;
273 mdio0_pins: mdio0-pins {
276 groups = "mdc_mdio0";
280 groups = "mdc_mdio0";
281 drive-strength = <MTK_DRIVE_8mA>;
285 i2c0_pins: i2c0-pins-g0 {
292 i2c1_pins: i2c1-pins-g0 {
299 i2c1_sfp_pins: i2c1-sfp-pins-g0 {
306 i2c2_pins: i2c2-pins {
313 i2c2_0_pins: i2c2-pins-g0 {
320 i2c2_1_pins: i2c2-pins-g1 {
327 gbe0_led0_pins: gbe0-led0-pins {
330 groups = "gbe0_led0";
334 gbe1_led0_pins: gbe1-led0-pins {
337 groups = "gbe1_led0";
341 gbe2_led0_pins: gbe2-led0-pins {
344 groups = "gbe2_led0";
348 gbe3_led0_pins: gbe3-led0-pins {
351 groups = "gbe3_led0";
355 gbe0_led1_pins: gbe0-led1-pins {
358 groups = "gbe0_led1";
362 gbe1_led1_pins: gbe1-led1-pins {
365 groups = "gbe1_led1";
369 gbe2_led1_pins: gbe2-led1-pins {
372 groups = "gbe2_led1";
376 gbe3_led1_pins: gbe3-led1-pins {
379 groups = "gbe3_led1";
383 i2p5gbe_led0_pins: 2p5gbe-led0-pins {
386 groups = "2p5gbe_led0";
390 i2p5gbe_led1_pins: 2p5gbe-led1-pins {
393 groups = "2p5gbe_led1";
397 mmc0_pins_emmc_45: mmc0-pins-emmc-45 {
404 mmc0_pins_emmc_51: mmc0-pins-emmc-51 {
411 mmc0_pins_sdcard: mmc0-pins-sdcard {
418 uart0_pins: uart0-pins {
425 uart1_0_pins: uart1-0-pins {
432 uart1_1_pins: uart1-1-pins {
439 uart1_2_pins: uart1-2-pins {
446 uart1_2_lite_pins: uart1-2-lite-pins {
449 groups = "uart1_2_lite";
453 uart2_pins: uart2-pins {
460 uart2_0_pins: uart2-0-pins {
467 uart2_1_pins: uart2-1-pins {
474 uart2_2_pins: uart2-2-pins {
481 uart2_3_pins: uart2-3-pins {
488 snfi_pins: snfi-pins {
495 spi0_pins: spi0-pins {
502 spi0_flash_pins: spi0-flash-pins {
505 groups = "spi0", "spi0_wp_hold";
509 spi1_pins: spi1-pins {
516 spi2_pins: spi2-pins {
523 spi2_flash_pins: spi2-flash-pins {
526 groups = "spi2", "spi2_wp_hold";
530 pcie0_pins: pcie0-pins {
533 groups = "pcie_2l_0_pereset", "pcie_clk_req_n0_0",
538 pcie1_pins: pcie1-pins {
541 groups = "pcie_2l_1_pereset", "pcie_clk_req_n1",
546 pcie2_pins: pcie2-pins {
549 groups = "pcie_1l_0_pereset", "pcie_clk_req_n2_0",
554 pcie3_pins: pcie3-pins {
557 groups = "pcie_1l_1_pereset", "pcie_clk_req_n3",
564 compatible = "mediatek,mt7988-pwm";
565 reg = <0 0x10048000 0 0x1000>;
567 clocks = <&infracfg CLK_INFRA_66M_PWM_BCK>,
568 <&infracfg CLK_INFRA_66M_PWM_HCK>,
569 <&infracfg CLK_INFRA_66M_PWM_CK1>,
570 <&infracfg CLK_INFRA_66M_PWM_CK2>,
571 <&infracfg CLK_INFRA_66M_PWM_CK3>,
572 <&infracfg CLK_INFRA_66M_PWM_CK4>,
573 <&infracfg CLK_INFRA_66M_PWM_CK5>,
574 <&infracfg CLK_INFRA_66M_PWM_CK6>,
575 <&infracfg CLK_INFRA_66M_PWM_CK7>,
576 <&infracfg CLK_INFRA_66M_PWM_CK8>;
577 clock-names = "top", "main", "pwm1", "pwm2", "pwm3",
578 "pwm4","pwm5","pwm6","pwm7","pwm8";
582 sgmiisys0: syscon@10060000 {
583 compatible = "mediatek,mt7988-sgmiisys",
584 "mediatek,mt7988-sgmiisys0",
587 reg = <0 0x10060000 0 0x1000>;
588 resets = <&watchdog MT7988_TOPRGU_SGMII0_GRST>;
592 compatible = "mediatek,mt7988-sgmii";
593 clocks = <&topckgen CLK_TOP_SGM_0_SEL>,
594 <&sgmiisys0 CLK_SGM0_TX_EN>,
595 <&sgmiisys0 CLK_SGM0_RX_EN>;
596 clock-names = "sgmii_sel", "sgmii_tx", "sgmii_rx";
600 sgmiisys1: syscon@10070000 {
601 compatible = "mediatek,mt7988-sgmiisys",
602 "mediatek,mt7988-sgmiisys1",
605 reg = <0 0x10070000 0 0x1000>;
606 resets = <&watchdog MT7988_TOPRGU_SGMII1_GRST>;
610 compatible = "mediatek,mt7988-sgmii";
611 clocks = <&topckgen CLK_TOP_SGM_1_SEL>,
612 <&sgmiisys1 CLK_SGM1_TX_EN>,
613 <&sgmiisys1 CLK_SGM1_RX_EN>;
614 clock-names = "sgmii_sel", "sgmii_tx", "sgmii_rx";
618 usxgmiisys0: pcs@10080000 {
619 compatible = "mediatek,mt7988-usxgmiisys";
620 reg = <0 0x10080000 0 0x1000>;
621 resets = <&watchdog MT7988_TOPRGU_XFI0_GRST>;
622 clocks = <&topckgen CLK_TOP_USXGMII_SBUS_0_SEL>;
625 usxgmiisys1: pcs@10081000 {
626 compatible = "mediatek,mt7988-usxgmiisys";
627 reg = <0 0x10081000 0 0x1000>;
628 resets = <&watchdog MT7988_TOPRGU_XFI1_GRST>;
629 clocks = <&topckgen CLK_TOP_USXGMII_SBUS_1_SEL>;
632 mcusys: mcusys@100e0000 {
633 compatible = "mediatek,mt7988-mcusys", "syscon";
634 reg = <0 0x100e0000 0 0x1000>;
638 uart0: serial@11000000 {
639 compatible = "mediatek,mt7986-uart",
640 "mediatek,mt6577-uart";
641 reg = <0 0x11000000 0 0x100>;
642 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
644 * 8250-mtk driver don't control "baud" clock since commit
645 * e32a83c70cf9 (kernel v5.7), but both "baud" and "bus" clocks
646 * still need to be passed to the driver to prevent probe fail
648 clocks = <&topckgen CLK_TOP_UART_SEL>,
649 <&infracfg CLK_INFRA_52M_UART0_CK>;
650 clock-names = "baud", "bus";
651 assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
652 <&infracfg CLK_INFRA_MUX_UART0_SEL>;
653 assigned-clock-parents = <&topckgen CLK_TOP_XTAL>,
654 <&topckgen CLK_TOP_UART_SEL>;
655 pinctrl-names = "default";
656 pinctrl-0 = <&uart0_pins>;
660 uart1: serial@11000100 {
661 compatible = "mediatek,mt7986-uart",
662 "mediatek,mt6577-uart";
663 reg = <0 0x11000100 0 0x100>;
664 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
666 * 8250-mtk driver don't control "baud" clock since commit
667 * e32a83c70cf9 (kernel v5.7), but both "baud" and "bus" clocks
668 * still need to be passed to the driver to prevent probe fail
670 clocks = <&topckgen CLK_TOP_UART_SEL>,
671 <&infracfg CLK_INFRA_52M_UART1_CK>;
672 clock-names = "baud", "bus";
673 assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
674 <&infracfg CLK_INFRA_MUX_UART1_SEL>;
675 assigned-clock-parents = <&topckgen CLK_TOP_XTAL>,
676 <&topckgen CLK_TOP_UART_SEL>;
680 uart2: serial@11000200 {
681 compatible = "mediatek,mt7986-uart",
682 "mediatek,mt6577-uart";
683 reg = <0 0x11000200 0 0x100>;
684 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
686 * 8250-mtk driver don't control "baud" clock since commit
687 * e32a83c70cf9 (kernel v5.7), but both "baud" and "bus" clocks
688 * still need to be passed to the driver to prevent probe fail
690 clocks = <&topckgen CLK_TOP_UART_SEL>,
691 <&infracfg CLK_INFRA_52M_UART2_CK>;
692 clock-names = "baud", "bus";
693 assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
694 <&infracfg CLK_INFRA_MUX_UART2_SEL>;
695 assigned-clock-parents = <&topckgen CLK_TOP_XTAL>,
696 <&topckgen CLK_TOP_UART_SEL>;
700 snand: spi@11001000 {
701 compatible = "mediatek,mt7986-snand";
702 reg = <0 0x11001000 0 0x1000>;
703 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
704 clocks = <&infracfg CLK_INFRA_SPINFI>,
705 <&infracfg CLK_INFRA_NFI>;
706 clock-names = "pad_clk", "nfi_clk";
707 assigned-clocks = <&topckgen CLK_TOP_SPINFI_SEL>,
708 <&topckgen CLK_TOP_NFI1X_SEL>;
709 assigned-clock-parents = <&topckgen CLK_TOP_MPLL_D8>,
710 <&topckgen CLK_TOP_MPLL_D8>;
711 nand-ecc-engine = <&bch>;
713 #address-cells = <1>;
715 pinctrl-names = "default";
716 pinctrl-0 = <&snfi_pins>;
721 compatible = "mediatek,mt7686-ecc";
722 reg = <0 0x11002000 0 0x1000>;
723 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
724 clocks = <&topckgen CLK_TOP_NFI1X_SEL>;
725 clock-names = "nfiecc_clk";
730 compatible = "mediatek,mt7988-i2c",
731 "mediatek,mt7981-i2c";
732 reg = <0 0x11003000 0 0x1000>,
733 <0 0x10217080 0 0x80>;
734 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
736 clocks = <&infracfg CLK_INFRA_I2C_BCK>,
737 <&infracfg CLK_INFRA_66M_AP_DMA_BCK>;
738 clock-names = "main", "dma";
739 #address-cells = <1>;
745 compatible = "mediatek,mt7988-i2c",
746 "mediatek,mt7981-i2c";
747 reg = <0 0x11004000 0 0x1000>,
748 <0 0x10217100 0 0x80>;
749 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
751 clocks = <&infracfg CLK_INFRA_I2C_BCK>,
752 <&infracfg CLK_INFRA_66M_AP_DMA_BCK>;
753 clock-names = "main", "dma";
754 #address-cells = <1>;
760 compatible = "mediatek,mt7988-i2c",
761 "mediatek,mt7981-i2c";
762 reg = <0 0x11005000 0 0x1000>,
763 <0 0x10217180 0 0x80>;
764 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
766 clocks = <&infracfg CLK_INFRA_I2C_BCK>,
767 <&infracfg CLK_INFRA_66M_AP_DMA_BCK>;
768 clock-names = "main", "dma";
769 #address-cells = <1>;
775 compatible = "mediatek,ipm-spi-quad", "mediatek,spi-ipm";
776 reg = <0 0x11007000 0 0x100>;
777 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
778 clocks = <&topckgen CLK_TOP_MPLL_D2>,
779 <&topckgen CLK_TOP_SPI_SEL>,
780 <&infracfg CLK_INFRA_104M_SPI0>,
781 <&infracfg CLK_INFRA_66M_SPI0_HCK>;
782 clock-names = "parent-clk", "sel-clk", "spi-clk",
784 #address-cells = <1>;
790 compatible = "mediatek,ipm-spi-single", "mediatek,spi-ipm";
791 reg = <0 0x11008000 0 0x100>;
792 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
793 clocks = <&topckgen CLK_TOP_MPLL_D2>,
794 <&topckgen CLK_TOP_SPI_SEL>,
795 <&infracfg CLK_INFRA_104M_SPI1>,
796 <&infracfg CLK_INFRA_66M_SPI1_HCK>;
797 clock-names = "parent-clk", "sel-clk", "spi-clk",
799 #address-cells = <1>;
801 pinctrl-names = "default";
802 pinctrl-0 = <&spi1_pins>;
807 compatible = "mediatek,ipm-spi-quad", "mediatek,spi-ipm";
808 reg = <0 0x11009000 0 0x100>;
809 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
810 clocks = <&topckgen CLK_TOP_MPLL_D2>,
811 <&topckgen CLK_TOP_SPI_SEL>,
812 <&infracfg CLK_INFRA_104M_SPI2_BCK>,
813 <&infracfg CLK_INFRA_66M_SPI2_HCK>;
814 clock-names = "parent-clk", "sel-clk", "spi-clk",
816 #address-cells = <1>;
821 lvts: lvts@1100a000 {
822 compatible = "mediatek,mt7988-lvts-ap";
823 reg = <0 0x1100a000 0 0x1000>;
824 clocks = <&infracfg CLK_INFRA_26M_THERM_SYSTEM>;
825 clock-names = "lvts_clk";
826 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
827 resets = <&infracfg MT7988_INFRA_RST1_THERM_CTRL_SWRST>;
828 nvmem-cells = <&lvts_calibration>;
829 nvmem-cell-names = "lvts-calib-data-1";
830 #thermal-sensor-cells = <1>;
833 ssusb0: usb@11190000 {
834 compatible = "mediatek,mt7988-xhci",
836 reg = <0 0x11190000 0 0x2e00>,
837 <0 0x11193e00 0 0x0100>;
838 reg-names = "mac", "ippc";
839 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
840 phys = <&xphyu2port0 PHY_TYPE_USB2>,
841 <&xphyu3port0 PHY_TYPE_USB3>;
842 clocks = <&infracfg CLK_INFRA_USB_SYS>,
843 <&infracfg CLK_INFRA_USB_XHCI>,
844 <&infracfg CLK_INFRA_USB_REF>,
845 <&infracfg CLK_INFRA_66M_USB_HCK>,
846 <&infracfg CLK_INFRA_133M_USB_HCK>;
847 clock-names = "sys_ck",
852 #address-cells = <2>;
854 mediatek,p0_speed_fixup;
858 ssusb1: usb@11200000 {
859 compatible = "mediatek,mt7988-xhci",
861 reg = <0 0x11200000 0 0x2e00>,
862 <0 0x11203e00 0 0x0100>;
863 reg-names = "mac", "ippc";
864 interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
865 phys = <&tphyu2port0 PHY_TYPE_USB2>,
866 <&tphyu3port0 PHY_TYPE_USB3>;
867 clocks = <&infracfg CLK_INFRA_USB_SYS_CK_P1>,
868 <&infracfg CLK_INFRA_USB_XHCI_CK_P1>,
869 <&infracfg CLK_INFRA_USB_CK_P1>,
870 <&infracfg CLK_INFRA_66M_USB_HCK_CK_P1>,
871 <&infracfg CLK_INFRA_133M_USB_HCK_CK_P1>;
872 clock-names = "sys_ck",
877 #address-cells = <2>;
882 afe: audio-controller@11210000 {
883 compatible = "mediatek,mt79xx-audio";
884 reg = <0 0x11210000 0 0x9000>;
885 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
886 clocks = <&infracfg CLK_INFRA_66M_AUD_SLV_BCK>,
887 <&infracfg CLK_INFRA_AUD_26M>,
888 <&infracfg CLK_INFRA_AUD_L>,
889 <&infracfg CLK_INFRA_AUD_AUD>,
890 <&infracfg CLK_INFRA_AUD_EG2>,
891 <&topckgen CLK_TOP_AUD_SEL>,
892 <&topckgen CLK_TOP_AUD_I2S_M>;
893 clock-names = "aud_bus_ck",
900 assigned-clocks = <&topckgen CLK_TOP_AUD_SEL>,
901 <&topckgen CLK_TOP_A1SYS_SEL>,
902 <&topckgen CLK_TOP_AUD_L_SEL>,
903 <&topckgen CLK_TOP_A_TUNER_SEL>;
904 assigned-clock-parents = <&apmixedsys CLK_APMIXED_APLL2>,
905 <&topckgen CLK_TOP_APLL2_D4>,
906 <&apmixedsys CLK_APMIXED_APLL2>,
907 <&topckgen CLK_TOP_APLL2_D4>;
912 compatible = "mediatek,mt7986-mmc",
913 "mediatek,mt7981-mmc";
914 reg = <0 0x11230000 0 0x1000>,
915 <0 0x11D60000 0 0x1000>;
916 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
917 clocks = <&infracfg CLK_INFRA_MSDC400>,
918 <&infracfg CLK_INFRA_MSDC2_HCK>,
919 <&infracfg CLK_INFRA_66M_MSDC_0_HCK>,
920 <&infracfg CLK_INFRA_133M_MSDC_0_HCK>;
921 assigned-clocks = <&topckgen CLK_TOP_EMMC_250M_SEL>,
922 <&topckgen CLK_TOP_EMMC_400M_SEL>;
923 assigned-clock-parents = <&topckgen CLK_TOP_NET1PLL_D5_D2>,
924 <&apmixedsys CLK_APMIXED_MSDCPLL>;
925 clock-names = "source",
929 #address-cells = <1>;
934 pcie2: pcie@11280000 {
935 compatible = "mediatek,mt7988-pcie",
936 "mediatek,mt7986-pcie",
937 "mediatek,mt8192-pcie";
938 reg = <0 0x11280000 0 0x2000>;
939 reg-names = "pcie-mac";
940 ranges = <0x81000000 0x00 0x20000000 0x00
941 0x20000000 0x00 0x00200000>,
942 <0x82000000 0x00 0x20200000 0x00
943 0x20200000 0x00 0x07e00000>;
945 linux,pci-domain = <3>;
946 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
947 bus-range = <0x00 0xff>;
948 clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P2>,
949 <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P2>,
950 <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P2>,
951 <&infracfg CLK_INFRA_133M_PCIE_CK_P2>,
952 <&topckgen CLK_TOP_PEXTP_P2_SEL>;
953 clock-names = "pl_250m", "tl_26m", "peri_26m",
954 "top_133m", "pextp_clk";
955 pinctrl-names = "default";
956 pinctrl-0 = <&pcie2_pins>;
957 phys = <&xphyu3port0 PHY_TYPE_PCIE>;
958 phy-names = "pcie-phy";
959 #interrupt-cells = <1>;
960 interrupt-map-mask = <0 0 0 0x7>;
961 interrupt-map = <0 0 0 1 &pcie_intc2 0>,
962 <0 0 0 2 &pcie_intc2 1>,
963 <0 0 0 3 &pcie_intc2 2>,
964 <0 0 0 4 &pcie_intc2 3>;
965 #address-cells = <3>;
969 pcie_intc2: interrupt-controller {
970 #address-cells = <0>;
971 #interrupt-cells = <1>;
972 interrupt-controller;
976 pcie3: pcie@11290000 {
977 compatible = "mediatek,mt7988-pcie",
978 "mediatek,mt7986-pcie",
979 "mediatek,mt8192-pcie";
980 reg = <0 0x11290000 0 0x2000>;
981 reg-names = "pcie-mac";
982 ranges = <0x81000000 0x00 0x28000000 0x00
983 0x28000000 0x00 0x00200000>,
984 <0x82000000 0x00 0x28200000 0x00
985 0x28200000 0x00 0x07e00000>;
987 linux,pci-domain = <2>;
988 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
989 bus-range = <0x00 0xff>;
990 clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P3>,
991 <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P3>,
992 <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P3>,
993 <&infracfg CLK_INFRA_133M_PCIE_CK_P3>,
994 <&topckgen CLK_TOP_PEXTP_P3_SEL>;
995 clock-names = "pl_250m", "tl_26m", "peri_26m",
996 "top_133m", "pextp_clk";
997 pinctrl-names = "default";
998 pinctrl-0 = <&pcie3_pins>;
999 #interrupt-cells = <1>;
1000 interrupt-map-mask = <0 0 0 0x7>;
1001 interrupt-map = <0 0 0 1 &pcie_intc3 0>,
1002 <0 0 0 2 &pcie_intc3 1>,
1003 <0 0 0 3 &pcie_intc3 2>,
1004 <0 0 0 4 &pcie_intc3 3>;
1005 #address-cells = <3>;
1007 status = "disabled";
1009 pcie_intc3: interrupt-controller {
1010 #address-cells = <0>;
1011 #interrupt-cells = <1>;
1012 interrupt-controller;
1016 pcie0: pcie@11300000 {
1017 compatible = "mediatek,mt7988-pcie",
1018 "mediatek,mt7986-pcie",
1019 "mediatek,mt8192-pcie";
1020 reg = <0 0x11300000 0 0x2000>;
1021 reg-names = "pcie-mac";
1022 ranges = <0x81000000 0x00 0x30000000 0x00
1023 0x30000000 0x00 0x00200000>,
1024 <0x82000000 0x00 0x30200000 0x00
1025 0x30200000 0x00 0x07e00000>;
1026 device_type = "pci";
1027 linux,pci-domain = <0>;
1028 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
1029 bus-range = <0x00 0xff>;
1030 clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P0>,
1031 <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P0>,
1032 <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P0>,
1033 <&infracfg CLK_INFRA_133M_PCIE_CK_P0>,
1034 <&topckgen CLK_TOP_PEXTP_P0_SEL>;
1035 clock-names = "pl_250m", "tl_26m", "peri_26m",
1036 "top_133m", "pextp_clk";
1037 pinctrl-names = "default";
1038 pinctrl-0 = <&pcie0_pins>;
1039 #interrupt-cells = <1>;
1040 interrupt-map-mask = <0 0 0 0x7>;
1041 interrupt-map = <0 0 0 1 &pcie_intc0 0>,
1042 <0 0 0 2 &pcie_intc0 1>,
1043 <0 0 0 3 &pcie_intc0 2>,
1044 <0 0 0 4 &pcie_intc0 3>;
1045 #address-cells = <3>;
1047 status = "disabled";
1049 pcie_intc0: interrupt-controller {
1050 #address-cells = <0>;
1051 #interrupt-cells = <1>;
1052 interrupt-controller;
1056 pcie1: pcie@11310000 {
1057 compatible = "mediatek,mt7988-pcie",
1058 "mediatek,mt7986-pcie",
1059 "mediatek,mt8192-pcie";
1060 reg = <0 0x11310000 0 0x2000>;
1061 reg-names = "pcie-mac";
1062 ranges = <0x81000000 0x00 0x38000000 0x00
1063 0x38000000 0x00 0x00200000>,
1064 <0x82000000 0x00 0x38200000 0x00
1065 0x38200000 0x00 0x07e00000>;
1066 device_type = "pci";
1067 linux,pci-domain = <1>;
1068 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
1069 bus-range = <0x00 0xff>;
1070 clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P1>,
1071 <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P1>,
1072 <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P1>,
1073 <&infracfg CLK_INFRA_133M_PCIE_CK_P1>,
1074 <&topckgen CLK_TOP_PEXTP_P1_SEL>;
1075 clock-names = "pl_250m", "tl_26m", "peri_26m",
1076 "top_133m", "pextp_clk";
1077 pinctrl-names = "default";
1078 pinctrl-0 = <&pcie1_pins>;
1079 #interrupt-cells = <1>;
1080 interrupt-map-mask = <0 0 0 0x7>;
1081 interrupt-map = <0 0 0 1 &pcie_intc1 0>,
1082 <0 0 0 2 &pcie_intc1 1>,
1083 <0 0 0 3 &pcie_intc1 2>,
1084 <0 0 0 4 &pcie_intc1 3>;
1085 #address-cells = <3>;
1087 status = "disabled";
1089 pcie_intc1: interrupt-controller {
1090 #address-cells = <0>;
1091 #interrupt-cells = <1>;
1092 interrupt-controller;
1096 tphy: tphy@11c50000 {
1097 compatible = "mediatek,mt7988",
1098 "mediatek,generic-tphy-v2";
1100 #address-cells = <2>;
1102 status = "disabled";
1104 tphyu2port0: usb-phy@11c50000 {
1105 reg = <0 0x11c50000 0 0x700>;
1106 clocks = <&infracfg CLK_INFRA_USB_UTMI_CK_P1>;
1107 clock-names = "ref";
1111 tphyu3port0: usb-phy@11c50700 {
1112 reg = <0 0x11c50700 0 0x900>;
1113 clocks = <&infracfg CLK_INFRA_USB_PIPE_CK_P1>;
1114 clock-names = "ref";
1116 mediatek,usb3-pll-ssc-delta;
1117 mediatek,usb3-pll-ssc-delta1;
1121 topmisc: topmisc@11d10000 {
1122 compatible = "mediatek,mt7988-topmisc", "syscon",
1123 "mediatek,mt7988-power-controller";
1124 reg = <0 0x11d10000 0 0x10000>;
1126 #power-domain-cells = <1>;
1127 #address-cells = <1>;
1131 xphy: xphy@11e10000 {
1132 compatible = "mediatek,mt7988",
1135 #address-cells = <2>;
1137 status = "disabled";
1139 xphyu2port0: usb-phy@11e10000 {
1140 reg = <0 0x11e10000 0 0x400>;
1141 clocks = <&infracfg CLK_INFRA_USB_UTMI>;
1142 clock-names = "ref";
1146 xphyu3port0: usb-phy@11e13000 {
1147 reg = <0 0x11e13400 0 0x500>;
1148 clocks = <&infracfg CLK_INFRA_USB_PIPE>;
1149 clock-names = "ref";
1151 mediatek,syscon-type = <&topmisc 0x218 0>;
1155 xfi_tphy0: phy@11f20000 {
1156 compatible = "mediatek,mt7988-xfi-tphy";
1157 reg = <0 0x11f20000 0 0x10000>;
1158 resets = <&watchdog MT7988_TOPRGU_XFI_PEXTP0_GRST>;
1159 clocks = <&xfi_pll CLK_XFIPLL_PLL_EN>, <&topckgen CLK_TOP_XFI_PHY_0_XTAL_SEL>;
1160 clock-names = "xfipll", "topxtal";
1161 mediatek,usxgmii-performance-errata;
1165 xfi_tphy1: phy@11f30000 {
1166 compatible = "mediatek,mt7988-xfi-tphy";
1167 reg = <0 0x11f30000 0 0x10000>;
1168 resets = <&watchdog MT7988_TOPRGU_XFI_PEXTP1_GRST>;
1169 clocks = <&xfi_pll CLK_XFIPLL_PLL_EN>, <&topckgen CLK_TOP_XFI_PHY_1_XTAL_SEL>;
1170 clock-names = "xfipll", "topxtal";
1174 xfi_pll: clock-controller@11f40000 {
1175 compatible = "mediatek,mt7988-xfi-pll";
1176 reg = <0 0x11f40000 0 0x1000>;
1177 resets = <&watchdog MT7988_TOPRGU_XFI_PLL_GRST>;
1181 efuse: efuse@11f50000 {
1182 compatible = "mediatek,efuse";
1183 reg = <0 0x11f50000 0 0x1000>;
1184 #address-cells = <1>;
1187 lvts_calibration: calib@918 {
1191 phy_calibration_p0: calib@940 {
1195 phy_calibration_p1: calib@954 {
1199 phy_calibration_p2: calib@968 {
1203 phy_calibration_p3: calib@97c {
1207 cpufreq_calibration: calib@278 {
1212 ethsys: syscon@15000000 {
1213 compatible = "mediatek,mt7988-ethsys", "syscon";
1214 reg = <0 0x15000000 0 0x1000>;
1217 #address-cells = <1>;
1221 switch: switch@15020000 {
1222 compatible = "mediatek,mt7988-switch";
1223 reg = <0 0x15020000 0 0x8000>;
1224 interrupt-controller;
1225 #interrupt-cells = <1>;
1226 interrupt-parent = <&gic>;
1227 interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
1228 resets = <ðwarp MT7988_ETHWARP_RST_SWITCH>;
1229 #address-cells = <1>;
1233 #address-cells = <1>;
1239 phy-mode = "internal";
1240 phy-handle = <&gsw_phy0>;
1246 phy-mode = "internal";
1247 phy-handle = <&gsw_phy1>;
1253 phy-mode = "internal";
1254 phy-handle = <&gsw_phy2>;
1260 phy-mode = "internal";
1261 phy-handle = <&gsw_phy3>;
1266 ethernet = <&gmac0>;
1267 phy-mode = "internal";
1278 #address-cells = <1>;
1280 mediatek,pio = <&pio>;
1282 gsw_phy0: ethernet-phy@0 {
1283 compatible = "ethernet-phy-ieee802.3-c22";
1285 phy-mode = "internal";
1286 nvmem-cells = <&phy_calibration_p0>;
1287 nvmem-cell-names = "phy-cal-data";
1290 #address-cells = <1>;
1293 gsw_phy0_led0: gsw-phy0-led0@0 {
1295 function = LED_FUNCTION_LAN;
1296 status = "disabled";
1299 gsw_phy0_led1: gsw-phy0-led1@1 {
1301 function = LED_FUNCTION_LAN;
1302 status = "disabled";
1307 gsw_phy1: ethernet-phy@1 {
1308 compatible = "ethernet-phy-ieee802.3-c22";
1310 phy-mode = "internal";
1311 nvmem-cells = <&phy_calibration_p1>;
1312 nvmem-cell-names = "phy-cal-data";
1315 #address-cells = <1>;
1318 gsw_phy1_led0: gsw-phy1-led0@0 {
1320 function = LED_FUNCTION_LAN;
1321 status = "disabled";
1324 gsw_phy1_led1: gsw-phy1-led1@1 {
1326 function = LED_FUNCTION_LAN;
1327 status = "disabled";
1332 gsw_phy2: ethernet-phy@2 {
1333 compatible = "ethernet-phy-ieee802.3-c22";
1335 phy-mode = "internal";
1336 nvmem-cells = <&phy_calibration_p2>;
1337 nvmem-cell-names = "phy-cal-data";
1340 #address-cells = <1>;
1343 gsw_phy2_led0: gsw-phy2-led0@0 {
1345 function = LED_FUNCTION_LAN;
1346 status = "disabled";
1349 gsw_phy2_led1: gsw-phy2-led1@1 {
1351 function = LED_FUNCTION_LAN;
1352 status = "disabled";
1357 gsw_phy3: ethernet-phy@3 {
1358 compatible = "ethernet-phy-ieee802.3-c22";
1360 phy-mode = "internal";
1361 nvmem-cells = <&phy_calibration_p3>;
1362 nvmem-cell-names = "phy-cal-data";
1365 #address-cells = <1>;
1368 gsw_phy3_led0: gsw-phy3-led0@0 {
1370 function = LED_FUNCTION_LAN;
1371 status = "disabled";
1374 gsw_phy3_led1: gsw-phy3-led1@1 {
1376 function = LED_FUNCTION_LAN;
1377 status = "disabled";
1384 ethwarp: clock-controller@15031000 {
1385 compatible = "mediatek,mt7988-ethwarp";
1386 reg = <0 0x15031000 0 0x1000>;
1391 eth: ethernet@15100000 {
1392 compatible = "mediatek,mt7988-eth";
1393 reg = <0 0x15100000 0 0x80000>,
1394 <0 0x15400000 0 0x380000>;
1395 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
1396 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
1397 <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
1398 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
1399 clocks = <ðsys CLK_ETHDMA_XGP1_EN>,
1400 <ðsys CLK_ETHDMA_XGP2_EN>,
1401 <ðsys CLK_ETHDMA_XGP3_EN>,
1402 <ðsys CLK_ETHDMA_FE_EN>,
1403 <ðsys CLK_ETHDMA_GP2_EN>,
1404 <ðsys CLK_ETHDMA_GP1_EN>,
1405 <ðsys CLK_ETHDMA_GP3_EN>,
1406 <ðsys CLK_ETHDMA_ESW_EN>,
1407 <ðsys CLK_ETHDMA_CRYPT0_EN>,
1408 <ðwarp CLK_ETHWARP_WOCPU2_EN>,
1409 <ðwarp CLK_ETHWARP_WOCPU1_EN>,
1410 <ðwarp CLK_ETHWARP_WOCPU0_EN>,
1411 <&topckgen CLK_TOP_ETH_GMII_SEL>,
1412 <&topckgen CLK_TOP_ETH_REFCK_50M_SEL>,
1413 <&topckgen CLK_TOP_ETH_SYS_200M_SEL>,
1414 <&topckgen CLK_TOP_ETH_SYS_SEL>,
1415 <&topckgen CLK_TOP_ETH_XGMII_SEL>,
1416 <&topckgen CLK_TOP_ETH_MII_SEL>,
1417 <&topckgen CLK_TOP_NETSYS_SEL>,
1418 <&topckgen CLK_TOP_NETSYS_500M_SEL>,
1419 <&topckgen CLK_TOP_NETSYS_PAO_2X_SEL>,
1420 <&topckgen CLK_TOP_NETSYS_SYNC_250M_SEL>,
1421 <&topckgen CLK_TOP_NETSYS_PPEFB_250M_SEL>,
1422 <&topckgen CLK_TOP_NETSYS_WARP_SEL>;
1423 clock-names = "xgp1", "xgp2", "xgp3", "fe", "gp2", "gp1",
1424 "gp3", "esw", "crypto",
1425 "ethwarp_wocpu2", "ethwarp_wocpu1",
1426 "ethwarp_wocpu0", "top_eth_gmii_sel",
1427 "top_eth_refck_50m_sel", "top_eth_sys_200m_sel",
1428 "top_eth_sys_sel", "top_eth_xgmii_sel",
1429 "top_eth_mii_sel", "top_netsys_sel",
1430 "top_netsys_500m_sel", "top_netsys_pao_2x_sel",
1431 "top_netsys_sync_250m_sel",
1432 "top_netsys_ppefb_250m_sel",
1433 "top_netsys_warp_sel";
1434 assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>,
1435 <&topckgen CLK_TOP_NETSYS_GSW_SEL>,
1436 <&topckgen CLK_TOP_USXGMII_SBUS_0_SEL>,
1437 <&topckgen CLK_TOP_USXGMII_SBUS_1_SEL>,
1438 <&topckgen CLK_TOP_SGM_0_SEL>,
1439 <&topckgen CLK_TOP_SGM_1_SEL>;
1440 assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>,
1441 <&topckgen CLK_TOP_NET1PLL_D4>,
1442 <&topckgen CLK_TOP_NET1PLL_D8_D4>,
1443 <&topckgen CLK_TOP_NET1PLL_D8_D4>,
1444 <&apmixedsys CLK_APMIXED_SGMPLL>,
1445 <&apmixedsys CLK_APMIXED_SGMPLL>;
1446 mediatek,ethsys = <ðsys>;
1447 mediatek,infracfg = <&topmisc>;
1448 #address-cells = <1>;
1452 compatible = "mediatek,eth-mac";
1454 phy-mode = "internal";
1455 status = "disabled";
1465 compatible = "mediatek,eth-mac";
1467 status = "disabled";
1468 pcs-handle = <&sgmiipcs1>, <&usxgmiisys1>;
1469 phys = <&xfi_tphy1>;
1473 compatible = "mediatek,eth-mac";
1475 status = "disabled";
1476 pcs-handle = <&sgmiipcs0>, <&usxgmiisys0>;
1477 phys = <&xfi_tphy0>;
1480 mdio_bus: mdio-bus {
1481 #address-cells = <1>;
1484 /* internal 2.5G PHY */
1485 int_2p5g_phy: ethernet-phy@15 {
1486 compatible = "ethernet-phy-ieee802.3-c45";
1488 phy-mode = "internal";
1493 crypto: crypto@15600000 {
1494 compatible = "inside-secure,safexcel-eip197b";
1495 reg = <0 0x15600000 0 0x180000>;
1496 interrupts = <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
1497 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
1498 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
1499 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>;
1500 interrupt-names = "ring0", "ring1", "ring2", "ring3";
1506 cpu_thermal: cpu-thermal {
1507 polling-delay-passive = <1000>;
1508 polling-delay = <1000>;
1509 thermal-sensors = <&lvts 0>;
1512 cpu_trip_crit: crit {
1513 temperature = <125000>;
1514 hysteresis = <2000>;
1519 temperature = <120000>;
1520 hysteresis = <2000>;
1524 cpu_trip_active_high: active-high {
1525 temperature = <115000>;
1526 hysteresis = <2000>;
1530 cpu_trip_active_med: active-med {
1531 temperature = <85000>;
1532 hysteresis = <2000>;
1536 cpu_trip_active_low: active-low {
1537 temperature = <40000>;
1538 hysteresis = <2000>;
1545 /* active: set fan to cooling level 2 */
1546 cooling-device = <&fan 3 3>;
1547 trip = <&cpu_trip_active_high>;
1551 /* active: set fan to cooling level 1 */
1552 cooling-device = <&fan 2 2>;
1553 trip = <&cpu_trip_active_med>;
1557 /* passive: set fan to cooling level 0 */
1558 cooling-device = <&fan 1 1>;
1559 trip = <&cpu_trip_active_low>;
1566 compatible = "arm,armv8-timer";
1567 interrupt-parent = <&gic>;
1568 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
1569 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
1570 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
1571 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;