1 // SPDX-License-Identifier: GPL-2.0+
2 #include <linux/bitfield.h>
3 #include <linux/firmware.h>
4 #include <linux/module.h>
5 #include <linux/nvmem-consumer.h>
6 #include <linux/of_address.h>
7 #include <linux/of_platform.h>
8 #include <linux/pinctrl/consumer.h>
10 #include <linux/pm_domain.h>
11 #include <linux/pm_runtime.h>
13 #define MT7988_2P5GE_PMB "mediatek/mt7988/i2p5ge-phy-pmb.bin"
15 #define MD32_EN BIT(0)
16 #define PMEM_PRIORITY BIT(8)
17 #define DMEM_PRIORITY BIT(16)
19 #define BASE100T_STATUS_EXTEND 0x10
20 #define BASE1000T_STATUS_EXTEND 0x11
21 #define EXTEND_CTRL_AND_STATUS 0x16
23 #define PHY_AUX_CTRL_STATUS 0x1d
24 #define PHY_AUX_DPX_MASK GENMASK(5, 5)
25 #define PHY_AUX_SPEED_MASK GENMASK(4, 2)
27 /* Registers on MDIO_MMD_VEND1 */
28 #define MTK_PHY_LINK_STATUS_MISC 0xa2
29 #define MTK_PHY_FDX_ENABLE BIT(5)
31 #define MTK_PHY_LPI_PCS_DSP_CTRL 0x121
32 #define MTK_PHY_LPI_SIG_EN_LO_THRESH100_MASK GENMASK(12, 8)
34 /* Registers on MDIO_MMD_VEND2 */
35 #define MTK_PHY_LED0_ON_CTRL 0x24
36 #define MTK_PHY_LED0_ON_LINK1000 BIT(0)
37 #define MTK_PHY_LED0_ON_LINK100 BIT(1)
38 #define MTK_PHY_LED0_ON_LINK10 BIT(2)
39 #define MTK_PHY_LED0_ON_LINK2500 BIT(7)
40 #define MTK_PHY_LED0_POLARITY BIT(14)
42 #define MTK_PHY_LED1_ON_CTRL 0x26
43 #define MTK_PHY_LED1_ON_FDX BIT(4)
44 #define MTK_PHY_LED1_ON_HDX BIT(5)
45 #define MTK_PHY_LED1_POLARITY BIT(14)
47 #define MTK_EXT_PAGE_ACCESS 0x1f
48 #define MTK_PHY_PAGE_STANDARD 0x0000
49 #define MTK_PHY_PAGE_EXTENDED_52B5 0x52b5
51 struct mtk_i2p5ge_phy_priv
{
62 static int mtk_2p5ge_phy_read_page(struct phy_device
*phydev
)
64 return __phy_read(phydev
, MTK_EXT_PAGE_ACCESS
);
67 static int mtk_2p5ge_phy_write_page(struct phy_device
*phydev
, int page
)
69 return __phy_write(phydev
, MTK_EXT_PAGE_ACCESS
, page
);
72 static int mt7988_2p5ge_phy_probe(struct phy_device
*phydev
)
74 struct mtk_i2p5ge_phy_priv
*phy_priv
;
76 phy_priv
= devm_kzalloc(&phydev
->mdio
.dev
,
77 sizeof(struct mtk_i2p5ge_phy_priv
), GFP_KERNEL
);
81 phydev
->priv
= phy_priv
;
86 static int mt7988_2p5ge_phy_config_init(struct phy_device
*phydev
)
89 const struct firmware
*fw
;
90 struct device
*dev
= &phydev
->mdio
.dev
;
91 struct device_node
*np
;
92 void __iomem
*pmb_addr
;
93 void __iomem
*md32_en_cfg_base
;
94 struct mtk_i2p5ge_phy_priv
*phy_priv
= phydev
->priv
;
96 struct pinctrl
*pinctrl
;
98 if (!phy_priv
->fw_loaded
) {
99 np
= of_find_compatible_node(NULL
, NULL
, "mediatek,2p5gphy-fw");
102 pmb_addr
= of_iomap(np
, 0);
105 md32_en_cfg_base
= of_iomap(np
, 1);
106 if (!md32_en_cfg_base
)
109 ret
= request_firmware(&fw
, MT7988_2P5GE_PMB
, dev
);
111 dev_err(dev
, "failed to load firmware: %s, ret: %d\n",
112 MT7988_2P5GE_PMB
, ret
);
116 reg
= readw(md32_en_cfg_base
);
118 phy_set_bits(phydev
, 0, BIT(15));
119 usleep_range(10000, 11000);
121 phy_set_bits(phydev
, 0, BIT(11));
123 /* Write magic number to safely stall MCU */
124 phy_write_mmd(phydev
, MDIO_MMD_VEND1
, 0x800e, 0x1100);
125 phy_write_mmd(phydev
, MDIO_MMD_VEND1
, 0x800f, 0x00df);
127 for (i
= 0; i
< fw
->size
- 1; i
+= 4)
128 writel(*((uint32_t *)(fw
->data
+ i
)), pmb_addr
+ i
);
129 release_firmware(fw
);
131 writew(reg
& ~MD32_EN
, md32_en_cfg_base
);
132 writew(reg
| MD32_EN
, md32_en_cfg_base
);
133 phy_set_bits(phydev
, 0, BIT(15));
134 dev_info(dev
, "Firmware loading/trigger ok.\n");
136 phy_priv
->fw_loaded
= true;
140 phy_set_bits_mmd(phydev
, MDIO_MMD_VEND2
, MTK_PHY_LED0_ON_CTRL
,
141 MTK_PHY_LED0_ON_LINK10
|
142 MTK_PHY_LED0_ON_LINK100
|
143 MTK_PHY_LED0_ON_LINK1000
|
144 MTK_PHY_LED0_ON_LINK2500
);
145 phy_set_bits_mmd(phydev
, MDIO_MMD_VEND2
, MTK_PHY_LED1_ON_CTRL
,
146 MTK_PHY_LED1_ON_FDX
| MTK_PHY_LED1_ON_HDX
);
148 pinctrl
= devm_pinctrl_get_select(&phydev
->mdio
.dev
, "i2p5gbe-led");
149 if (IS_ERR(pinctrl
)) {
150 dev_err(&phydev
->mdio
.dev
, "Fail to set LED pins!\n");
151 return PTR_ERR(pinctrl
);
154 phy_modify_mmd(phydev
, MDIO_MMD_VEND1
, MTK_PHY_LPI_PCS_DSP_CTRL
,
155 MTK_PHY_LPI_SIG_EN_LO_THRESH100_MASK
, 0);
157 /* Enable 16-bit next page exchange bit if 1000-BT isn't advertizing */
158 phy_select_page(phydev
, MTK_PHY_PAGE_EXTENDED_52B5
);
159 __phy_write(phydev
, 0x11, 0xfbfa);
160 __phy_write(phydev
, 0x12, 0xc3);
161 __phy_write(phydev
, 0x10, 0x87f8);
162 phy_restore_page(phydev
, MTK_PHY_PAGE_STANDARD
, 0);
167 static int mt7988_2p5ge_phy_config_aneg(struct phy_device
*phydev
)
169 bool changed
= false;
173 if (phydev
->autoneg
== AUTONEG_DISABLE
) {
174 /* Configure half duplex with genphy_setup_forced,
175 * because genphy_c45_pma_setup_forced does not support.
177 return phydev
->duplex
!= DUPLEX_FULL
178 ? genphy_setup_forced(phydev
)
179 : genphy_c45_pma_setup_forced(phydev
);
182 ret
= genphy_c45_an_config_aneg(phydev
);
188 adv
= linkmode_adv_to_mii_ctrl1000_t(phydev
->advertising
);
189 ret
= phy_modify_changed(phydev
, MII_CTRL1000
,
190 ADVERTISE_1000FULL
| ADVERTISE_1000HALF
,
197 return genphy_c45_check_and_restart_aneg(phydev
, changed
);
200 static int mt7988_2p5ge_phy_get_features(struct phy_device
*phydev
)
204 ret
= genphy_read_abilities(phydev
);
208 /* We don't support HDX at MAC layer on mt7988.
209 * So mask phy's HDX capabilities, too.
211 linkmode_set_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT
,
213 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT
,
215 linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT
,
217 linkmode_set_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT
,
219 linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT
, phydev
->supported
);
224 static int mt7988_2p5ge_phy_read_status(struct phy_device
*phydev
)
228 ret
= genphy_update_link(phydev
);
232 phydev
->speed
= SPEED_UNKNOWN
;
233 phydev
->duplex
= DUPLEX_UNKNOWN
;
235 phydev
->asym_pause
= 0;
237 if (phydev
->autoneg
== AUTONEG_ENABLE
&& phydev
->autoneg_complete
) {
238 ret
= genphy_c45_read_lpa(phydev
);
242 /* Read the link partner's 1G advertisement */
243 ret
= phy_read(phydev
, MII_STAT1000
);
246 mii_stat1000_mod_linkmode_lpa_t(phydev
->lp_advertising
, ret
);
247 } else if (phydev
->autoneg
== AUTONEG_DISABLE
) {
248 linkmode_zero(phydev
->lp_advertising
);
251 ret
= phy_read(phydev
, PHY_AUX_CTRL_STATUS
);
255 switch (FIELD_GET(PHY_AUX_SPEED_MASK
, ret
)) {
257 phydev
->speed
= SPEED_10
;
259 case PHY_AUX_SPD_100
:
260 phydev
->speed
= SPEED_100
;
262 case PHY_AUX_SPD_1000
:
263 phydev
->speed
= SPEED_1000
;
265 case PHY_AUX_SPD_2500
:
266 phydev
->speed
= SPEED_2500
;
270 ret
= phy_read_mmd(phydev
, MDIO_MMD_VEND1
, MTK_PHY_LINK_STATUS_MISC
);
274 phydev
->duplex
= (ret
& MTK_PHY_FDX_ENABLE
) ? DUPLEX_FULL
: DUPLEX_HALF
;
275 /* FIXME: The current firmware always enables rate adaptation mode. */
276 phydev
->rate_matching
= RATE_MATCH_PAUSE
;
281 static int mt7988_2p5ge_phy_get_rate_matching(struct phy_device
*phydev
,
282 phy_interface_t iface
)
284 return RATE_MATCH_PAUSE
;
287 static struct phy_driver mtk_gephy_driver
[] = {
289 PHY_ID_MATCH_MODEL(0x00339c11),
290 .name
= "MediaTek MT798x 2.5GbE PHY",
291 .probe
= mt7988_2p5ge_phy_probe
,
292 .config_init
= mt7988_2p5ge_phy_config_init
,
293 .config_aneg
= mt7988_2p5ge_phy_config_aneg
,
294 .get_features
= mt7988_2p5ge_phy_get_features
,
295 .read_status
= mt7988_2p5ge_phy_read_status
,
296 .get_rate_matching
= mt7988_2p5ge_phy_get_rate_matching
,
297 .suspend
= genphy_suspend
,
298 .resume
= genphy_resume
,
299 .read_page
= mtk_2p5ge_phy_read_page
,
300 .write_page
= mtk_2p5ge_phy_write_page
,
304 module_phy_driver(mtk_gephy_driver
);
306 static struct mdio_device_id __maybe_unused mtk_2p5ge_phy_tbl
[] = {
307 { PHY_ID_MATCH_VENDOR(0x00339c00) },
311 MODULE_DESCRIPTION("MediaTek 2.5Gb Ethernet PHY driver");
312 MODULE_AUTHOR("SkyLake Huang <SkyLake.Huang@mediatek.com>");
313 MODULE_LICENSE("GPL");
315 MODULE_DEVICE_TABLE(mdio
, mtk_2p5ge_phy_tbl
);
316 MODULE_FIRMWARE(MT7988_2P5GE_PMB
);