1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 * Copyright (C) 2021 MediaTek Inc.
4 * Author: Sam.Shih <sam.shih@mediatek.com>
8 #include "mt7986a.dtsi"
11 model = "MediaTek MT7986a RFB";
12 compatible = "mediatek,mt7986a-rfb";
19 stdout-path = "serial0:115200n8";
23 reg = <0 0x40000000 0 0x40000000>;
26 reg_1p8v: regulator-1p8v {
27 compatible = "regulator-fixed";
28 regulator-name = "fixed-1.8V";
29 regulator-min-microvolt = <1800000>;
30 regulator-max-microvolt = <1800000>;
35 reg_3p3v: regulator-3p3v {
36 compatible = "regulator-fixed";
37 regulator-name = "fixed-3.3V";
38 regulator-min-microvolt = <3300000>;
39 regulator-max-microvolt = <3300000>;
44 reg_5v: regulator-5v {
45 compatible = "regulator-fixed";
46 regulator-name = "fixed-5V";
47 regulator-min-microvolt = <5000000>;
48 regulator-max-microvolt = <5000000>;
58 compatible = "mediatek,eth-mac";
60 phy-mode = "2500base-x";
70 compatible = "mediatek,eth-mac";
72 phy-mode = "2500base-x";
83 pinctrl-names = "default", "dbdc";
84 pinctrl-0 = <&wf_2g_5g_pins>;
85 pinctrl-1 = <&wf_dbdc_pins>;
90 compatible = "ethernet-phy-id67c9.de0a";
93 reset-gpios = <&pio 6 1>;
94 reset-deassert-us = <20000>;
98 compatible = "ethernet-phy-id67c9.de0a";
103 compatible = "mediatek,mt7531";
105 reset-gpios = <&pio 5 0>;
114 pinctrl-names = "default", "state_uhs";
115 pinctrl-0 = <&mmc0_pins_default>;
116 pinctrl-1 = <&mmc0_pins_uhs>;
118 max-frequency = <200000000>;
122 hs400-ds-delay = <0x14014>;
123 vmmc-supply = <®_3p3v>;
124 vqmmc-supply = <®_1p8v>;
132 pinctrl-names = "default";
133 pinctrl-0 = <&pcie_pins>;
142 mmc0_pins_default: mmc0-pins {
148 pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
149 "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
150 "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
152 drive-strength = <4>;
153 mediatek,pull-up-adv = <1>; /* pull-up 10K */
157 drive-strength = <6>;
158 mediatek,pull-down-adv = <2>; /* pull-down 50K */
162 mediatek,pull-down-adv = <2>; /* pull-down 50K */
166 drive-strength = <4>;
167 mediatek,pull-up-adv = <1>; /* pull-up 10K */
171 mmc0_pins_uhs: mmc0-uhs-pins {
177 pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
178 "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
179 "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
181 drive-strength = <4>;
182 mediatek,pull-up-adv = <1>; /* pull-up 10K */
186 drive-strength = <6>;
187 mediatek,pull-down-adv = <2>; /* pull-down 50K */
191 mediatek,pull-down-adv = <2>; /* pull-down 50K */
195 drive-strength = <4>;
196 mediatek,pull-up-adv = <1>; /* pull-up 10K */
200 pcie_pins: pcie-pins {
203 groups = "pcie_clk", "pcie_wake", "pcie_pereset";
207 spic_pins_g2: spic-pins-29-to-32 {
214 spi_flash_pins: spi-flash-pins-33-to-38 {
217 groups = "spi0", "spi0_wp_hold";
220 pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP";
221 drive-strength = <8>;
222 mediatek,pull-up-adv = <0>; /* bias-disable */
225 pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO";
226 drive-strength = <8>;
227 mediatek,pull-down-adv = <0>; /* bias-disable */
231 uart1_pins: uart1-pins {
238 uart2_pins: uart2-pins {
245 wf_2g_5g_pins: wf_2g_5g-pins {
248 groups = "wf_2g", "wf_5g";
251 pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
252 "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
253 "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
254 "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
255 "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
256 "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
257 "WF1_TOP_CLK", "WF1_TOP_DATA";
258 drive-strength = <4>;
262 wf_dbdc_pins: wf_dbdc-pins {
268 pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
269 "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
270 "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
271 "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
272 "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
273 "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
274 "WF1_TOP_CLK", "WF1_TOP_DATA";
275 drive-strength = <4>;
281 pinctrl-names = "default";
282 pinctrl-0 = <&spi_flash_pins>;
284 #address-cells = <1>;
290 pinctrl-names = "default";
291 pinctrl-0 = <&spic_pins_g2>;
294 proslic_spi: proslic_spi@0 {
295 compatible = "silabs,proslic_spi";
297 spi-max-frequency = <10000000>;
301 debug_level = <4>; /* 1 = TRC, 2 = DBG, 4 = ERR */
302 reset_gpio = <&pio 7 0>;
303 ig,enable-spi = <1>; /* 1: Enable, 0: Disable */
308 phy-mode = "2500base-x";
309 phy-connection-type = "2500base-x";
310 phy-handle = <&phy6>;
315 #address-cells = <1>;
347 phy-mode = "2500base-x";
348 phy-handle = <&phy5>;
354 phy-mode = "2500base-x";
366 vusb33-supply = <®_3p3v>;
367 vbus-supply = <®_5v>;
376 pinctrl-names = "default";
377 pinctrl-0 = <&uart1_pins>;
382 pinctrl-names = "default";
383 pinctrl-0 = <&uart2_pins>;