1 From f851b4ea6cae9fd5875036b6d3968375882ce56b Mon Sep 17 00:00:00 2001
2 From: James Liao <jamesjj.liao@mediatek.com>
3 Date: Thu, 23 Apr 2015 10:35:39 +0200
4 Subject: [PATCH 02/76] clk: mediatek: Add initial common clock support for
7 This patch adds common clock support for Mediatek SoCs, including plls,
10 Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
11 Signed-off-by: Henry Chen <henryc.chen@mediatek.com>
12 Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
14 drivers/clk/Makefile | 1 +
15 drivers/clk/mediatek/Makefile | 1 +
16 drivers/clk/mediatek/clk-gate.c | 137 ++++++++++++++++
17 drivers/clk/mediatek/clk-gate.h | 49 ++++++
18 drivers/clk/mediatek/clk-mtk.c | 220 ++++++++++++++++++++++++++
19 drivers/clk/mediatek/clk-mtk.h | 159 +++++++++++++++++++
20 drivers/clk/mediatek/clk-pll.c | 332 +++++++++++++++++++++++++++++++++++++++
21 7 files changed, 899 insertions(+)
22 create mode 100644 drivers/clk/mediatek/Makefile
23 create mode 100644 drivers/clk/mediatek/clk-gate.c
24 create mode 100644 drivers/clk/mediatek/clk-gate.h
25 create mode 100644 drivers/clk/mediatek/clk-mtk.c
26 create mode 100644 drivers/clk/mediatek/clk-mtk.h
27 create mode 100644 drivers/clk/mediatek/clk-pll.c
29 --- a/drivers/clk/Makefile
30 +++ b/drivers/clk/Makefile
31 @@ -51,6 +51,7 @@ obj-$(CONFIG_ARCH_HI3xxx) += hisilicon/
32 obj-$(CONFIG_ARCH_HIP04) += hisilicon/
33 obj-$(CONFIG_ARCH_HIX5HD2) += hisilicon/
34 obj-$(CONFIG_COMMON_CLK_KEYSTONE) += keystone/
35 +obj-$(CONFIG_ARCH_MEDIATEK) += mediatek/
36 ifeq ($(CONFIG_COMMON_CLK), y)
37 obj-$(CONFIG_ARCH_MMP) += mmp/
40 +++ b/drivers/clk/mediatek/Makefile
42 +obj-y += clk-mtk.o clk-pll.o clk-gate.o
44 +++ b/drivers/clk/mediatek/clk-gate.c
47 + * Copyright (c) 2014 MediaTek Inc.
48 + * Author: James Liao <jamesjj.liao@mediatek.com>
50 + * This program is free software; you can redistribute it and/or modify
51 + * it under the terms of the GNU General Public License version 2 as
52 + * published by the Free Software Foundation.
54 + * This program is distributed in the hope that it will be useful,
55 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
56 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
57 + * GNU General Public License for more details.
60 +#include <linux/of.h>
61 +#include <linux/of_address.h>
63 +#include <linux/io.h>
64 +#include <linux/slab.h>
65 +#include <linux/delay.h>
66 +#include <linux/clkdev.h>
69 +#include "clk-gate.h"
71 +static int mtk_cg_bit_is_cleared(struct clk_hw *hw)
73 + struct mtk_clk_gate *cg = to_clk_gate(hw);
76 + regmap_read(cg->regmap, cg->sta_ofs, &val);
78 + val &= BIT(cg->bit);
83 +static int mtk_cg_bit_is_set(struct clk_hw *hw)
85 + struct mtk_clk_gate *cg = to_clk_gate(hw);
88 + regmap_read(cg->regmap, cg->sta_ofs, &val);
90 + val &= BIT(cg->bit);
95 +static void mtk_cg_set_bit(struct clk_hw *hw)
97 + struct mtk_clk_gate *cg = to_clk_gate(hw);
99 + regmap_write(cg->regmap, cg->set_ofs, BIT(cg->bit));
102 +static void mtk_cg_clr_bit(struct clk_hw *hw)
104 + struct mtk_clk_gate *cg = to_clk_gate(hw);
106 + regmap_write(cg->regmap, cg->clr_ofs, BIT(cg->bit));
109 +static int mtk_cg_enable(struct clk_hw *hw)
111 + mtk_cg_clr_bit(hw);
116 +static void mtk_cg_disable(struct clk_hw *hw)
118 + mtk_cg_set_bit(hw);
121 +static int mtk_cg_enable_inv(struct clk_hw *hw)
123 + mtk_cg_set_bit(hw);
128 +static void mtk_cg_disable_inv(struct clk_hw *hw)
130 + mtk_cg_clr_bit(hw);
133 +const struct clk_ops mtk_clk_gate_ops_setclr = {
134 + .is_enabled = mtk_cg_bit_is_cleared,
135 + .enable = mtk_cg_enable,
136 + .disable = mtk_cg_disable,
139 +const struct clk_ops mtk_clk_gate_ops_setclr_inv = {
140 + .is_enabled = mtk_cg_bit_is_set,
141 + .enable = mtk_cg_enable_inv,
142 + .disable = mtk_cg_disable_inv,
145 +struct clk *mtk_clk_register_gate(
147 + const char *parent_name,
148 + struct regmap *regmap,
153 + const struct clk_ops *ops)
155 + struct mtk_clk_gate *cg;
157 + struct clk_init_data init;
159 + cg = kzalloc(sizeof(*cg), GFP_KERNEL);
161 + return ERR_PTR(-ENOMEM);
164 + init.flags = CLK_SET_RATE_PARENT;
165 + init.parent_names = parent_name ? &parent_name : NULL;
166 + init.num_parents = parent_name ? 1 : 0;
169 + cg->regmap = regmap;
170 + cg->set_ofs = set_ofs;
171 + cg->clr_ofs = clr_ofs;
172 + cg->sta_ofs = sta_ofs;
175 + cg->hw.init = &init;
177 + clk = clk_register(NULL, &cg->hw);
184 +++ b/drivers/clk/mediatek/clk-gate.h
187 + * Copyright (c) 2014 MediaTek Inc.
188 + * Author: James Liao <jamesjj.liao@mediatek.com>
190 + * This program is free software; you can redistribute it and/or modify
191 + * it under the terms of the GNU General Public License version 2 as
192 + * published by the Free Software Foundation.
194 + * This program is distributed in the hope that it will be useful,
195 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
196 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
197 + * GNU General Public License for more details.
200 +#ifndef __DRV_CLK_GATE_H
201 +#define __DRV_CLK_GATE_H
203 +#include <linux/regmap.h>
204 +#include <linux/clk.h>
205 +#include <linux/clk-provider.h>
207 +struct mtk_clk_gate {
209 + struct regmap *regmap;
216 +static inline struct mtk_clk_gate *to_clk_gate(struct clk_hw *hw)
218 + return container_of(hw, struct mtk_clk_gate, hw);
221 +extern const struct clk_ops mtk_clk_gate_ops_setclr;
222 +extern const struct clk_ops mtk_clk_gate_ops_setclr_inv;
224 +struct clk *mtk_clk_register_gate(
226 + const char *parent_name,
227 + struct regmap *regmap,
232 + const struct clk_ops *ops);
234 +#endif /* __DRV_CLK_GATE_H */
236 +++ b/drivers/clk/mediatek/clk-mtk.c
239 + * Copyright (c) 2014 MediaTek Inc.
240 + * Author: James Liao <jamesjj.liao@mediatek.com>
242 + * This program is free software; you can redistribute it and/or modify
243 + * it under the terms of the GNU General Public License version 2 as
244 + * published by the Free Software Foundation.
246 + * This program is distributed in the hope that it will be useful,
247 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
248 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
249 + * GNU General Public License for more details.
252 +#include <linux/of.h>
253 +#include <linux/of_address.h>
254 +#include <linux/err.h>
255 +#include <linux/io.h>
256 +#include <linux/slab.h>
257 +#include <linux/delay.h>
258 +#include <linux/clkdev.h>
259 +#include <linux/mfd/syscon.h>
261 +#include "clk-mtk.h"
262 +#include "clk-gate.h"
264 +struct clk_onecell_data *mtk_alloc_clk_data(unsigned int clk_num)
267 + struct clk_onecell_data *clk_data;
269 + clk_data = kzalloc(sizeof(*clk_data), GFP_KERNEL);
273 + clk_data->clks = kcalloc(clk_num, sizeof(*clk_data->clks), GFP_KERNEL);
274 + if (!clk_data->clks)
277 + clk_data->clk_num = clk_num;
279 + for (i = 0; i < clk_num; i++)
280 + clk_data->clks[i] = ERR_PTR(-ENOENT);
289 +void mtk_clk_register_factors(const struct mtk_fixed_factor *clks, int num,
290 + struct clk_onecell_data *clk_data)
295 + for (i = 0; i < num; i++) {
296 + const struct mtk_fixed_factor *ff = &clks[i];
298 + clk = clk_register_fixed_factor(NULL, ff->name, ff->parent_name,
299 + CLK_SET_RATE_PARENT, ff->mult, ff->div);
302 + pr_err("Failed to register clk %s: %ld\n",
303 + ff->name, PTR_ERR(clk));
308 + clk_data->clks[ff->id] = clk;
312 +int mtk_clk_register_gates(struct device_node *node, const struct mtk_gate *clks,
313 + int num, struct clk_onecell_data *clk_data)
317 + struct regmap *regmap;
322 + regmap = syscon_node_to_regmap(node);
323 + if (IS_ERR(regmap)) {
324 + pr_err("Cannot find regmap for %s: %ld\n", node->full_name,
326 + return PTR_ERR(regmap);
329 + for (i = 0; i < num; i++) {
330 + const struct mtk_gate *gate = &clks[i];
332 + clk = mtk_clk_register_gate(gate->name, gate->parent_name,
334 + gate->regs->set_ofs,
335 + gate->regs->clr_ofs,
336 + gate->regs->sta_ofs,
337 + gate->shift, gate->ops);
340 + pr_err("Failed to register clk %s: %ld\n",
341 + gate->name, PTR_ERR(clk));
345 + clk_data->clks[gate->id] = clk;
351 +struct clk *mtk_clk_register_composite(const struct mtk_composite *mc,
352 + void __iomem *base, spinlock_t *lock)
355 + struct clk_mux *mux = NULL;
356 + struct clk_gate *gate = NULL;
357 + struct clk_divider *div = NULL;
358 + struct clk_hw *mux_hw = NULL, *gate_hw = NULL, *div_hw = NULL;
359 + const struct clk_ops *mux_ops = NULL, *gate_ops = NULL, *div_ops = NULL;
360 + const char * const *parent_names;
361 + const char *parent;
365 + if (mc->mux_shift >= 0) {
366 + mux = kzalloc(sizeof(*mux), GFP_KERNEL);
368 + return ERR_PTR(-ENOMEM);
370 + mux->reg = base + mc->mux_reg;
371 + mux->mask = BIT(mc->mux_width) - 1;
372 + mux->shift = mc->mux_shift;
376 + mux_ops = &clk_mux_ops;
378 + parent_names = mc->parent_names;
379 + num_parents = mc->num_parents;
381 + parent = mc->parent;
382 + parent_names = &parent;
386 + if (mc->gate_shift >= 0) {
387 + gate = kzalloc(sizeof(*gate), GFP_KERNEL);
393 + gate->reg = base + mc->gate_reg;
394 + gate->bit_idx = mc->gate_shift;
395 + gate->flags = CLK_GATE_SET_TO_DISABLE;
398 + gate_hw = &gate->hw;
399 + gate_ops = &clk_gate_ops;
402 + if (mc->divider_shift >= 0) {
403 + div = kzalloc(sizeof(*div), GFP_KERNEL);
409 + div->reg = base + mc->divider_reg;
410 + div->shift = mc->divider_shift;
411 + div->width = mc->divider_width;
415 + div_ops = &clk_divider_ops;
418 + clk = clk_register_composite(NULL, mc->name, parent_names, num_parents,
433 + return ERR_PTR(ret);
436 +void mtk_clk_register_composites(const struct mtk_composite *mcs,
437 + int num, void __iomem *base, spinlock_t *lock,
438 + struct clk_onecell_data *clk_data)
443 + for (i = 0; i < num; i++) {
444 + const struct mtk_composite *mc = &mcs[i];
446 + clk = mtk_clk_register_composite(mc, base, lock);
449 + pr_err("Failed to register clk %s: %ld\n",
450 + mc->name, PTR_ERR(clk));
455 + clk_data->clks[mc->id] = clk;
459 +++ b/drivers/clk/mediatek/clk-mtk.h
462 + * Copyright (c) 2014 MediaTek Inc.
463 + * Author: James Liao <jamesjj.liao@mediatek.com>
465 + * This program is free software; you can redistribute it and/or modify
466 + * it under the terms of the GNU General Public License version 2 as
467 + * published by the Free Software Foundation.
469 + * This program is distributed in the hope that it will be useful,
470 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
471 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
472 + * GNU General Public License for more details.
475 +#ifndef __DRV_CLK_MTK_H
476 +#define __DRV_CLK_MTK_H
478 +#include <linux/regmap.h>
479 +#include <linux/bitops.h>
480 +#include <linux/clk.h>
481 +#include <linux/clk-provider.h>
483 +#define MAX_MUX_GATE_BIT 31
484 +#define INVALID_MUX_GATE_BIT (MAX_MUX_GATE_BIT + 1)
486 +#define MHZ (1000 * 1000)
488 +struct mtk_fixed_factor {
491 + const char *parent_name;
496 +#define FACTOR(_id, _name, _parent, _mult, _div) { \
499 + .parent_name = _parent, \
504 +extern void mtk_clk_register_factors(const struct mtk_fixed_factor *clks,
505 + int num, struct clk_onecell_data *clk_data);
507 +struct mtk_composite {
510 + const char * const * parent_names;
511 + const char *parent;
515 + uint32_t divider_reg;
518 + signed char mux_shift;
519 + signed char mux_width;
520 + signed char gate_shift;
522 + signed char divider_shift;
523 + signed char divider_width;
525 + signed char num_parents;
528 +#define MUX_GATE(_id, _name, _parents, _reg, _shift, _width, _gate) { \
532 + .mux_shift = _shift, \
533 + .mux_width = _width, \
534 + .gate_reg = _reg, \
535 + .gate_shift = _gate, \
536 + .divider_shift = -1, \
537 + .parent_names = _parents, \
538 + .num_parents = ARRAY_SIZE(_parents), \
539 + .flags = CLK_SET_RATE_PARENT, \
542 +#define MUX(_id, _name, _parents, _reg, _shift, _width) { \
546 + .mux_shift = _shift, \
547 + .mux_width = _width, \
548 + .gate_shift = -1, \
549 + .divider_shift = -1, \
550 + .parent_names = _parents, \
551 + .num_parents = ARRAY_SIZE(_parents), \
552 + .flags = CLK_SET_RATE_PARENT, \
555 +#define DIV_GATE(_id, _name, _parent, _gate_reg, _gate_shift, _div_reg, _div_width, _div_shift) { \
557 + .parent = _parent, \
559 + .divider_reg = _div_reg, \
560 + .divider_shift = _div_shift, \
561 + .divider_width = _div_width, \
562 + .gate_reg = _gate_reg, \
563 + .gate_shift = _gate_shift, \
568 +struct clk *mtk_clk_register_composite(const struct mtk_composite *mc,
569 + void __iomem *base, spinlock_t *lock);
571 +void mtk_clk_register_composites(const struct mtk_composite *mcs,
572 + int num, void __iomem *base, spinlock_t *lock,
573 + struct clk_onecell_data *clk_data);
575 +struct mtk_gate_regs {
584 + const char *parent_name;
585 + const struct mtk_gate_regs *regs;
587 + const struct clk_ops *ops;
590 +int mtk_clk_register_gates(struct device_node *node, const struct mtk_gate *clks,
591 + int num, struct clk_onecell_data *clk_data);
593 +struct clk_onecell_data *mtk_alloc_clk_data(unsigned int clk_num);
595 +#define HAVE_RST_BAR BIT(0)
597 +struct mtk_pll_data {
604 + uint32_t tuner_reg;
606 + unsigned int flags;
607 + const struct clk_ops *ops;
609 + unsigned long fmax;
615 +void __init mtk_clk_register_plls(struct device_node *node,
616 + const struct mtk_pll_data *plls, int num_plls,
617 + struct clk_onecell_data *clk_data);
619 +#endif /* __DRV_CLK_MTK_H */
621 +++ b/drivers/clk/mediatek/clk-pll.c
624 + * Copyright (c) 2014 MediaTek Inc.
625 + * Author: James Liao <jamesjj.liao@mediatek.com>
627 + * This program is free software; you can redistribute it and/or modify
628 + * it under the terms of the GNU General Public License version 2 as
629 + * published by the Free Software Foundation.
631 + * This program is distributed in the hope that it will be useful,
632 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
633 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
634 + * GNU General Public License for more details.
637 +#include <linux/of.h>
638 +#include <linux/of_address.h>
639 +#include <linux/io.h>
640 +#include <linux/slab.h>
641 +#include <linux/clkdev.h>
642 +#include <linux/delay.h>
644 +#include "clk-mtk.h"
649 +#define CON0_BASE_EN BIT(0)
650 +#define CON0_PWR_ON BIT(0)
651 +#define CON0_ISO_EN BIT(1)
652 +#define CON0_PCW_CHG BIT(31)
654 +#define AUDPLL_TUNER_EN BIT(31)
656 +#define POSTDIV_MASK 0x7
657 +#define INTEGER_BITS 7
660 + * MediaTek PLLs are configured through their pcw value. The pcw value describes
661 + * a divider in the PLL feedback loop which consists of 7 bits for the integer
662 + * part and the remaining bits (if present) for the fractional part. Also they
663 + * have a 3 bit power-of-two post divider.
666 +struct mtk_clk_pll {
668 + void __iomem *base_addr;
669 + void __iomem *pd_addr;
670 + void __iomem *pwr_addr;
671 + void __iomem *tuner_addr;
672 + void __iomem *pcw_addr;
673 + const struct mtk_pll_data *data;
676 +static inline struct mtk_clk_pll *to_mtk_clk_pll(struct clk_hw *hw)
678 + return container_of(hw, struct mtk_clk_pll, hw);
681 +static int mtk_pll_is_prepared(struct clk_hw *hw)
683 + struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
685 + return (readl(pll->base_addr + REG_CON0) & CON0_BASE_EN) != 0;
688 +static unsigned long __mtk_pll_recalc_rate(struct mtk_clk_pll *pll, u32 fin,
689 + u32 pcw, int postdiv)
691 + int pcwbits = pll->data->pcwbits;
696 + /* The fractional part of the PLL divider. */
697 + pcwfbits = pcwbits > INTEGER_BITS ? pcwbits - INTEGER_BITS : 0;
699 + vco = (u64)fin * pcw;
701 + if (pcwfbits && (vco & GENMASK(pcwfbits - 1, 0)))
709 + return ((unsigned long)vco + postdiv - 1) / postdiv;
712 +static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw,
719 + pd = readl(pll->pd_addr);
720 + pd &= ~(POSTDIV_MASK << pll->data->pd_shift);
721 + pd |= (ffs(postdiv) - 1) << pll->data->pd_shift;
722 + writel(pd, pll->pd_addr);
724 + pll_en = readl(pll->base_addr + REG_CON0) & CON0_BASE_EN;
727 + val = readl(pll->pcw_addr);
729 + val &= ~GENMASK(pll->data->pcw_shift + pll->data->pcwbits - 1,
730 + pll->data->pcw_shift);
731 + val |= pcw << pll->data->pcw_shift;
732 + writel(val, pll->pcw_addr);
734 + con1 = readl(pll->base_addr + REG_CON1);
737 + con1 |= CON0_PCW_CHG;
739 + writel(con1, pll->base_addr + REG_CON1);
740 + if (pll->tuner_addr)
741 + writel(con1 + 1, pll->tuner_addr);
748 + * mtk_pll_calc_values - calculate good values for a given input frequency.
750 + * @pcw: The pcw value (output)
751 + * @postdiv: The post divider (output)
752 + * @freq: The desired target frequency
753 + * @fin: The input frequency
756 +static void mtk_pll_calc_values(struct mtk_clk_pll *pll, u32 *pcw, u32 *postdiv,
759 + unsigned long fmin = 1000 * MHZ;
763 + if (freq > pll->data->fmax)
764 + freq = pll->data->fmax;
766 + for (val = 0; val < 4; val++) {
767 + *postdiv = 1 << val;
768 + if (freq * *postdiv >= fmin)
772 + /* _pcw = freq * postdiv / fin * 2^pcwfbits */
773 + _pcw = ((u64)freq << val) << (pll->data->pcwbits - INTEGER_BITS);
779 +static int mtk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
780 + unsigned long parent_rate)
782 + struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
786 + mtk_pll_calc_values(pll, &pcw, &postdiv, rate, parent_rate);
787 + mtk_pll_set_rate_regs(pll, pcw, postdiv);
792 +static unsigned long mtk_pll_recalc_rate(struct clk_hw *hw,
793 + unsigned long parent_rate)
795 + struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
799 + postdiv = (readl(pll->pd_addr) >> pll->data->pd_shift) & POSTDIV_MASK;
800 + postdiv = 1 << postdiv;
802 + pcw = readl(pll->pcw_addr) >> pll->data->pcw_shift;
803 + pcw &= GENMASK(pll->data->pcwbits - 1, 0);
805 + return __mtk_pll_recalc_rate(pll, parent_rate, pcw, postdiv);
808 +static long mtk_pll_round_rate(struct clk_hw *hw, unsigned long rate,
809 + unsigned long *prate)
811 + struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
815 + mtk_pll_calc_values(pll, &pcw, &postdiv, rate, *prate);
817 + return __mtk_pll_recalc_rate(pll, *prate, pcw, postdiv);
820 +static int mtk_pll_prepare(struct clk_hw *hw)
822 + struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
825 + r = readl(pll->pwr_addr) | CON0_PWR_ON;
826 + writel(r, pll->pwr_addr);
829 + r = readl(pll->pwr_addr) & ~CON0_ISO_EN;
830 + writel(r, pll->pwr_addr);
833 + r = readl(pll->base_addr + REG_CON0);
834 + r |= pll->data->en_mask;
835 + writel(r, pll->base_addr + REG_CON0);
837 + if (pll->tuner_addr) {
838 + r = readl(pll->tuner_addr) | AUDPLL_TUNER_EN;
839 + writel(r, pll->tuner_addr);
844 + if (pll->data->flags & HAVE_RST_BAR) {
845 + r = readl(pll->base_addr + REG_CON0);
846 + r |= pll->data->rst_bar_mask;
847 + writel(r, pll->base_addr + REG_CON0);
853 +static void mtk_pll_unprepare(struct clk_hw *hw)
855 + struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
858 + if (pll->data->flags & HAVE_RST_BAR) {
859 + r = readl(pll->base_addr + REG_CON0);
860 + r &= ~pll->data->rst_bar_mask;
861 + writel(r, pll->base_addr + REG_CON0);
864 + if (pll->tuner_addr) {
865 + r = readl(pll->tuner_addr) & ~AUDPLL_TUNER_EN;
866 + writel(r, pll->tuner_addr);
869 + r = readl(pll->base_addr + REG_CON0);
870 + r &= ~CON0_BASE_EN;
871 + writel(r, pll->base_addr + REG_CON0);
873 + r = readl(pll->pwr_addr) | CON0_ISO_EN;
874 + writel(r, pll->pwr_addr);
876 + r = readl(pll->pwr_addr) & ~CON0_PWR_ON;
877 + writel(r, pll->pwr_addr);
880 +static const struct clk_ops mtk_pll_ops = {
881 + .is_prepared = mtk_pll_is_prepared,
882 + .prepare = mtk_pll_prepare,
883 + .unprepare = mtk_pll_unprepare,
884 + .recalc_rate = mtk_pll_recalc_rate,
885 + .round_rate = mtk_pll_round_rate,
886 + .set_rate = mtk_pll_set_rate,
889 +static struct clk *mtk_clk_register_pll(const struct mtk_pll_data *data,
890 + void __iomem *base)
892 + struct mtk_clk_pll *pll;
893 + struct clk_init_data init;
895 + const char *parent_name = "clk26m";
897 + pll = kzalloc(sizeof(*pll), GFP_KERNEL);
899 + return ERR_PTR(-ENOMEM);
901 + pll->base_addr = base + data->reg;
902 + pll->pwr_addr = base + data->pwr_reg;
903 + pll->pd_addr = base + data->pd_reg;
904 + pll->pcw_addr = base + data->pcw_reg;
905 + if (data->tuner_reg)
906 + pll->tuner_addr = base + data->tuner_reg;
907 + pll->hw.init = &init;
910 + init.name = data->name;
911 + init.ops = &mtk_pll_ops;
912 + init.parent_names = &parent_name;
913 + init.num_parents = 1;
915 + clk = clk_register(NULL, &pll->hw);
923 +void __init mtk_clk_register_plls(struct device_node *node,
924 + const struct mtk_pll_data *plls, int num_plls, struct clk_onecell_data *clk_data)
926 + void __iomem *base;
930 + base = of_iomap(node, 0);
932 + pr_err("%s(): ioremap failed\n", __func__);
936 + for (i = 0; i < num_plls; i++) {
937 + const struct mtk_pll_data *pll = &plls[i];
939 + clk = mtk_clk_register_pll(pll, base);
942 + pr_err("Failed to register clk %s: %ld\n",
943 + pll->name, PTR_ERR(clk));
947 + clk_data->clks[pll->id] = clk;
950 + r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
952 + pr_err("%s(): could not register clock provider: %d\n",