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[openwrt/staging/luka.git] / target / linux / mediatek / patches / 0002-clk-mediatek-Add-initial-common-clock-support-for-Me.patch
1 From f851b4ea6cae9fd5875036b6d3968375882ce56b Mon Sep 17 00:00:00 2001
2 From: James Liao <jamesjj.liao@mediatek.com>
3 Date: Thu, 23 Apr 2015 10:35:39 +0200
4 Subject: [PATCH 02/76] clk: mediatek: Add initial common clock support for
5 Mediatek SoCs.
6
7 This patch adds common clock support for Mediatek SoCs, including plls,
8 muxes and clock gates.
9
10 Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
11 Signed-off-by: Henry Chen <henryc.chen@mediatek.com>
12 Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
13 ---
14 drivers/clk/Makefile | 1 +
15 drivers/clk/mediatek/Makefile | 1 +
16 drivers/clk/mediatek/clk-gate.c | 137 ++++++++++++++++
17 drivers/clk/mediatek/clk-gate.h | 49 ++++++
18 drivers/clk/mediatek/clk-mtk.c | 220 ++++++++++++++++++++++++++
19 drivers/clk/mediatek/clk-mtk.h | 159 +++++++++++++++++++
20 drivers/clk/mediatek/clk-pll.c | 332 +++++++++++++++++++++++++++++++++++++++
21 7 files changed, 899 insertions(+)
22 create mode 100644 drivers/clk/mediatek/Makefile
23 create mode 100644 drivers/clk/mediatek/clk-gate.c
24 create mode 100644 drivers/clk/mediatek/clk-gate.h
25 create mode 100644 drivers/clk/mediatek/clk-mtk.c
26 create mode 100644 drivers/clk/mediatek/clk-mtk.h
27 create mode 100644 drivers/clk/mediatek/clk-pll.c
28
29 diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
30 index 3d00c25..d965b3f 100644
31 --- a/drivers/clk/Makefile
32 +++ b/drivers/clk/Makefile
33 @@ -51,6 +51,7 @@ obj-$(CONFIG_ARCH_HI3xxx) += hisilicon/
34 obj-$(CONFIG_ARCH_HIP04) += hisilicon/
35 obj-$(CONFIG_ARCH_HIX5HD2) += hisilicon/
36 obj-$(CONFIG_COMMON_CLK_KEYSTONE) += keystone/
37 +obj-$(CONFIG_ARCH_MEDIATEK) += mediatek/
38 ifeq ($(CONFIG_COMMON_CLK), y)
39 obj-$(CONFIG_ARCH_MMP) += mmp/
40 endif
41 diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
42 new file mode 100644
43 index 0000000..c384e97
44 --- /dev/null
45 +++ b/drivers/clk/mediatek/Makefile
46 @@ -0,0 +1 @@
47 +obj-y += clk-mtk.o clk-pll.o clk-gate.o
48 diff --git a/drivers/clk/mediatek/clk-gate.c b/drivers/clk/mediatek/clk-gate.c
49 new file mode 100644
50 index 0000000..9d77ee3
51 --- /dev/null
52 +++ b/drivers/clk/mediatek/clk-gate.c
53 @@ -0,0 +1,137 @@
54 +/*
55 + * Copyright (c) 2014 MediaTek Inc.
56 + * Author: James Liao <jamesjj.liao@mediatek.com>
57 + *
58 + * This program is free software; you can redistribute it and/or modify
59 + * it under the terms of the GNU General Public License version 2 as
60 + * published by the Free Software Foundation.
61 + *
62 + * This program is distributed in the hope that it will be useful,
63 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
64 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
65 + * GNU General Public License for more details.
66 + */
67 +
68 +#include <linux/of.h>
69 +#include <linux/of_address.h>
70 +
71 +#include <linux/io.h>
72 +#include <linux/slab.h>
73 +#include <linux/delay.h>
74 +#include <linux/clkdev.h>
75 +
76 +#include "clk-mtk.h"
77 +#include "clk-gate.h"
78 +
79 +static int mtk_cg_bit_is_cleared(struct clk_hw *hw)
80 +{
81 + struct mtk_clk_gate *cg = to_clk_gate(hw);
82 + u32 val;
83 +
84 + regmap_read(cg->regmap, cg->sta_ofs, &val);
85 +
86 + val &= BIT(cg->bit);
87 +
88 + return val == 0;
89 +}
90 +
91 +static int mtk_cg_bit_is_set(struct clk_hw *hw)
92 +{
93 + struct mtk_clk_gate *cg = to_clk_gate(hw);
94 + u32 val;
95 +
96 + regmap_read(cg->regmap, cg->sta_ofs, &val);
97 +
98 + val &= BIT(cg->bit);
99 +
100 + return val != 0;
101 +}
102 +
103 +static void mtk_cg_set_bit(struct clk_hw *hw)
104 +{
105 + struct mtk_clk_gate *cg = to_clk_gate(hw);
106 +
107 + regmap_write(cg->regmap, cg->set_ofs, BIT(cg->bit));
108 +}
109 +
110 +static void mtk_cg_clr_bit(struct clk_hw *hw)
111 +{
112 + struct mtk_clk_gate *cg = to_clk_gate(hw);
113 +
114 + regmap_write(cg->regmap, cg->clr_ofs, BIT(cg->bit));
115 +}
116 +
117 +static int mtk_cg_enable(struct clk_hw *hw)
118 +{
119 + mtk_cg_clr_bit(hw);
120 +
121 + return 0;
122 +}
123 +
124 +static void mtk_cg_disable(struct clk_hw *hw)
125 +{
126 + mtk_cg_set_bit(hw);
127 +}
128 +
129 +static int mtk_cg_enable_inv(struct clk_hw *hw)
130 +{
131 + mtk_cg_set_bit(hw);
132 +
133 + return 0;
134 +}
135 +
136 +static void mtk_cg_disable_inv(struct clk_hw *hw)
137 +{
138 + mtk_cg_clr_bit(hw);
139 +}
140 +
141 +const struct clk_ops mtk_clk_gate_ops_setclr = {
142 + .is_enabled = mtk_cg_bit_is_cleared,
143 + .enable = mtk_cg_enable,
144 + .disable = mtk_cg_disable,
145 +};
146 +
147 +const struct clk_ops mtk_clk_gate_ops_setclr_inv = {
148 + .is_enabled = mtk_cg_bit_is_set,
149 + .enable = mtk_cg_enable_inv,
150 + .disable = mtk_cg_disable_inv,
151 +};
152 +
153 +struct clk *mtk_clk_register_gate(
154 + const char *name,
155 + const char *parent_name,
156 + struct regmap *regmap,
157 + int set_ofs,
158 + int clr_ofs,
159 + int sta_ofs,
160 + u8 bit,
161 + const struct clk_ops *ops)
162 +{
163 + struct mtk_clk_gate *cg;
164 + struct clk *clk;
165 + struct clk_init_data init;
166 +
167 + cg = kzalloc(sizeof(*cg), GFP_KERNEL);
168 + if (!cg)
169 + return ERR_PTR(-ENOMEM);
170 +
171 + init.name = name;
172 + init.flags = CLK_SET_RATE_PARENT;
173 + init.parent_names = parent_name ? &parent_name : NULL;
174 + init.num_parents = parent_name ? 1 : 0;
175 + init.ops = ops;
176 +
177 + cg->regmap = regmap;
178 + cg->set_ofs = set_ofs;
179 + cg->clr_ofs = clr_ofs;
180 + cg->sta_ofs = sta_ofs;
181 + cg->bit = bit;
182 +
183 + cg->hw.init = &init;
184 +
185 + clk = clk_register(NULL, &cg->hw);
186 + if (IS_ERR(clk))
187 + kfree(cg);
188 +
189 + return clk;
190 +}
191 diff --git a/drivers/clk/mediatek/clk-gate.h b/drivers/clk/mediatek/clk-gate.h
192 new file mode 100644
193 index 0000000..6b6780b
194 --- /dev/null
195 +++ b/drivers/clk/mediatek/clk-gate.h
196 @@ -0,0 +1,49 @@
197 +/*
198 + * Copyright (c) 2014 MediaTek Inc.
199 + * Author: James Liao <jamesjj.liao@mediatek.com>
200 + *
201 + * This program is free software; you can redistribute it and/or modify
202 + * it under the terms of the GNU General Public License version 2 as
203 + * published by the Free Software Foundation.
204 + *
205 + * This program is distributed in the hope that it will be useful,
206 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
207 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
208 + * GNU General Public License for more details.
209 + */
210 +
211 +#ifndef __DRV_CLK_GATE_H
212 +#define __DRV_CLK_GATE_H
213 +
214 +#include <linux/regmap.h>
215 +#include <linux/clk.h>
216 +#include <linux/clk-provider.h>
217 +
218 +struct mtk_clk_gate {
219 + struct clk_hw hw;
220 + struct regmap *regmap;
221 + int set_ofs;
222 + int clr_ofs;
223 + int sta_ofs;
224 + u8 bit;
225 +};
226 +
227 +static inline struct mtk_clk_gate *to_clk_gate(struct clk_hw *hw)
228 +{
229 + return container_of(hw, struct mtk_clk_gate, hw);
230 +}
231 +
232 +extern const struct clk_ops mtk_clk_gate_ops_setclr;
233 +extern const struct clk_ops mtk_clk_gate_ops_setclr_inv;
234 +
235 +struct clk *mtk_clk_register_gate(
236 + const char *name,
237 + const char *parent_name,
238 + struct regmap *regmap,
239 + int set_ofs,
240 + int clr_ofs,
241 + int sta_ofs,
242 + u8 bit,
243 + const struct clk_ops *ops);
244 +
245 +#endif /* __DRV_CLK_GATE_H */
246 diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c
247 new file mode 100644
248 index 0000000..18444ae
249 --- /dev/null
250 +++ b/drivers/clk/mediatek/clk-mtk.c
251 @@ -0,0 +1,220 @@
252 +/*
253 + * Copyright (c) 2014 MediaTek Inc.
254 + * Author: James Liao <jamesjj.liao@mediatek.com>
255 + *
256 + * This program is free software; you can redistribute it and/or modify
257 + * it under the terms of the GNU General Public License version 2 as
258 + * published by the Free Software Foundation.
259 + *
260 + * This program is distributed in the hope that it will be useful,
261 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
262 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
263 + * GNU General Public License for more details.
264 + */
265 +
266 +#include <linux/of.h>
267 +#include <linux/of_address.h>
268 +#include <linux/err.h>
269 +#include <linux/io.h>
270 +#include <linux/slab.h>
271 +#include <linux/delay.h>
272 +#include <linux/clkdev.h>
273 +#include <linux/mfd/syscon.h>
274 +
275 +#include "clk-mtk.h"
276 +#include "clk-gate.h"
277 +
278 +struct clk_onecell_data *mtk_alloc_clk_data(unsigned int clk_num)
279 +{
280 + int i;
281 + struct clk_onecell_data *clk_data;
282 +
283 + clk_data = kzalloc(sizeof(*clk_data), GFP_KERNEL);
284 + if (!clk_data)
285 + return NULL;
286 +
287 + clk_data->clks = kcalloc(clk_num, sizeof(*clk_data->clks), GFP_KERNEL);
288 + if (!clk_data->clks)
289 + goto err_out;
290 +
291 + clk_data->clk_num = clk_num;
292 +
293 + for (i = 0; i < clk_num; i++)
294 + clk_data->clks[i] = ERR_PTR(-ENOENT);
295 +
296 + return clk_data;
297 +err_out:
298 + kfree(clk_data);
299 +
300 + return NULL;
301 +}
302 +
303 +void mtk_clk_register_factors(const struct mtk_fixed_factor *clks, int num,
304 + struct clk_onecell_data *clk_data)
305 +{
306 + int i;
307 + struct clk *clk;
308 +
309 + for (i = 0; i < num; i++) {
310 + const struct mtk_fixed_factor *ff = &clks[i];
311 +
312 + clk = clk_register_fixed_factor(NULL, ff->name, ff->parent_name,
313 + CLK_SET_RATE_PARENT, ff->mult, ff->div);
314 +
315 + if (IS_ERR(clk)) {
316 + pr_err("Failed to register clk %s: %ld\n",
317 + ff->name, PTR_ERR(clk));
318 + continue;
319 + }
320 +
321 + if (clk_data)
322 + clk_data->clks[ff->id] = clk;
323 + }
324 +}
325 +
326 +int mtk_clk_register_gates(struct device_node *node, const struct mtk_gate *clks,
327 + int num, struct clk_onecell_data *clk_data)
328 +{
329 + int i;
330 + struct clk *clk;
331 + struct regmap *regmap;
332 +
333 + if (!clk_data)
334 + return -ENOMEM;
335 +
336 + regmap = syscon_node_to_regmap(node);
337 + if (IS_ERR(regmap)) {
338 + pr_err("Cannot find regmap for %s: %ld\n", node->full_name,
339 + PTR_ERR(regmap));
340 + return PTR_ERR(regmap);
341 + }
342 +
343 + for (i = 0; i < num; i++) {
344 + const struct mtk_gate *gate = &clks[i];
345 +
346 + clk = mtk_clk_register_gate(gate->name, gate->parent_name,
347 + regmap,
348 + gate->regs->set_ofs,
349 + gate->regs->clr_ofs,
350 + gate->regs->sta_ofs,
351 + gate->shift, gate->ops);
352 +
353 + if (IS_ERR(clk)) {
354 + pr_err("Failed to register clk %s: %ld\n",
355 + gate->name, PTR_ERR(clk));
356 + continue;
357 + }
358 +
359 + clk_data->clks[gate->id] = clk;
360 + }
361 +
362 + return 0;
363 +}
364 +
365 +struct clk *mtk_clk_register_composite(const struct mtk_composite *mc,
366 + void __iomem *base, spinlock_t *lock)
367 +{
368 + struct clk *clk;
369 + struct clk_mux *mux = NULL;
370 + struct clk_gate *gate = NULL;
371 + struct clk_divider *div = NULL;
372 + struct clk_hw *mux_hw = NULL, *gate_hw = NULL, *div_hw = NULL;
373 + const struct clk_ops *mux_ops = NULL, *gate_ops = NULL, *div_ops = NULL;
374 + const char * const *parent_names;
375 + const char *parent;
376 + int num_parents;
377 + int ret;
378 +
379 + if (mc->mux_shift >= 0) {
380 + mux = kzalloc(sizeof(*mux), GFP_KERNEL);
381 + if (!mux)
382 + return ERR_PTR(-ENOMEM);
383 +
384 + mux->reg = base + mc->mux_reg;
385 + mux->mask = BIT(mc->mux_width) - 1;
386 + mux->shift = mc->mux_shift;
387 + mux->lock = lock;
388 +
389 + mux_hw = &mux->hw;
390 + mux_ops = &clk_mux_ops;
391 +
392 + parent_names = mc->parent_names;
393 + num_parents = mc->num_parents;
394 + } else {
395 + parent = mc->parent;
396 + parent_names = &parent;
397 + num_parents = 1;
398 + }
399 +
400 + if (mc->gate_shift >= 0) {
401 + gate = kzalloc(sizeof(*gate), GFP_KERNEL);
402 + if (!gate) {
403 + ret = -ENOMEM;
404 + goto err_out;
405 + }
406 +
407 + gate->reg = base + mc->gate_reg;
408 + gate->bit_idx = mc->gate_shift;
409 + gate->flags = CLK_GATE_SET_TO_DISABLE;
410 + gate->lock = lock;
411 +
412 + gate_hw = &gate->hw;
413 + gate_ops = &clk_gate_ops;
414 + }
415 +
416 + if (mc->divider_shift >= 0) {
417 + div = kzalloc(sizeof(*div), GFP_KERNEL);
418 + if (!div) {
419 + ret = -ENOMEM;
420 + goto err_out;
421 + }
422 +
423 + div->reg = base + mc->divider_reg;
424 + div->shift = mc->divider_shift;
425 + div->width = mc->divider_width;
426 + div->lock = lock;
427 +
428 + div_hw = &div->hw;
429 + div_ops = &clk_divider_ops;
430 + }
431 +
432 + clk = clk_register_composite(NULL, mc->name, parent_names, num_parents,
433 + mux_hw, mux_ops,
434 + div_hw, div_ops,
435 + gate_hw, gate_ops,
436 + mc->flags);
437 +
438 + if (IS_ERR(clk)) {
439 + kfree(gate);
440 + kfree(mux);
441 + }
442 +
443 + return clk;
444 +err_out:
445 + kfree(mux);
446 +
447 + return ERR_PTR(ret);
448 +}
449 +
450 +void mtk_clk_register_composites(const struct mtk_composite *mcs,
451 + int num, void __iomem *base, spinlock_t *lock,
452 + struct clk_onecell_data *clk_data)
453 +{
454 + struct clk *clk;
455 + int i;
456 +
457 + for (i = 0; i < num; i++) {
458 + const struct mtk_composite *mc = &mcs[i];
459 +
460 + clk = mtk_clk_register_composite(mc, base, lock);
461 +
462 + if (IS_ERR(clk)) {
463 + pr_err("Failed to register clk %s: %ld\n",
464 + mc->name, PTR_ERR(clk));
465 + continue;
466 + }
467 +
468 + if (clk_data)
469 + clk_data->clks[mc->id] = clk;
470 + }
471 +}
472 diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h
473 new file mode 100644
474 index 0000000..694fc39
475 --- /dev/null
476 +++ b/drivers/clk/mediatek/clk-mtk.h
477 @@ -0,0 +1,159 @@
478 +/*
479 + * Copyright (c) 2014 MediaTek Inc.
480 + * Author: James Liao <jamesjj.liao@mediatek.com>
481 + *
482 + * This program is free software; you can redistribute it and/or modify
483 + * it under the terms of the GNU General Public License version 2 as
484 + * published by the Free Software Foundation.
485 + *
486 + * This program is distributed in the hope that it will be useful,
487 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
488 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
489 + * GNU General Public License for more details.
490 + */
491 +
492 +#ifndef __DRV_CLK_MTK_H
493 +#define __DRV_CLK_MTK_H
494 +
495 +#include <linux/regmap.h>
496 +#include <linux/bitops.h>
497 +#include <linux/clk.h>
498 +#include <linux/clk-provider.h>
499 +
500 +#define MAX_MUX_GATE_BIT 31
501 +#define INVALID_MUX_GATE_BIT (MAX_MUX_GATE_BIT + 1)
502 +
503 +#define MHZ (1000 * 1000)
504 +
505 +struct mtk_fixed_factor {
506 + int id;
507 + const char *name;
508 + const char *parent_name;
509 + int mult;
510 + int div;
511 +};
512 +
513 +#define FACTOR(_id, _name, _parent, _mult, _div) { \
514 + .id = _id, \
515 + .name = _name, \
516 + .parent_name = _parent, \
517 + .mult = _mult, \
518 + .div = _div, \
519 + }
520 +
521 +extern void mtk_clk_register_factors(const struct mtk_fixed_factor *clks,
522 + int num, struct clk_onecell_data *clk_data);
523 +
524 +struct mtk_composite {
525 + int id;
526 + const char *name;
527 + const char * const * parent_names;
528 + const char *parent;
529 + unsigned flags;
530 +
531 + uint32_t mux_reg;
532 + uint32_t divider_reg;
533 + uint32_t gate_reg;
534 +
535 + signed char mux_shift;
536 + signed char mux_width;
537 + signed char gate_shift;
538 +
539 + signed char divider_shift;
540 + signed char divider_width;
541 +
542 + signed char num_parents;
543 +};
544 +
545 +#define MUX_GATE(_id, _name, _parents, _reg, _shift, _width, _gate) { \
546 + .id = _id, \
547 + .name = _name, \
548 + .mux_reg = _reg, \
549 + .mux_shift = _shift, \
550 + .mux_width = _width, \
551 + .gate_reg = _reg, \
552 + .gate_shift = _gate, \
553 + .divider_shift = -1, \
554 + .parent_names = _parents, \
555 + .num_parents = ARRAY_SIZE(_parents), \
556 + .flags = CLK_SET_RATE_PARENT, \
557 + }
558 +
559 +#define MUX(_id, _name, _parents, _reg, _shift, _width) { \
560 + .id = _id, \
561 + .name = _name, \
562 + .mux_reg = _reg, \
563 + .mux_shift = _shift, \
564 + .mux_width = _width, \
565 + .gate_shift = -1, \
566 + .divider_shift = -1, \
567 + .parent_names = _parents, \
568 + .num_parents = ARRAY_SIZE(_parents), \
569 + .flags = CLK_SET_RATE_PARENT, \
570 + }
571 +
572 +#define DIV_GATE(_id, _name, _parent, _gate_reg, _gate_shift, _div_reg, _div_width, _div_shift) { \
573 + .id = _id, \
574 + .parent = _parent, \
575 + .name = _name, \
576 + .divider_reg = _div_reg, \
577 + .divider_shift = _div_shift, \
578 + .divider_width = _div_width, \
579 + .gate_reg = _gate_reg, \
580 + .gate_shift = _gate_shift, \
581 + .mux_shift = -1, \
582 + .flags = 0, \
583 + }
584 +
585 +struct clk *mtk_clk_register_composite(const struct mtk_composite *mc,
586 + void __iomem *base, spinlock_t *lock);
587 +
588 +void mtk_clk_register_composites(const struct mtk_composite *mcs,
589 + int num, void __iomem *base, spinlock_t *lock,
590 + struct clk_onecell_data *clk_data);
591 +
592 +struct mtk_gate_regs {
593 + u32 sta_ofs;
594 + u32 clr_ofs;
595 + u32 set_ofs;
596 +};
597 +
598 +struct mtk_gate {
599 + int id;
600 + const char *name;
601 + const char *parent_name;
602 + const struct mtk_gate_regs *regs;
603 + int shift;
604 + const struct clk_ops *ops;
605 +};
606 +
607 +int mtk_clk_register_gates(struct device_node *node, const struct mtk_gate *clks,
608 + int num, struct clk_onecell_data *clk_data);
609 +
610 +struct clk_onecell_data *mtk_alloc_clk_data(unsigned int clk_num);
611 +
612 +#define HAVE_RST_BAR BIT(0)
613 +
614 +struct mtk_pll_data {
615 + int id;
616 + const char *name;
617 + uint32_t reg;
618 + uint32_t pwr_reg;
619 + uint32_t en_mask;
620 + uint32_t pd_reg;
621 + uint32_t tuner_reg;
622 + int pd_shift;
623 + unsigned int flags;
624 + const struct clk_ops *ops;
625 + u32 rst_bar_mask;
626 + unsigned long fmax;
627 + int pcwbits;
628 + uint32_t pcw_reg;
629 + int pcw_shift;
630 +};
631 +
632 +void __init mtk_clk_register_plls(struct device_node *node,
633 + const struct mtk_pll_data *plls, int num_plls,
634 + struct clk_onecell_data *clk_data);
635 +
636 +#endif /* __DRV_CLK_MTK_H */
637 diff --git a/drivers/clk/mediatek/clk-pll.c b/drivers/clk/mediatek/clk-pll.c
638 new file mode 100644
639 index 0000000..66154ca
640 --- /dev/null
641 +++ b/drivers/clk/mediatek/clk-pll.c
642 @@ -0,0 +1,332 @@
643 +/*
644 + * Copyright (c) 2014 MediaTek Inc.
645 + * Author: James Liao <jamesjj.liao@mediatek.com>
646 + *
647 + * This program is free software; you can redistribute it and/or modify
648 + * it under the terms of the GNU General Public License version 2 as
649 + * published by the Free Software Foundation.
650 + *
651 + * This program is distributed in the hope that it will be useful,
652 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
653 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
654 + * GNU General Public License for more details.
655 + */
656 +
657 +#include <linux/of.h>
658 +#include <linux/of_address.h>
659 +#include <linux/io.h>
660 +#include <linux/slab.h>
661 +#include <linux/clkdev.h>
662 +#include <linux/delay.h>
663 +
664 +#include "clk-mtk.h"
665 +
666 +#define REG_CON0 0
667 +#define REG_CON1 4
668 +
669 +#define CON0_BASE_EN BIT(0)
670 +#define CON0_PWR_ON BIT(0)
671 +#define CON0_ISO_EN BIT(1)
672 +#define CON0_PCW_CHG BIT(31)
673 +
674 +#define AUDPLL_TUNER_EN BIT(31)
675 +
676 +#define POSTDIV_MASK 0x7
677 +#define INTEGER_BITS 7
678 +
679 +/*
680 + * MediaTek PLLs are configured through their pcw value. The pcw value describes
681 + * a divider in the PLL feedback loop which consists of 7 bits for the integer
682 + * part and the remaining bits (if present) for the fractional part. Also they
683 + * have a 3 bit power-of-two post divider.
684 + */
685 +
686 +struct mtk_clk_pll {
687 + struct clk_hw hw;
688 + void __iomem *base_addr;
689 + void __iomem *pd_addr;
690 + void __iomem *pwr_addr;
691 + void __iomem *tuner_addr;
692 + void __iomem *pcw_addr;
693 + const struct mtk_pll_data *data;
694 +};
695 +
696 +static inline struct mtk_clk_pll *to_mtk_clk_pll(struct clk_hw *hw)
697 +{
698 + return container_of(hw, struct mtk_clk_pll, hw);
699 +}
700 +
701 +static int mtk_pll_is_prepared(struct clk_hw *hw)
702 +{
703 + struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
704 +
705 + return (readl(pll->base_addr + REG_CON0) & CON0_BASE_EN) != 0;
706 +}
707 +
708 +static unsigned long __mtk_pll_recalc_rate(struct mtk_clk_pll *pll, u32 fin,
709 + u32 pcw, int postdiv)
710 +{
711 + int pcwbits = pll->data->pcwbits;
712 + int pcwfbits;
713 + u64 vco;
714 + u8 c = 0;
715 +
716 + /* The fractional part of the PLL divider. */
717 + pcwfbits = pcwbits > INTEGER_BITS ? pcwbits - INTEGER_BITS : 0;
718 +
719 + vco = (u64)fin * pcw;
720 +
721 + if (pcwfbits && (vco & GENMASK(pcwfbits - 1, 0)))
722 + c = 1;
723 +
724 + vco >>= pcwfbits;
725 +
726 + if (c)
727 + vco++;
728 +
729 + return ((unsigned long)vco + postdiv - 1) / postdiv;
730 +}
731 +
732 +static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw,
733 + int postdiv)
734 +{
735 + u32 con1, pd, val;
736 + int pll_en;
737 +
738 + /* set postdiv */
739 + pd = readl(pll->pd_addr);
740 + pd &= ~(POSTDIV_MASK << pll->data->pd_shift);
741 + pd |= (ffs(postdiv) - 1) << pll->data->pd_shift;
742 + writel(pd, pll->pd_addr);
743 +
744 + pll_en = readl(pll->base_addr + REG_CON0) & CON0_BASE_EN;
745 +
746 + /* set pcw */
747 + val = readl(pll->pcw_addr);
748 +
749 + val &= ~GENMASK(pll->data->pcw_shift + pll->data->pcwbits - 1,
750 + pll->data->pcw_shift);
751 + val |= pcw << pll->data->pcw_shift;
752 + writel(val, pll->pcw_addr);
753 +
754 + con1 = readl(pll->base_addr + REG_CON1);
755 +
756 + if (pll_en)
757 + con1 |= CON0_PCW_CHG;
758 +
759 + writel(con1, pll->base_addr + REG_CON1);
760 + if (pll->tuner_addr)
761 + writel(con1 + 1, pll->tuner_addr);
762 +
763 + if (pll_en)
764 + udelay(20);
765 +}
766 +
767 +/*
768 + * mtk_pll_calc_values - calculate good values for a given input frequency.
769 + * @pll: The pll
770 + * @pcw: The pcw value (output)
771 + * @postdiv: The post divider (output)
772 + * @freq: The desired target frequency
773 + * @fin: The input frequency
774 + *
775 + */
776 +static void mtk_pll_calc_values(struct mtk_clk_pll *pll, u32 *pcw, u32 *postdiv,
777 + u32 freq, u32 fin)
778 +{
779 + unsigned long fmin = 1000 * MHZ;
780 + u64 _pcw;
781 + u32 val;
782 +
783 + if (freq > pll->data->fmax)
784 + freq = pll->data->fmax;
785 +
786 + for (val = 0; val < 4; val++) {
787 + *postdiv = 1 << val;
788 + if (freq * *postdiv >= fmin)
789 + break;
790 + }
791 +
792 + /* _pcw = freq * postdiv / fin * 2^pcwfbits */
793 + _pcw = ((u64)freq << val) << (pll->data->pcwbits - INTEGER_BITS);
794 + do_div(_pcw, fin);
795 +
796 + *pcw = (u32)_pcw;
797 +}
798 +
799 +static int mtk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
800 + unsigned long parent_rate)
801 +{
802 + struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
803 + u32 pcw = 0;
804 + u32 postdiv;
805 +
806 + mtk_pll_calc_values(pll, &pcw, &postdiv, rate, parent_rate);
807 + mtk_pll_set_rate_regs(pll, pcw, postdiv);
808 +
809 + return 0;
810 +}
811 +
812 +static unsigned long mtk_pll_recalc_rate(struct clk_hw *hw,
813 + unsigned long parent_rate)
814 +{
815 + struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
816 + u32 postdiv;
817 + u32 pcw;
818 +
819 + postdiv = (readl(pll->pd_addr) >> pll->data->pd_shift) & POSTDIV_MASK;
820 + postdiv = 1 << postdiv;
821 +
822 + pcw = readl(pll->pcw_addr) >> pll->data->pcw_shift;
823 + pcw &= GENMASK(pll->data->pcwbits - 1, 0);
824 +
825 + return __mtk_pll_recalc_rate(pll, parent_rate, pcw, postdiv);
826 +}
827 +
828 +static long mtk_pll_round_rate(struct clk_hw *hw, unsigned long rate,
829 + unsigned long *prate)
830 +{
831 + struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
832 + u32 pcw = 0;
833 + int postdiv;
834 +
835 + mtk_pll_calc_values(pll, &pcw, &postdiv, rate, *prate);
836 +
837 + return __mtk_pll_recalc_rate(pll, *prate, pcw, postdiv);
838 +}
839 +
840 +static int mtk_pll_prepare(struct clk_hw *hw)
841 +{
842 + struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
843 + u32 r;
844 +
845 + r = readl(pll->pwr_addr) | CON0_PWR_ON;
846 + writel(r, pll->pwr_addr);
847 + udelay(1);
848 +
849 + r = readl(pll->pwr_addr) & ~CON0_ISO_EN;
850 + writel(r, pll->pwr_addr);
851 + udelay(1);
852 +
853 + r = readl(pll->base_addr + REG_CON0);
854 + r |= pll->data->en_mask;
855 + writel(r, pll->base_addr + REG_CON0);
856 +
857 + if (pll->tuner_addr) {
858 + r = readl(pll->tuner_addr) | AUDPLL_TUNER_EN;
859 + writel(r, pll->tuner_addr);
860 + }
861 +
862 + udelay(20);
863 +
864 + if (pll->data->flags & HAVE_RST_BAR) {
865 + r = readl(pll->base_addr + REG_CON0);
866 + r |= pll->data->rst_bar_mask;
867 + writel(r, pll->base_addr + REG_CON0);
868 + }
869 +
870 + return 0;
871 +}
872 +
873 +static void mtk_pll_unprepare(struct clk_hw *hw)
874 +{
875 + struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
876 + u32 r;
877 +
878 + if (pll->data->flags & HAVE_RST_BAR) {
879 + r = readl(pll->base_addr + REG_CON0);
880 + r &= ~pll->data->rst_bar_mask;
881 + writel(r, pll->base_addr + REG_CON0);
882 + }
883 +
884 + if (pll->tuner_addr) {
885 + r = readl(pll->tuner_addr) & ~AUDPLL_TUNER_EN;
886 + writel(r, pll->tuner_addr);
887 + }
888 +
889 + r = readl(pll->base_addr + REG_CON0);
890 + r &= ~CON0_BASE_EN;
891 + writel(r, pll->base_addr + REG_CON0);
892 +
893 + r = readl(pll->pwr_addr) | CON0_ISO_EN;
894 + writel(r, pll->pwr_addr);
895 +
896 + r = readl(pll->pwr_addr) & ~CON0_PWR_ON;
897 + writel(r, pll->pwr_addr);
898 +}
899 +
900 +static const struct clk_ops mtk_pll_ops = {
901 + .is_prepared = mtk_pll_is_prepared,
902 + .prepare = mtk_pll_prepare,
903 + .unprepare = mtk_pll_unprepare,
904 + .recalc_rate = mtk_pll_recalc_rate,
905 + .round_rate = mtk_pll_round_rate,
906 + .set_rate = mtk_pll_set_rate,
907 +};
908 +
909 +static struct clk *mtk_clk_register_pll(const struct mtk_pll_data *data,
910 + void __iomem *base)
911 +{
912 + struct mtk_clk_pll *pll;
913 + struct clk_init_data init;
914 + struct clk *clk;
915 + const char *parent_name = "clk26m";
916 +
917 + pll = kzalloc(sizeof(*pll), GFP_KERNEL);
918 + if (!pll)
919 + return ERR_PTR(-ENOMEM);
920 +
921 + pll->base_addr = base + data->reg;
922 + pll->pwr_addr = base + data->pwr_reg;
923 + pll->pd_addr = base + data->pd_reg;
924 + pll->pcw_addr = base + data->pcw_reg;
925 + if (data->tuner_reg)
926 + pll->tuner_addr = base + data->tuner_reg;
927 + pll->hw.init = &init;
928 + pll->data = data;
929 +
930 + init.name = data->name;
931 + init.ops = &mtk_pll_ops;
932 + init.parent_names = &parent_name;
933 + init.num_parents = 1;
934 +
935 + clk = clk_register(NULL, &pll->hw);
936 +
937 + if (IS_ERR(clk))
938 + kfree(pll);
939 +
940 + return clk;
941 +}
942 +
943 +void __init mtk_clk_register_plls(struct device_node *node,
944 + const struct mtk_pll_data *plls, int num_plls, struct clk_onecell_data *clk_data)
945 +{
946 + void __iomem *base;
947 + int r, i;
948 + struct clk *clk;
949 +
950 + base = of_iomap(node, 0);
951 + if (!base) {
952 + pr_err("%s(): ioremap failed\n", __func__);
953 + return;
954 + }
955 +
956 + for (i = 0; i < num_plls; i++) {
957 + const struct mtk_pll_data *pll = &plls[i];
958 +
959 + clk = mtk_clk_register_pll(pll, base);
960 +
961 + if (IS_ERR(clk)) {
962 + pr_err("Failed to register clk %s: %ld\n",
963 + pll->name, PTR_ERR(clk));
964 + continue;
965 + }
966 +
967 + clk_data->clks[pll->id] = clk;
968 + }
969 +
970 + r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
971 + if (r)
972 + pr_err("%s(): could not register clock provider: %d\n",
973 + __func__, r);
974 +}
975 --
976 1.7.10.4
977
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