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[openwrt/staging/yousong.git] / target / linux / mediatek / patches / 0004-clk-mediatek-Add-basic-clocks-for-Mediatek-MT8135.patch
1 From 242572135fdb513cba0506415c7e26a0909eb4b5 Mon Sep 17 00:00:00 2001
2 From: James Liao <jamesjj.liao@mediatek.com>
3 Date: Thu, 23 Apr 2015 10:35:41 +0200
4 Subject: [PATCH 04/76] clk: mediatek: Add basic clocks for Mediatek MT8135.
5
6 This patch adds basic clocks for MT8135, including TOPCKGEN, PLLs,
7 INFRA and PERI clocks.
8
9 Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
10 Signed-off-by: Henry Chen <henryc.chen@mediatek.com>
11 Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
12 ---
13 drivers/clk/mediatek/Makefile | 1 +
14 drivers/clk/mediatek/clk-mt8135.c | 644 ++++++++++++++++++++
15 include/dt-bindings/clock/mt8135-clk.h | 194 ++++++
16 .../dt-bindings/reset-controller/mt8135-resets.h | 64 ++
17 4 files changed, 903 insertions(+)
18 create mode 100644 drivers/clk/mediatek/clk-mt8135.c
19 create mode 100644 include/dt-bindings/clock/mt8135-clk.h
20 create mode 100644 include/dt-bindings/reset-controller/mt8135-resets.h
21
22 diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
23 index 0b6f1c3..12ce576 100644
24 --- a/drivers/clk/mediatek/Makefile
25 +++ b/drivers/clk/mediatek/Makefile
26 @@ -1,2 +1,3 @@
27 obj-y += clk-mtk.o clk-pll.o clk-gate.o
28 obj-$(CONFIG_RESET_CONTROLLER) += reset.o
29 +obj-y += clk-mt8135.o
30 diff --git a/drivers/clk/mediatek/clk-mt8135.c b/drivers/clk/mediatek/clk-mt8135.c
31 new file mode 100644
32 index 0000000..a63435b
33 --- /dev/null
34 +++ b/drivers/clk/mediatek/clk-mt8135.c
35 @@ -0,0 +1,644 @@
36 +/*
37 + * Copyright (c) 2014 MediaTek Inc.
38 + * Author: James Liao <jamesjj.liao@mediatek.com>
39 + *
40 + * This program is free software; you can redistribute it and/or modify
41 + * it under the terms of the GNU General Public License version 2 as
42 + * published by the Free Software Foundation.
43 + *
44 + * This program is distributed in the hope that it will be useful,
45 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
46 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
47 + * GNU General Public License for more details.
48 + */
49 +
50 +#include <linux/of.h>
51 +#include <linux/of_address.h>
52 +#include <linux/slab.h>
53 +#include <linux/mfd/syscon.h>
54 +#include <dt-bindings/clock/mt8135-clk.h>
55 +
56 +#include "clk-mtk.h"
57 +#include "clk-gate.h"
58 +
59 +static DEFINE_SPINLOCK(mt8135_clk_lock);
60 +
61 +static const struct mtk_fixed_factor root_clk_alias[] __initconst = {
62 + FACTOR(CLK_TOP_DSI0_LNTC_DSICLK, "dsi0_lntc_dsiclk", "clk_null", 1, 1),
63 + FACTOR(CLK_TOP_HDMITX_CLKDIG_CTS, "hdmitx_clkdig_cts", "clk_null", 1, 1),
64 + FACTOR(CLK_TOP_CLKPH_MCK, "clkph_mck", "clk_null", 1, 1),
65 + FACTOR(CLK_TOP_CPUM_TCK_IN, "cpum_tck_in", "clk_null", 1, 1),
66 +};
67 +
68 +static const struct mtk_fixed_factor top_divs[] __initconst = {
69 + FACTOR(CLK_TOP_MAINPLL_806M, "mainpll_806m", "mainpll", 1, 2),
70 + FACTOR(CLK_TOP_MAINPLL_537P3M, "mainpll_537p3m", "mainpll", 1, 3),
71 + FACTOR(CLK_TOP_MAINPLL_322P4M, "mainpll_322p4m", "mainpll", 1, 5),
72 + FACTOR(CLK_TOP_MAINPLL_230P3M, "mainpll_230p3m", "mainpll", 1, 7),
73 +
74 + FACTOR(CLK_TOP_UNIVPLL_624M, "univpll_624m", "univpll", 1, 2),
75 + FACTOR(CLK_TOP_UNIVPLL_416M, "univpll_416m", "univpll", 1, 3),
76 + FACTOR(CLK_TOP_UNIVPLL_249P6M, "univpll_249p6m", "univpll", 1, 5),
77 + FACTOR(CLK_TOP_UNIVPLL_178P3M, "univpll_178p3m", "univpll", 1, 7),
78 + FACTOR(CLK_TOP_UNIVPLL_48M, "univpll_48m", "univpll", 1, 26),
79 +
80 + FACTOR(CLK_TOP_MMPLL_D2, "mmpll_d2", "mmpll", 1, 2),
81 + FACTOR(CLK_TOP_MMPLL_D3, "mmpll_d3", "mmpll", 1, 3),
82 + FACTOR(CLK_TOP_MMPLL_D5, "mmpll_d5", "mmpll", 1, 5),
83 + FACTOR(CLK_TOP_MMPLL_D7, "mmpll_d7", "mmpll", 1, 7),
84 + FACTOR(CLK_TOP_MMPLL_D4, "mmpll_d4", "mmpll_d2", 1, 2),
85 + FACTOR(CLK_TOP_MMPLL_D6, "mmpll_d6", "mmpll_d3", 1, 2),
86 +
87 + FACTOR(CLK_TOP_SYSPLL_D2, "syspll_d2", "mainpll_806m", 1, 1),
88 + FACTOR(CLK_TOP_SYSPLL_D4, "syspll_d4", "mainpll_806m", 1, 2),
89 + FACTOR(CLK_TOP_SYSPLL_D6, "syspll_d6", "mainpll_806m", 1, 3),
90 + FACTOR(CLK_TOP_SYSPLL_D8, "syspll_d8", "mainpll_806m", 1, 4),
91 + FACTOR(CLK_TOP_SYSPLL_D10, "syspll_d10", "mainpll_806m", 1, 5),
92 + FACTOR(CLK_TOP_SYSPLL_D12, "syspll_d12", "mainpll_806m", 1, 6),
93 + FACTOR(CLK_TOP_SYSPLL_D16, "syspll_d16", "mainpll_806m", 1, 8),
94 + FACTOR(CLK_TOP_SYSPLL_D24, "syspll_d24", "mainpll_806m", 1, 12),
95 +
96 + FACTOR(CLK_TOP_SYSPLL_D3, "syspll_d3", "mainpll_537p3m", 1, 1),
97 +
98 + FACTOR(CLK_TOP_SYSPLL_D2P5, "syspll_d2p5", "mainpll_322p4m", 2, 1),
99 + FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "mainpll_322p4m", 1, 1),
100 +
101 + FACTOR(CLK_TOP_SYSPLL_D3P5, "syspll_d3p5", "mainpll_230p3m", 2, 1),
102 +
103 + FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univpll_624m", 1, 2),
104 + FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univpll_624m", 1, 4),
105 + FACTOR(CLK_TOP_UNIVPLL1_D6, "univpll1_d6", "univpll_624m", 1, 6),
106 + FACTOR(CLK_TOP_UNIVPLL1_D8, "univpll1_d8", "univpll_624m", 1, 8),
107 + FACTOR(CLK_TOP_UNIVPLL1_D10, "univpll1_d10", "univpll_624m", 1, 10),
108 +
109 + FACTOR(CLK_TOP_UNIVPLL2_D2, "univpll2_d2", "univpll_416m", 1, 2),
110 + FACTOR(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univpll_416m", 1, 4),
111 + FACTOR(CLK_TOP_UNIVPLL2_D6, "univpll2_d6", "univpll_416m", 1, 6),
112 + FACTOR(CLK_TOP_UNIVPLL2_D8, "univpll2_d8", "univpll_416m", 1, 8),
113 +
114 + FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll_416m", 1, 1),
115 + FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll_249p6m", 1, 1),
116 + FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll_178p3m", 1, 1),
117 + FACTOR(CLK_TOP_UNIVPLL_D10, "univpll_d10", "univpll_249p6m", 1, 2),
118 + FACTOR(CLK_TOP_UNIVPLL_D26, "univpll_d26", "univpll_48m", 1, 1),
119 +
120 + FACTOR(CLK_TOP_APLL, "apll_ck", "audpll", 1, 1),
121 + FACTOR(CLK_TOP_APLL_D4, "apll_d4", "audpll", 1, 4),
122 + FACTOR(CLK_TOP_APLL_D8, "apll_d8", "audpll", 1, 8),
123 + FACTOR(CLK_TOP_APLL_D16, "apll_d16", "audpll", 1, 16),
124 + FACTOR(CLK_TOP_APLL_D24, "apll_d24", "audpll", 1, 24),
125 +
126 + FACTOR(CLK_TOP_LVDSPLL_D2, "lvdspll_d2", "lvdspll", 1, 2),
127 + FACTOR(CLK_TOP_LVDSPLL_D4, "lvdspll_d4", "lvdspll", 1, 4),
128 + FACTOR(CLK_TOP_LVDSPLL_D8, "lvdspll_d8", "lvdspll", 1, 8),
129 +
130 + FACTOR(CLK_TOP_LVDSTX_CLKDIG_CT, "lvdstx_clkdig_cts", "lvdspll", 1, 1),
131 + FACTOR(CLK_TOP_VPLL_DPIX, "vpll_dpix_ck", "lvdspll", 1, 1),
132 +
133 + FACTOR(CLK_TOP_TVHDMI_H, "tvhdmi_h_ck", "tvdpll", 1, 1),
134 +
135 + FACTOR(CLK_TOP_HDMITX_CLKDIG_D2, "hdmitx_clkdig_d2", "hdmitx_clkdig_cts", 1, 2),
136 + FACTOR(CLK_TOP_HDMITX_CLKDIG_D3, "hdmitx_clkdig_d3", "hdmitx_clkdig_cts", 1, 3),
137 +
138 + FACTOR(CLK_TOP_TVHDMI_D2, "tvhdmi_d2", "tvhdmi_h_ck", 1, 2),
139 + FACTOR(CLK_TOP_TVHDMI_D4, "tvhdmi_d4", "tvhdmi_h_ck", 1, 4),
140 +
141 + FACTOR(CLK_TOP_MEMPLL_MCK_D4, "mempll_mck_d4", "clkph_mck", 1, 4),
142 +};
143 +
144 +static const char * const axi_parents[] __initconst = {
145 + "clk26m",
146 + "syspll_d3",
147 + "syspll_d4",
148 + "syspll_d6",
149 + "univpll_d5",
150 + "univpll2_d2",
151 + "syspll_d3p5"
152 +};
153 +
154 +static const char * const smi_parents[] __initconst = {
155 + "clk26m",
156 + "clkph_mck",
157 + "syspll_d2p5",
158 + "syspll_d3",
159 + "syspll_d8",
160 + "univpll_d5",
161 + "univpll1_d2",
162 + "univpll1_d6",
163 + "mmpll_d3",
164 + "mmpll_d4",
165 + "mmpll_d5",
166 + "mmpll_d6",
167 + "mmpll_d7",
168 + "vdecpll",
169 + "lvdspll"
170 +};
171 +
172 +static const char * const mfg_parents[] __initconst = {
173 + "clk26m",
174 + "univpll1_d4",
175 + "syspll_d2",
176 + "syspll_d2p5",
177 + "syspll_d3",
178 + "univpll_d5",
179 + "univpll1_d2",
180 + "mmpll_d2",
181 + "mmpll_d3",
182 + "mmpll_d4",
183 + "mmpll_d5",
184 + "mmpll_d6",
185 + "mmpll_d7"
186 +};
187 +
188 +static const char * const irda_parents[] __initconst = {
189 + "clk26m",
190 + "univpll2_d8",
191 + "univpll1_d6"
192 +};
193 +
194 +static const char * const cam_parents[] __initconst = {
195 + "clk26m",
196 + "syspll_d3",
197 + "syspll_d3p5",
198 + "syspll_d4",
199 + "univpll_d5",
200 + "univpll2_d2",
201 + "univpll_d7",
202 + "univpll1_d4"
203 +};
204 +
205 +static const char * const aud_intbus_parents[] __initconst = {
206 + "clk26m",
207 + "syspll_d6",
208 + "univpll_d10"
209 +};
210 +
211 +static const char * const jpg_parents[] __initconst = {
212 + "clk26m",
213 + "syspll_d5",
214 + "syspll_d4",
215 + "syspll_d3",
216 + "univpll_d7",
217 + "univpll2_d2",
218 + "univpll_d5"
219 +};
220 +
221 +static const char * const disp_parents[] __initconst = {
222 + "clk26m",
223 + "syspll_d3p5",
224 + "syspll_d3",
225 + "univpll2_d2",
226 + "univpll_d5",
227 + "univpll1_d2",
228 + "lvdspll",
229 + "vdecpll"
230 +};
231 +
232 +static const char * const msdc30_parents[] __initconst = {
233 + "clk26m",
234 + "syspll_d6",
235 + "syspll_d5",
236 + "univpll1_d4",
237 + "univpll2_d4",
238 + "msdcpll"
239 +};
240 +
241 +static const char * const usb20_parents[] __initconst = {
242 + "clk26m",
243 + "univpll2_d6",
244 + "univpll1_d10"
245 +};
246 +
247 +static const char * const venc_parents[] __initconst = {
248 + "clk26m",
249 + "syspll_d3",
250 + "syspll_d8",
251 + "univpll_d5",
252 + "univpll1_d6",
253 + "mmpll_d4",
254 + "mmpll_d5",
255 + "mmpll_d6"
256 +};
257 +
258 +static const char * const spi_parents[] __initconst = {
259 + "clk26m",
260 + "syspll_d6",
261 + "syspll_d8",
262 + "syspll_d10",
263 + "univpll1_d6",
264 + "univpll1_d8"
265 +};
266 +
267 +static const char * const uart_parents[] __initconst = {
268 + "clk26m",
269 + "univpll2_d8"
270 +};
271 +
272 +static const char * const mem_parents[] __initconst = {
273 + "clk26m",
274 + "clkph_mck"
275 +};
276 +
277 +static const char * const camtg_parents[] __initconst = {
278 + "clk26m",
279 + "univpll_d26",
280 + "univpll1_d6",
281 + "syspll_d16",
282 + "syspll_d8"
283 +};
284 +
285 +static const char * const audio_parents[] __initconst = {
286 + "clk26m",
287 + "syspll_d24"
288 +};
289 +
290 +static const char * const fix_parents[] __initconst = {
291 + "rtc32k",
292 + "clk26m",
293 + "univpll_d5",
294 + "univpll_d7",
295 + "univpll1_d2",
296 + "univpll1_d4",
297 + "univpll1_d6",
298 + "univpll1_d8"
299 +};
300 +
301 +static const char * const vdec_parents[] __initconst = {
302 + "clk26m",
303 + "vdecpll",
304 + "clkph_mck",
305 + "syspll_d2p5",
306 + "syspll_d3",
307 + "syspll_d3p5",
308 + "syspll_d4",
309 + "syspll_d5",
310 + "syspll_d6",
311 + "syspll_d8",
312 + "univpll1_d2",
313 + "univpll2_d2",
314 + "univpll_d7",
315 + "univpll_d10",
316 + "univpll2_d4",
317 + "lvdspll"
318 +};
319 +
320 +static const char * const ddrphycfg_parents[] __initconst = {
321 + "clk26m",
322 + "axi_sel",
323 + "syspll_d12"
324 +};
325 +
326 +static const char * const dpilvds_parents[] __initconst = {
327 + "clk26m",
328 + "lvdspll",
329 + "lvdspll_d2",
330 + "lvdspll_d4",
331 + "lvdspll_d8"
332 +};
333 +
334 +static const char * const pmicspi_parents[] __initconst = {
335 + "clk26m",
336 + "univpll2_d6",
337 + "syspll_d8",
338 + "syspll_d10",
339 + "univpll1_d10",
340 + "mempll_mck_d4",
341 + "univpll_d26",
342 + "syspll_d24"
343 +};
344 +
345 +static const char * const smi_mfg_as_parents[] __initconst = {
346 + "clk26m",
347 + "smi_sel",
348 + "mfg_sel",
349 + "mem_sel"
350 +};
351 +
352 +static const char * const gcpu_parents[] __initconst = {
353 + "clk26m",
354 + "syspll_d4",
355 + "univpll_d7",
356 + "syspll_d5",
357 + "syspll_d6"
358 +};
359 +
360 +static const char * const dpi1_parents[] __initconst = {
361 + "clk26m",
362 + "tvhdmi_h_ck",
363 + "tvhdmi_d2",
364 + "tvhdmi_d4"
365 +};
366 +
367 +static const char * const cci_parents[] __initconst = {
368 + "clk26m",
369 + "mainpll_537p3m",
370 + "univpll_d3",
371 + "syspll_d2p5",
372 + "syspll_d3",
373 + "syspll_d5"
374 +};
375 +
376 +static const char * const apll_parents[] __initconst = {
377 + "clk26m",
378 + "apll_ck",
379 + "apll_d4",
380 + "apll_d8",
381 + "apll_d16",
382 + "apll_d24"
383 +};
384 +
385 +static const char * const hdmipll_parents[] __initconst = {
386 + "clk26m",
387 + "hdmitx_clkdig_cts",
388 + "hdmitx_clkdig_d2",
389 + "hdmitx_clkdig_d3"
390 +};
391 +
392 +static const struct mtk_composite top_muxes[] __initconst = {
393 + /* CLK_CFG_0 */
394 + MUX_GATE(CLK_TOP_AXI_SEL, "axi_sel", axi_parents,
395 + 0x0140, 0, 3, INVALID_MUX_GATE_BIT),
396 + MUX_GATE(CLK_TOP_SMI_SEL, "smi_sel", smi_parents, 0x0140, 8, 4, 15),
397 + MUX_GATE(CLK_TOP_MFG_SEL, "mfg_sel", mfg_parents, 0x0140, 16, 4, 23),
398 + MUX_GATE(CLK_TOP_IRDA_SEL, "irda_sel", irda_parents, 0x0140, 24, 2, 31),
399 + /* CLK_CFG_1 */
400 + MUX_GATE(CLK_TOP_CAM_SEL, "cam_sel", cam_parents, 0x0144, 0, 3, 7),
401 + MUX_GATE(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel", aud_intbus_parents,
402 + 0x0144, 8, 2, 15),
403 + MUX_GATE(CLK_TOP_JPG_SEL, "jpg_sel", jpg_parents, 0x0144, 16, 3, 23),
404 + MUX_GATE(CLK_TOP_DISP_SEL, "disp_sel", disp_parents, 0x0144, 24, 3, 31),
405 + /* CLK_CFG_2 */
406 + MUX_GATE(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel", msdc30_parents, 0x0148, 0, 3, 7),
407 + MUX_GATE(CLK_TOP_MSDC30_2_SEL, "msdc30_2_sel", msdc30_parents, 0x0148, 8, 3, 15),
408 + MUX_GATE(CLK_TOP_MSDC30_3_SEL, "msdc30_3_sel", msdc30_parents, 0x0148, 16, 3, 23),
409 + MUX_GATE(CLK_TOP_MSDC30_4_SEL, "msdc30_4_sel", msdc30_parents, 0x0148, 24, 3, 31),
410 + /* CLK_CFG_3 */
411 + MUX_GATE(CLK_TOP_USB20_SEL, "usb20_sel", usb20_parents, 0x014c, 0, 2, 7),
412 + /* CLK_CFG_4 */
413 + MUX_GATE(CLK_TOP_VENC_SEL, "venc_sel", venc_parents, 0x0150, 8, 3, 15),
414 + MUX_GATE(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x0150, 16, 3, 23),
415 + MUX_GATE(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x0150, 24, 2, 31),
416 + /* CLK_CFG_6 */
417 + MUX_GATE(CLK_TOP_MEM_SEL, "mem_sel", mem_parents, 0x0158, 0, 2, 7),
418 + MUX_GATE(CLK_TOP_CAMTG_SEL, "camtg_sel", camtg_parents, 0x0158, 8, 3, 15),
419 + MUX_GATE(CLK_TOP_AUDIO_SEL, "audio_sel", audio_parents, 0x0158, 24, 2, 31),
420 + /* CLK_CFG_7 */
421 + MUX_GATE(CLK_TOP_FIX_SEL, "fix_sel", fix_parents, 0x015c, 0, 3, 7),
422 + MUX_GATE(CLK_TOP_VDEC_SEL, "vdec_sel", vdec_parents, 0x015c, 8, 4, 15),
423 + MUX_GATE(CLK_TOP_DDRPHYCFG_SEL, "ddrphycfg_sel", ddrphycfg_parents,
424 + 0x015c, 16, 2, 23),
425 + MUX_GATE(CLK_TOP_DPILVDS_SEL, "dpilvds_sel", dpilvds_parents, 0x015c, 24, 3, 31),
426 + /* CLK_CFG_8 */
427 + MUX_GATE(CLK_TOP_PMICSPI_SEL, "pmicspi_sel", pmicspi_parents, 0x0164, 0, 3, 7),
428 + MUX_GATE(CLK_TOP_MSDC30_0_SEL, "msdc30_0_sel", msdc30_parents, 0x0164, 8, 3, 15),
429 + MUX_GATE(CLK_TOP_SMI_MFG_AS_SEL, "smi_mfg_as_sel", smi_mfg_as_parents,
430 + 0x0164, 16, 2, 23),
431 + MUX_GATE(CLK_TOP_GCPU_SEL, "gcpu_sel", gcpu_parents, 0x0164, 24, 3, 31),
432 + /* CLK_CFG_9 */
433 + MUX_GATE(CLK_TOP_DPI1_SEL, "dpi1_sel", dpi1_parents, 0x0168, 0, 2, 7),
434 + MUX_GATE(CLK_TOP_CCI_SEL, "cci_sel", cci_parents, 0x0168, 8, 3, 15),
435 + MUX_GATE(CLK_TOP_APLL_SEL, "apll_sel", apll_parents, 0x0168, 16, 3, 23),
436 + MUX_GATE(CLK_TOP_HDMIPLL_SEL, "hdmipll_sel", hdmipll_parents, 0x0168, 24, 2, 31),
437 +};
438 +
439 +static const struct mtk_gate_regs infra_cg_regs = {
440 + .set_ofs = 0x0040,
441 + .clr_ofs = 0x0044,
442 + .sta_ofs = 0x0048,
443 +};
444 +
445 +#define GATE_ICG(_id, _name, _parent, _shift) { \
446 + .id = _id, \
447 + .name = _name, \
448 + .parent_name = _parent, \
449 + .regs = &infra_cg_regs, \
450 + .shift = _shift, \
451 + .ops = &mtk_clk_gate_ops_setclr, \
452 + }
453 +
454 +static const struct mtk_gate infra_clks[] __initconst = {
455 + GATE_ICG(CLK_INFRA_PMIC_WRAP, "pmic_wrap_ck", "axi_sel", 23),
456 + GATE_ICG(CLK_INFRA_PMICSPI, "pmicspi_ck", "pmicspi_sel", 22),
457 + GATE_ICG(CLK_INFRA_CCIF1_AP_CTRL, "ccif1_ap_ctrl", "axi_sel", 21),
458 + GATE_ICG(CLK_INFRA_CCIF0_AP_CTRL, "ccif0_ap_ctrl", "axi_sel", 20),
459 + GATE_ICG(CLK_INFRA_KP, "kp_ck", "axi_sel", 16),
460 + GATE_ICG(CLK_INFRA_CPUM, "cpum_ck", "cpum_tck_in", 15),
461 + GATE_ICG(CLK_INFRA_M4U, "m4u_ck", "mem_sel", 8),
462 + GATE_ICG(CLK_INFRA_MFGAXI, "mfgaxi_ck", "axi_sel", 7),
463 + GATE_ICG(CLK_INFRA_DEVAPC, "devapc_ck", "axi_sel", 6),
464 + GATE_ICG(CLK_INFRA_AUDIO, "audio_ck", "aud_intbus_sel", 5),
465 + GATE_ICG(CLK_INFRA_MFG_BUS, "mfg_bus_ck", "axi_sel", 2),
466 + GATE_ICG(CLK_INFRA_SMI, "smi_ck", "smi_sel", 1),
467 + GATE_ICG(CLK_INFRA_DBGCLK, "dbgclk_ck", "axi_sel", 0),
468 +};
469 +
470 +static const struct mtk_gate_regs peri0_cg_regs = {
471 + .set_ofs = 0x0008,
472 + .clr_ofs = 0x0010,
473 + .sta_ofs = 0x0018,
474 +};
475 +
476 +static const struct mtk_gate_regs peri1_cg_regs = {
477 + .set_ofs = 0x000c,
478 + .clr_ofs = 0x0014,
479 + .sta_ofs = 0x001c,
480 +};
481 +
482 +#define GATE_PERI0(_id, _name, _parent, _shift) { \
483 + .id = _id, \
484 + .name = _name, \
485 + .parent_name = _parent, \
486 + .regs = &peri0_cg_regs, \
487 + .shift = _shift, \
488 + .ops = &mtk_clk_gate_ops_setclr, \
489 + }
490 +
491 +#define GATE_PERI1(_id, _name, _parent, _shift) { \
492 + .id = _id, \
493 + .name = _name, \
494 + .parent_name = _parent, \
495 + .regs = &peri1_cg_regs, \
496 + .shift = _shift, \
497 + .ops = &mtk_clk_gate_ops_setclr, \
498 + }
499 +
500 +static const struct mtk_gate peri_gates[] __initconst = {
501 + /* PERI0 */
502 + GATE_PERI0(CLK_PERI_I2C5, "i2c5_ck", "axi_sel", 31),
503 + GATE_PERI0(CLK_PERI_I2C4, "i2c4_ck", "axi_sel", 30),
504 + GATE_PERI0(CLK_PERI_I2C3, "i2c3_ck", "axi_sel", 29),
505 + GATE_PERI0(CLK_PERI_I2C2, "i2c2_ck", "axi_sel", 28),
506 + GATE_PERI0(CLK_PERI_I2C1, "i2c1_ck", "axi_sel", 27),
507 + GATE_PERI0(CLK_PERI_I2C0, "i2c0_ck", "axi_sel", 26),
508 + GATE_PERI0(CLK_PERI_UART3, "uart3_ck", "axi_sel", 25),
509 + GATE_PERI0(CLK_PERI_UART2, "uart2_ck", "axi_sel", 24),
510 + GATE_PERI0(CLK_PERI_UART1, "uart1_ck", "axi_sel", 23),
511 + GATE_PERI0(CLK_PERI_UART0, "uart0_ck", "axi_sel", 22),
512 + GATE_PERI0(CLK_PERI_IRDA, "irda_ck", "irda_sel", 21),
513 + GATE_PERI0(CLK_PERI_NLI, "nli_ck", "axi_sel", 20),
514 + GATE_PERI0(CLK_PERI_MD_HIF, "md_hif_ck", "axi_sel", 19),
515 + GATE_PERI0(CLK_PERI_AP_HIF, "ap_hif_ck", "axi_sel", 18),
516 + GATE_PERI0(CLK_PERI_MSDC30_3, "msdc30_3_ck", "msdc30_4_sel", 17),
517 + GATE_PERI0(CLK_PERI_MSDC30_2, "msdc30_2_ck", "msdc30_3_sel", 16),
518 + GATE_PERI0(CLK_PERI_MSDC30_1, "msdc30_1_ck", "msdc30_2_sel", 15),
519 + GATE_PERI0(CLK_PERI_MSDC20_2, "msdc20_2_ck", "msdc30_1_sel", 14),
520 + GATE_PERI0(CLK_PERI_MSDC20_1, "msdc20_1_ck", "msdc30_0_sel", 13),
521 + GATE_PERI0(CLK_PERI_AP_DMA, "ap_dma_ck", "axi_sel", 12),
522 + GATE_PERI0(CLK_PERI_USB1, "usb1_ck", "usb20_sel", 11),
523 + GATE_PERI0(CLK_PERI_USB0, "usb0_ck", "usb20_sel", 10),
524 + GATE_PERI0(CLK_PERI_PWM, "pwm_ck", "axi_sel", 9),
525 + GATE_PERI0(CLK_PERI_PWM7, "pwm7_ck", "axi_sel", 8),
526 + GATE_PERI0(CLK_PERI_PWM6, "pwm6_ck", "axi_sel", 7),
527 + GATE_PERI0(CLK_PERI_PWM5, "pwm5_ck", "axi_sel", 6),
528 + GATE_PERI0(CLK_PERI_PWM4, "pwm4_ck", "axi_sel", 5),
529 + GATE_PERI0(CLK_PERI_PWM3, "pwm3_ck", "axi_sel", 4),
530 + GATE_PERI0(CLK_PERI_PWM2, "pwm2_ck", "axi_sel", 3),
531 + GATE_PERI0(CLK_PERI_PWM1, "pwm1_ck", "axi_sel", 2),
532 + GATE_PERI0(CLK_PERI_THERM, "therm_ck", "axi_sel", 1),
533 + GATE_PERI0(CLK_PERI_NFI, "nfi_ck", "axi_sel", 0),
534 + /* PERI1 */
535 + GATE_PERI1(CLK_PERI_USBSLV, "usbslv_ck", "axi_sel", 8),
536 + GATE_PERI1(CLK_PERI_USB1_MCU, "usb1_mcu_ck", "axi_sel", 7),
537 + GATE_PERI1(CLK_PERI_USB0_MCU, "usb0_mcu_ck", "axi_sel", 6),
538 + GATE_PERI1(CLK_PERI_GCPU, "gcpu_ck", "gcpu_sel", 5),
539 + GATE_PERI1(CLK_PERI_FHCTL, "fhctl_ck", "clk26m", 4),
540 + GATE_PERI1(CLK_PERI_SPI1, "spi1_ck", "spi_sel", 3),
541 + GATE_PERI1(CLK_PERI_AUXADC, "auxadc_ck", "clk26m", 2),
542 + GATE_PERI1(CLK_PERI_PERI_PWRAP, "peri_pwrap_ck", "axi_sel", 1),
543 + GATE_PERI1(CLK_PERI_I2C6, "i2c6_ck", "axi_sel", 0),
544 +};
545 +
546 +static const char * const uart_ck_sel_parents[] __initconst = {
547 + "clk26m",
548 + "uart_sel",
549 +};
550 +
551 +static const struct mtk_composite peri_clks[] __initconst = {
552 + MUX(CLK_PERI_UART0_SEL, "uart0_ck_sel", uart_ck_sel_parents, 0x40c, 0, 1),
553 + MUX(CLK_PERI_UART1_SEL, "uart1_ck_sel", uart_ck_sel_parents, 0x40c, 1, 1),
554 + MUX(CLK_PERI_UART2_SEL, "uart2_ck_sel", uart_ck_sel_parents, 0x40c, 2, 1),
555 + MUX(CLK_PERI_UART3_SEL, "uart3_ck_sel", uart_ck_sel_parents, 0x40c, 3, 1),
556 +};
557 +
558 +static void __init mtk_topckgen_init(struct device_node *node)
559 +{
560 + struct clk_onecell_data *clk_data;
561 + void __iomem *base;
562 + int r;
563 +
564 + base = of_iomap(node, 0);
565 + if (!base) {
566 + pr_err("%s(): ioremap failed\n", __func__);
567 + return;
568 + }
569 +
570 + clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK);
571 +
572 + mtk_clk_register_factors(root_clk_alias, ARRAY_SIZE(root_clk_alias), clk_data);
573 + mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data);
574 + mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), base,
575 + &mt8135_clk_lock, clk_data);
576 +
577 + clk_prepare_enable(clk_data->clks[CLK_TOP_CCI_SEL]);
578 +
579 + r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
580 + if (r)
581 + pr_err("%s(): could not register clock provider: %d\n",
582 + __func__, r);
583 +}
584 +CLK_OF_DECLARE(mtk_topckgen, "mediatek,mt8135-topckgen", mtk_topckgen_init);
585 +
586 +static void __init mtk_infrasys_init(struct device_node *node)
587 +{
588 + struct clk_onecell_data *clk_data;
589 + int r;
590 +
591 + clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK);
592 +
593 + mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
594 + clk_data);
595 +
596 + clk_prepare_enable(clk_data->clks[CLK_INFRA_M4U]);
597 +
598 + r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
599 + if (r)
600 + pr_err("%s(): could not register clock provider: %d\n",
601 + __func__, r);
602 +
603 + mtk_register_reset_controller(node, 2, 0x30);
604 +}
605 +CLK_OF_DECLARE(mtk_infrasys, "mediatek,mt8135-infracfg", mtk_infrasys_init);
606 +
607 +static void __init mtk_pericfg_init(struct device_node *node)
608 +{
609 + struct clk_onecell_data *clk_data;
610 + int r;
611 + void __iomem *base;
612 +
613 + base = of_iomap(node, 0);
614 + if (!base) {
615 + pr_err("%s(): ioremap failed\n", __func__);
616 + return;
617 + }
618 +
619 + clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK);
620 +
621 + mtk_clk_register_gates(node, peri_gates, ARRAY_SIZE(peri_gates),
622 + clk_data);
623 + mtk_clk_register_composites(peri_clks, ARRAY_SIZE(peri_clks), base,
624 + &mt8135_clk_lock, clk_data);
625 +
626 + r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
627 + if (r)
628 + pr_err("%s(): could not register clock provider: %d\n",
629 + __func__, r);
630 +
631 + mtk_register_reset_controller(node, 2, 0);
632 +}
633 +CLK_OF_DECLARE(mtk_pericfg, "mediatek,mt8135-pericfg", mtk_pericfg_init);
634 +
635 +#define MT8135_PLL_FMAX (2000 * MHZ)
636 +#define CON0_MT8135_RST_BAR BIT(27)
637 +
638 +#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift) { \
639 + .id = _id, \
640 + .name = _name, \
641 + .reg = _reg, \
642 + .pwr_reg = _pwr_reg, \
643 + .en_mask = _en_mask, \
644 + .flags = _flags, \
645 + .rst_bar_mask = CON0_MT8135_RST_BAR, \
646 + .fmax = MT8135_PLL_FMAX, \
647 + .pcwbits = _pcwbits, \
648 + .pd_reg = _pd_reg, \
649 + .pd_shift = _pd_shift, \
650 + .tuner_reg = _tuner_reg, \
651 + .pcw_reg = _pcw_reg, \
652 + .pcw_shift = _pcw_shift, \
653 + }
654 +
655 +static const struct mtk_pll_data plls[] = {
656 + PLL(CLK_APMIXED_ARMPLL1, "armpll1", 0x200, 0x218, 0x80000001, 0, 21, 0x204, 24, 0x0, 0x204, 0),
657 + PLL(CLK_APMIXED_ARMPLL2, "armpll2", 0x2cc, 0x2e4, 0x80000001, 0, 21, 0x2d0, 24, 0x0, 0x2d0, 0),
658 + PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x21c, 0x234, 0xf0000001, HAVE_RST_BAR, 21, 0x21c, 6, 0x0, 0x220, 0),
659 + PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x238, 0x250, 0xf3000001, HAVE_RST_BAR, 7, 0x238, 6, 0x0, 0x238, 9),
660 + PLL(CLK_APMIXED_MMPLL, "mmpll", 0x254, 0x26c, 0xf0000001, HAVE_RST_BAR, 21, 0x254, 6, 0x0, 0x258, 0),
661 + PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x278, 0x290, 0x80000001, 0, 21, 0x278, 6, 0x0, 0x27c, 0),
662 + PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x294, 0x2ac, 0x80000001, 0, 31, 0x294, 6, 0x0, 0x298, 0),
663 + PLL(CLK_APMIXED_LVDSPLL, "lvdspll", 0x2b0, 0x2c8, 0x80000001, 0, 21, 0x2b0, 6, 0x0, 0x2b4, 0),
664 + PLL(CLK_APMIXED_AUDPLL, "audpll", 0x2e8, 0x300, 0x80000001, 0, 31, 0x2e8, 6, 0x2f8, 0x2ec, 0),
665 + PLL(CLK_APMIXED_VDECPLL, "vdecpll", 0x304, 0x31c, 0x80000001, 0, 21, 0x2b0, 6, 0x0, 0x308, 0),
666 +};
667 +
668 +static void __init mtk_apmixedsys_init(struct device_node *node)
669 +{
670 + struct clk_onecell_data *clk_data;
671 +
672 + clk_data = mtk_alloc_clk_data(ARRAY_SIZE(plls));
673 + if (!clk_data)
674 + return;
675 +
676 + mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
677 +}
678 +CLK_OF_DECLARE(mtk_apmixedsys, "mediatek,mt8135-apmixedsys",
679 + mtk_apmixedsys_init);
680 diff --git a/include/dt-bindings/clock/mt8135-clk.h b/include/dt-bindings/clock/mt8135-clk.h
681 new file mode 100644
682 index 0000000..6dac6c0
683 --- /dev/null
684 +++ b/include/dt-bindings/clock/mt8135-clk.h
685 @@ -0,0 +1,194 @@
686 +/*
687 + * Copyright (c) 2014 MediaTek Inc.
688 + * Author: James Liao <jamesjj.liao@mediatek.com>
689 + *
690 + * This program is free software; you can redistribute it and/or modify
691 + * it under the terms of the GNU General Public License version 2 as
692 + * published by the Free Software Foundation.
693 + *
694 + * This program is distributed in the hope that it will be useful,
695 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
696 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
697 + * GNU General Public License for more details.
698 + */
699 +
700 +#ifndef _DT_BINDINGS_CLK_MT8135_H
701 +#define _DT_BINDINGS_CLK_MT8135_H
702 +
703 +/* TOPCKGEN */
704 +
705 +#define CLK_TOP_DSI0_LNTC_DSICLK 1
706 +#define CLK_TOP_HDMITX_CLKDIG_CTS 2
707 +#define CLK_TOP_CLKPH_MCK 3
708 +#define CLK_TOP_CPUM_TCK_IN 4
709 +#define CLK_TOP_MAINPLL_806M 5
710 +#define CLK_TOP_MAINPLL_537P3M 6
711 +#define CLK_TOP_MAINPLL_322P4M 7
712 +#define CLK_TOP_MAINPLL_230P3M 8
713 +#define CLK_TOP_UNIVPLL_624M 9
714 +#define CLK_TOP_UNIVPLL_416M 10
715 +#define CLK_TOP_UNIVPLL_249P6M 11
716 +#define CLK_TOP_UNIVPLL_178P3M 12
717 +#define CLK_TOP_UNIVPLL_48M 13
718 +#define CLK_TOP_MMPLL_D2 14
719 +#define CLK_TOP_MMPLL_D3 15
720 +#define CLK_TOP_MMPLL_D5 16
721 +#define CLK_TOP_MMPLL_D7 17
722 +#define CLK_TOP_MMPLL_D4 18
723 +#define CLK_TOP_MMPLL_D6 19
724 +#define CLK_TOP_SYSPLL_D2 20
725 +#define CLK_TOP_SYSPLL_D4 21
726 +#define CLK_TOP_SYSPLL_D6 22
727 +#define CLK_TOP_SYSPLL_D8 23
728 +#define CLK_TOP_SYSPLL_D10 24
729 +#define CLK_TOP_SYSPLL_D12 25
730 +#define CLK_TOP_SYSPLL_D16 26
731 +#define CLK_TOP_SYSPLL_D24 27
732 +#define CLK_TOP_SYSPLL_D3 28
733 +#define CLK_TOP_SYSPLL_D2P5 29
734 +#define CLK_TOP_SYSPLL_D5 30
735 +#define CLK_TOP_SYSPLL_D3P5 31
736 +#define CLK_TOP_UNIVPLL1_D2 32
737 +#define CLK_TOP_UNIVPLL1_D4 33
738 +#define CLK_TOP_UNIVPLL1_D6 34
739 +#define CLK_TOP_UNIVPLL1_D8 35
740 +#define CLK_TOP_UNIVPLL1_D10 36
741 +#define CLK_TOP_UNIVPLL2_D2 37
742 +#define CLK_TOP_UNIVPLL2_D4 38
743 +#define CLK_TOP_UNIVPLL2_D6 39
744 +#define CLK_TOP_UNIVPLL2_D8 40
745 +#define CLK_TOP_UNIVPLL_D3 41
746 +#define CLK_TOP_UNIVPLL_D5 42
747 +#define CLK_TOP_UNIVPLL_D7 43
748 +#define CLK_TOP_UNIVPLL_D10 44
749 +#define CLK_TOP_UNIVPLL_D26 45
750 +#define CLK_TOP_APLL 46
751 +#define CLK_TOP_APLL_D4 47
752 +#define CLK_TOP_APLL_D8 48
753 +#define CLK_TOP_APLL_D16 49
754 +#define CLK_TOP_APLL_D24 50
755 +#define CLK_TOP_LVDSPLL_D2 51
756 +#define CLK_TOP_LVDSPLL_D4 52
757 +#define CLK_TOP_LVDSPLL_D8 53
758 +#define CLK_TOP_LVDSTX_CLKDIG_CT 54
759 +#define CLK_TOP_VPLL_DPIX 55
760 +#define CLK_TOP_TVHDMI_H 56
761 +#define CLK_TOP_HDMITX_CLKDIG_D2 57
762 +#define CLK_TOP_HDMITX_CLKDIG_D3 58
763 +#define CLK_TOP_TVHDMI_D2 59
764 +#define CLK_TOP_TVHDMI_D4 60
765 +#define CLK_TOP_MEMPLL_MCK_D4 61
766 +#define CLK_TOP_AXI_SEL 62
767 +#define CLK_TOP_SMI_SEL 63
768 +#define CLK_TOP_MFG_SEL 64
769 +#define CLK_TOP_IRDA_SEL 65
770 +#define CLK_TOP_CAM_SEL 66
771 +#define CLK_TOP_AUD_INTBUS_SEL 67
772 +#define CLK_TOP_JPG_SEL 68
773 +#define CLK_TOP_DISP_SEL 69
774 +#define CLK_TOP_MSDC30_1_SEL 70
775 +#define CLK_TOP_MSDC30_2_SEL 71
776 +#define CLK_TOP_MSDC30_3_SEL 72
777 +#define CLK_TOP_MSDC30_4_SEL 73
778 +#define CLK_TOP_USB20_SEL 74
779 +#define CLK_TOP_VENC_SEL 75
780 +#define CLK_TOP_SPI_SEL 76
781 +#define CLK_TOP_UART_SEL 77
782 +#define CLK_TOP_MEM_SEL 78
783 +#define CLK_TOP_CAMTG_SEL 79
784 +#define CLK_TOP_AUDIO_SEL 80
785 +#define CLK_TOP_FIX_SEL 81
786 +#define CLK_TOP_VDEC_SEL 82
787 +#define CLK_TOP_DDRPHYCFG_SEL 83
788 +#define CLK_TOP_DPILVDS_SEL 84
789 +#define CLK_TOP_PMICSPI_SEL 85
790 +#define CLK_TOP_MSDC30_0_SEL 86
791 +#define CLK_TOP_SMI_MFG_AS_SEL 87
792 +#define CLK_TOP_GCPU_SEL 88
793 +#define CLK_TOP_DPI1_SEL 89
794 +#define CLK_TOP_CCI_SEL 90
795 +#define CLK_TOP_APLL_SEL 91
796 +#define CLK_TOP_HDMIPLL_SEL 92
797 +#define CLK_TOP_NR_CLK 93
798 +
799 +/* APMIXED_SYS */
800 +
801 +#define CLK_APMIXED_ARMPLL1 1
802 +#define CLK_APMIXED_ARMPLL2 2
803 +#define CLK_APMIXED_MAINPLL 3
804 +#define CLK_APMIXED_UNIVPLL 4
805 +#define CLK_APMIXED_MMPLL 5
806 +#define CLK_APMIXED_MSDCPLL 6
807 +#define CLK_APMIXED_TVDPLL 7
808 +#define CLK_APMIXED_LVDSPLL 8
809 +#define CLK_APMIXED_AUDPLL 9
810 +#define CLK_APMIXED_VDECPLL 10
811 +#define CLK_APMIXED_NR_CLK 11
812 +
813 +/* INFRA_SYS */
814 +
815 +#define CLK_INFRA_PMIC_WRAP 1
816 +#define CLK_INFRA_PMICSPI 2
817 +#define CLK_INFRA_CCIF1_AP_CTRL 3
818 +#define CLK_INFRA_CCIF0_AP_CTRL 4
819 +#define CLK_INFRA_KP 5
820 +#define CLK_INFRA_CPUM 6
821 +#define CLK_INFRA_M4U 7
822 +#define CLK_INFRA_MFGAXI 8
823 +#define CLK_INFRA_DEVAPC 9
824 +#define CLK_INFRA_AUDIO 10
825 +#define CLK_INFRA_MFG_BUS 11
826 +#define CLK_INFRA_SMI 12
827 +#define CLK_INFRA_DBGCLK 13
828 +#define CLK_INFRA_NR_CLK 14
829 +
830 +/* PERI_SYS */
831 +
832 +#define CLK_PERI_I2C5 1
833 +#define CLK_PERI_I2C4 2
834 +#define CLK_PERI_I2C3 3
835 +#define CLK_PERI_I2C2 4
836 +#define CLK_PERI_I2C1 5
837 +#define CLK_PERI_I2C0 6
838 +#define CLK_PERI_UART3 7
839 +#define CLK_PERI_UART2 8
840 +#define CLK_PERI_UART1 9
841 +#define CLK_PERI_UART0 10
842 +#define CLK_PERI_IRDA 11
843 +#define CLK_PERI_NLI 12
844 +#define CLK_PERI_MD_HIF 13
845 +#define CLK_PERI_AP_HIF 14
846 +#define CLK_PERI_MSDC30_3 15
847 +#define CLK_PERI_MSDC30_2 16
848 +#define CLK_PERI_MSDC30_1 17
849 +#define CLK_PERI_MSDC20_2 18
850 +#define CLK_PERI_MSDC20_1 19
851 +#define CLK_PERI_AP_DMA 20
852 +#define CLK_PERI_USB1 21
853 +#define CLK_PERI_USB0 22
854 +#define CLK_PERI_PWM 23
855 +#define CLK_PERI_PWM7 24
856 +#define CLK_PERI_PWM6 25
857 +#define CLK_PERI_PWM5 26
858 +#define CLK_PERI_PWM4 27
859 +#define CLK_PERI_PWM3 28
860 +#define CLK_PERI_PWM2 29
861 +#define CLK_PERI_PWM1 30
862 +#define CLK_PERI_THERM 31
863 +#define CLK_PERI_NFI 32
864 +#define CLK_PERI_USBSLV 33
865 +#define CLK_PERI_USB1_MCU 34
866 +#define CLK_PERI_USB0_MCU 35
867 +#define CLK_PERI_GCPU 36
868 +#define CLK_PERI_FHCTL 37
869 +#define CLK_PERI_SPI1 38
870 +#define CLK_PERI_AUXADC 39
871 +#define CLK_PERI_PERI_PWRAP 40
872 +#define CLK_PERI_I2C6 41
873 +#define CLK_PERI_UART0_SEL 42
874 +#define CLK_PERI_UART1_SEL 43
875 +#define CLK_PERI_UART2_SEL 44
876 +#define CLK_PERI_UART3_SEL 45
877 +#define CLK_PERI_NR_CLK 46
878 +
879 +#endif /* _DT_BINDINGS_CLK_MT8135_H */
880 diff --git a/include/dt-bindings/reset-controller/mt8135-resets.h b/include/dt-bindings/reset-controller/mt8135-resets.h
881 new file mode 100644
882 index 0000000..1fb6295
883 --- /dev/null
884 +++ b/include/dt-bindings/reset-controller/mt8135-resets.h
885 @@ -0,0 +1,64 @@
886 +/*
887 + * Copyright (c) 2014 MediaTek Inc.
888 + * Author: Flora Fu, MediaTek
889 + *
890 + * This program is free software; you can redistribute it and/or modify
891 + * it under the terms of the GNU General Public License version 2 as
892 + * published by the Free Software Foundation.
893 + *
894 + * This program is distributed in the hope that it will be useful,
895 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
896 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
897 + * GNU General Public License for more details.
898 + */
899 +
900 +#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8135
901 +#define _DT_BINDINGS_RESET_CONTROLLER_MT8135
902 +
903 +/* INFRACFG resets */
904 +#define MT8135_INFRA_EMI_REG_RST 0
905 +#define MT8135_INFRA_DRAMC0_A0_RST 1
906 +#define MT8135_INFRA_CCIF0_RST 2
907 +#define MT8135_INFRA_APCIRQ_EINT_RST 3
908 +#define MT8135_INFRA_APXGPT_RST 4
909 +#define MT8135_INFRA_SCPSYS_RST 5
910 +#define MT8135_INFRA_CCIF1_RST 6
911 +#define MT8135_INFRA_PMIC_WRAP_RST 7
912 +#define MT8135_INFRA_KP_RST 8
913 +#define MT8135_INFRA_EMI_RST 32
914 +#define MT8135_INFRA_DRAMC0_RST 34
915 +#define MT8135_INFRA_SMI_RST 35
916 +#define MT8135_INFRA_M4U_RST 36
917 +
918 +/* PERICFG resets */
919 +#define MT8135_PERI_UART0_SW_RST 0
920 +#define MT8135_PERI_UART1_SW_RST 1
921 +#define MT8135_PERI_UART2_SW_RST 2
922 +#define MT8135_PERI_UART3_SW_RST 3
923 +#define MT8135_PERI_IRDA_SW_RST 4
924 +#define MT8135_PERI_PTP_SW_RST 5
925 +#define MT8135_PERI_AP_HIF_SW_RST 6
926 +#define MT8135_PERI_GPCU_SW_RST 7
927 +#define MT8135_PERI_MD_HIF_SW_RST 8
928 +#define MT8135_PERI_NLI_SW_RST 9
929 +#define MT8135_PERI_AUXADC_SW_RST 10
930 +#define MT8135_PERI_DMA_SW_RST 11
931 +#define MT8135_PERI_NFI_SW_RST 14
932 +#define MT8135_PERI_PWM_SW_RST 15
933 +#define MT8135_PERI_THERM_SW_RST 16
934 +#define MT8135_PERI_MSDC0_SW_RST 17
935 +#define MT8135_PERI_MSDC1_SW_RST 18
936 +#define MT8135_PERI_MSDC2_SW_RST 19
937 +#define MT8135_PERI_MSDC3_SW_RST 20
938 +#define MT8135_PERI_I2C0_SW_RST 22
939 +#define MT8135_PERI_I2C1_SW_RST 23
940 +#define MT8135_PERI_I2C2_SW_RST 24
941 +#define MT8135_PERI_I2C3_SW_RST 25
942 +#define MT8135_PERI_I2C4_SW_RST 26
943 +#define MT8135_PERI_I2C5_SW_RST 27
944 +#define MT8135_PERI_I2C6_SW_RST 28
945 +#define MT8135_PERI_USB_SW_RST 29
946 +#define MT8135_PERI_SPI1_SW_RST 33
947 +#define MT8135_PERI_PWRAP_BRIDGE_SW_RST 34
948 +
949 +#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8135 */
950 --
951 1.7.10.4
952
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