1 From 87043a64dd5185dc076b3c3ab2e421b3a8c47798 Mon Sep 17 00:00:00 2001
2 From: Sascha Hauer <s.hauer@pengutronix.de>
3 Date: Thu, 23 Apr 2015 10:35:43 +0200
4 Subject: [PATCH 09/76] dt-bindings: ARM: Mediatek: Document devicetree
5 bindings for clock/reset controllers
7 This adds the binding documentation for the apmixedsys, perisys and
8 infracfg controllers found on Mediatek SoCs.
10 Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
12 .../bindings/arm/mediatek/mediatek,apmixedsys.txt | 23 +++++++++++++++
13 .../bindings/arm/mediatek/mediatek,infracfg.txt | 30 ++++++++++++++++++++
14 .../bindings/arm/mediatek/mediatek,pericfg.txt | 30 ++++++++++++++++++++
15 .../bindings/arm/mediatek/mediatek,topckgen.txt | 23 +++++++++++++++
16 4 files changed, 106 insertions(+)
17 create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt
18 create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt
19 create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.txt
20 create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt
22 diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt
24 index 0000000..5af6d73
26 +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt
28 +Mediatek apmixedsys controller
29 +==============================
31 +The Mediatek apmixedsys controller provides the PLLs to the system.
35 +- compatible: Should be:
36 + - "mediatek,mt8135-apmixedsys"
37 + - "mediatek,mt8173-apmixedsys"
38 +- #clock-cells: Must be 1
40 +The apmixedsys controller uses the common clk binding from
41 +Documentation/devicetree/bindings/clock/clock-bindings.txt
42 +The available clocks are defined in dt-bindings/clock/mt*-clk.h.
46 +apmixedsys: apmixedsys@10209000 {
47 + compatible = "mediatek,mt8173-apmixedsys";
48 + reg = <0 0x10209000 0 0x1000>;
51 diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt
53 index 0000000..684da473
55 +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt
57 +Mediatek infracfg controller
58 +============================
60 +The Mediatek infracfg controller provides various clocks and reset
61 +outputs to the system.
65 +- compatible: Should be:
66 + - "mediatek,mt8135-infracfg", "syscon"
67 + - "mediatek,mt8173-infracfg", "syscon"
68 +- #clock-cells: Must be 1
69 +- #reset-cells: Must be 1
71 +The infracfg controller uses the common clk binding from
72 +Documentation/devicetree/bindings/clock/clock-bindings.txt
73 +The available clocks are defined in dt-bindings/clock/mt*-clk.h.
74 +Also it uses the common reset controller binding from
75 +Documentation/devicetree/bindings/reset/reset.txt.
76 +The available reset outputs are defined in
77 +dt-bindings/reset-controller/mt*-resets.h
81 +infracfg: infracfg@10001000 {
82 + compatible = "mediatek,mt8173-infracfg", "syscon";
83 + reg = <0 0x10001000 0 0x1000>;
87 diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.txt
89 index 0000000..fdb45c6
91 +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.txt
93 +Mediatek pericfg controller
94 +===========================
96 +The Mediatek pericfg controller provides various clocks and reset
97 +outputs to the system.
101 +- compatible: Should be:
102 + - "mediatek,mt8135-pericfg", "syscon"
103 + - "mediatek,mt8173-pericfg", "syscon"
104 +- #clock-cells: Must be 1
105 +- #reset-cells: Must be 1
107 +The pericfg controller uses the common clk binding from
108 +Documentation/devicetree/bindings/clock/clock-bindings.txt
109 +The available clocks are defined in dt-bindings/clock/mt*-clk.h.
110 +Also it uses the common reset controller binding from
111 +Documentation/devicetree/bindings/reset/reset.txt.
112 +The available reset outputs are defined in
113 +dt-bindings/reset-controller/mt*-resets.h
117 +pericfg: pericfg@10003000 {
118 + compatible = "mediatek,mt8173-pericfg", "syscon";
119 + reg = <0 0x10003000 0 0x1000>;
120 + #clock-cells = <1>;
121 + #reset-cells = <1>;
123 diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt
125 index 0000000..a425248
127 +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt
129 +Mediatek topckgen controller
130 +============================
132 +The Mediatek topckgen controller provides various clocks to the system.
134 +Required Properties:
136 +- compatible: Should be:
137 + - "mediatek,mt8135-topckgen"
138 + - "mediatek,mt8173-topckgen"
139 +- #clock-cells: Must be 1
141 +The topckgen controller uses the common clk binding from
142 +Documentation/devicetree/bindings/clock/clock-bindings.txt
143 +The available clocks are defined in dt-bindings/clock/mt*-clk.h.
147 +topckgen: topckgen@10000000 {
148 + compatible = "mediatek,mt8173-topckgen";
149 + reg = <0 0x10000000 0 0x1000>;
150 + #clock-cells = <1>;