1 From 014330a304100782a26bc7df02778c8c386b2857 Mon Sep 17 00:00:00 2001
2 From: Sascha Hauer <s.hauer@pengutronix.de>
3 Date: Wed, 13 May 2015 10:52:42 +0200
4 Subject: [PATCH 23/76] thermal: Add Mediatek thermal controller support
6 This adds support for the Mediatek thermal controller found on MT8173
8 The controller is a bit special. It does not have its own ADC, instead
9 it controls the on-SoC AUXADC via AHB bus accesses. For this reason
10 we need the physical address of the AUXADC. Also it controls a mux
11 using AHB bus accesses, so we need the APMIXEDSYS physical address aswell.
13 Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
15 drivers/thermal/Kconfig | 8 +
16 drivers/thermal/Makefile | 1 +
17 drivers/thermal/mtk_thermal.c | 728 +++++++++++++++++++++++++++++++++++++++++
18 3 files changed, 737 insertions(+)
19 create mode 100644 drivers/thermal/mtk_thermal.c
21 diff --git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig
22 index af40db0..3aa5500 100644
23 --- a/drivers/thermal/Kconfig
24 +++ b/drivers/thermal/Kconfig
25 @@ -285,6 +285,14 @@ config ACPI_THERMAL_REL
30 + tristate "Temperature sensor driver for mediatek SoCs"
31 + depends on ARCH_MEDIATEK || COMPILE_TEST
34 + Enable this option if you want to have support for thermal management
35 + controller present in Mediatek SoCs
37 menu "Texas Instruments thermal drivers"
38 source "drivers/thermal/ti-soc-thermal/Kconfig"
40 diff --git a/drivers/thermal/Makefile b/drivers/thermal/Makefile
41 index fa0dc48..51cfab7 100644
42 --- a/drivers/thermal/Makefile
43 +++ b/drivers/thermal/Makefile
44 @@ -39,3 +39,4 @@ obj-$(CONFIG_TI_SOC_THERMAL) += ti-soc-thermal/
45 obj-$(CONFIG_INT340X_THERMAL) += int340x_thermal/
46 obj-$(CONFIG_ST_THERMAL) += st/
47 obj-$(CONFIG_TEGRA_SOCTHERM) += tegra_soctherm.o
48 +obj-$(CONFIG_MTK_THERMAL) += mtk_thermal.o
49 diff --git a/drivers/thermal/mtk_thermal.c b/drivers/thermal/mtk_thermal.c
51 index 0000000..27aab12
53 +++ b/drivers/thermal/mtk_thermal.c
56 + * Copyright (c) 2014 MediaTek Inc.
57 + * Author: Hanyi.Wu <hanyi.wu@mediatek.com>
59 + * This program is free software; you can redistribute it and/or modify
60 + * it under the terms of the GNU General Public License version 2 as
61 + * published by the Free Software Foundation.
63 + * This program is distributed in the hope that it will be useful,
64 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
65 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
66 + * GNU General Public License for more details.
69 +#include <linux/kernel.h>
70 +#include <linux/module.h>
71 +#include <linux/dmi.h>
72 +#include <linux/thermal.h>
73 +#include <linux/platform_device.h>
74 +#include <linux/types.h>
75 +#include <linux/delay.h>
76 +#include <linux/slab.h>
77 +#include <linux/clk.h>
78 +#include <linux/time.h>
79 +#include <linux/of.h>
80 +#include <linux/of_irq.h>
81 +#include <linux/of_address.h>
82 +#include <linux/interrupt.h>
83 +#include <linux/reset.h>
85 +/* AUXADC Registers */
86 +#define AUXADC_CON0_V 0x000
87 +#define AUXADC_CON1_V 0x004
88 +#define AUXADC_CON1_SET_V 0x008
89 +#define AUXADC_CON1_CLR_V 0x00c
90 +#define AUXADC_CON2_V 0x010
91 +#define AUXADC_DATA(channel) (0x14 + (channel) * 4)
92 +#define AUXADC_MISC_V 0x094
94 +#define AUXADC_CON1_CHANNEL(x) (1 << (x))
96 +/* Thermal Controller Registers */
97 +#define TEMPMONCTL0 0x000
98 +#define TEMPMONCTL1 0x004
99 +#define TEMPMONCTL2 0x008
100 +#define TEMPMONINT 0x00c
101 +#define TEMPMONINTSTS 0x010
102 +#define TEMPMONIDET0 0x014
103 +#define TEMPMONIDET1 0x018
104 +#define TEMPMONIDET2 0x01c
105 +#define TEMPH2NTHRE 0x024
106 +#define TEMPHTHRE 0x028
107 +#define TEMPCTHRE 0x02c
108 +#define TEMPOFFSETH 0x030
109 +#define TEMPOFFSETL 0x034
110 +#define TEMPMSRCTL0 0x038
111 +#define TEMPMSRCTL1 0x03c
112 +#define TEMPAHBPOLL 0x040
113 +#define TEMPAHBTO 0x044
114 +#define TEMPADCPNP0 0x048
115 +#define TEMPADCPNP1 0x04c
116 +#define TEMPADCPNP2 0x050
117 +#define TEMPADCPNP3 0x0b4
119 +#define TEMPADCMUX 0x054
120 +#define TEMPADCEXT 0x058
121 +#define TEMPADCEXT1 0x05c
122 +#define TEMPADCEN 0x060
123 +#define TEMPPNPMUXADDR 0x064
124 +#define TEMPADCMUXADDR 0x068
125 +#define TEMPADCEXTADDR 0x06c
126 +#define TEMPADCEXT1ADDR 0x070
127 +#define TEMPADCENADDR 0x074
128 +#define TEMPADCVALIDADDR 0x078
129 +#define TEMPADCVOLTADDR 0x07c
130 +#define TEMPRDCTRL 0x080
131 +#define TEMPADCVALIDMASK 0x084
132 +#define TEMPADCVOLTAGESHIFT 0x088
133 +#define TEMPADCWRITECTRL 0x08c
134 +#define TEMPMSR0 0x090
135 +#define TEMPMSR1 0x094
136 +#define TEMPMSR2 0x098
137 +#define TEMPMSR3 0x0B8
139 +#define TEMPIMMD0 0x0a0
140 +#define TEMPIMMD1 0x0a4
141 +#define TEMPIMMD2 0x0a8
143 +#define TEMPPROTCTL 0x0c0
144 +#define TEMPPROTTA 0x0c4
145 +#define TEMPPROTTB 0x0c8
146 +#define TEMPPROTTC 0x0cc
148 +#define TEMPSPARE0 0x0f0
149 +#define TEMPSPARE1 0x0f4
150 +#define TEMPSPARE2 0x0f8
151 +#define TEMPSPARE3 0x0fc
153 +#define PTPCORESEL 0x400
154 +#define THERMINTST 0x404
155 +#define PTPODINTST 0x408
156 +#define THSTAGE0ST 0x40c
157 +#define THSTAGE1ST 0x410
158 +#define THSTAGE2ST 0x414
159 +#define THAHBST0 0x418
160 +#define THAHBST1 0x41c /* Only for DE debug */
161 +#define PTPSPARE0 0x420
162 +#define PTPSPARE1 0x424
163 +#define PTPSPARE2 0x428
164 +#define PTPSPARE3 0x42c
165 +#define THSLPEVEB 0x430
167 +#define TEMPMONINT_COLD(sp) ((1 << 0) << ((sp) * 5))
168 +#define TEMPMONINT_HOT(sp) ((1 << 1) << ((sp) * 5))
169 +#define TEMPMONINT_LOW_OFS(sp) ((1 << 2) << ((sp) * 5))
170 +#define TEMPMONINT_HIGH_OFS(sp) ((1 << 3) << ((sp) * 5))
171 +#define TEMPMONINT_HOT_TO_NORM(sp) ((1 << 4) << ((sp) * 5))
172 +#define TEMPMONINT_TIMEOUT (1 << 15)
173 +#define TEMPMONINT_IMMEDIATE_SENSE(sp) (1 << (16 + (sp)))
174 +#define TEMPMONINT_FILTER_SENSE(sp) (1 << (19 + (sp)))
176 +#define TEMPADCWRITECTRL_ADC_PNP_WRITE (1 << 0)
177 +#define TEMPADCWRITECTRL_ADC_MUX_WRITE (1 << 1)
178 +#define TEMPADCWRITECTRL_ADC_EXTRA_WRITE (1 << 2)
179 +#define TEMPADCWRITECTRL_ADC_EXTRA1_WRITE (1 << 3)
181 +#define TEMPADCVALIDMASK_VALID_HIGH (1 << 5)
182 +#define TEMPADCVALIDMASK_VALID_POS(bit) (bit)
184 +#define TEMPPROTCTL_AVERAGE (0 << 16)
185 +#define TEMPPROTCTL_MAXIMUM (1 << 16)
186 +#define TEMPPROTCTL_SELECTED (2 << 16)
188 +#define MT8173_THERMAL_ZONE_CA57 0
189 +#define MT8173_THERMAL_ZONE_CA53 1
190 +#define MT8173_THERMAL_ZONE_GPU 2
191 +#define MT8173_THERMAL_ZONE_CORE 3
193 +#define MT8173_TS1 0
194 +#define MT8173_TS2 1
195 +#define MT8173_TS3 2
196 +#define MT8173_TS4 3
197 +#define MT8173_TSABB 4
199 +/* AUXADC channel 11 is used for the temperature sensors */
200 +#define MT8173_TEMP_AUXADC_CHANNEL 11
202 +/* The total number of temperature sensors in the MT8173 */
203 +#define MT8173_NUM_SENSORS 5
205 +/* The number of banks in the MT8173 */
206 +#define MT8173_NUM_BANKS 4
208 +/* The number of sensing points per bank */
209 +#define MT8173_NUM_SENSING_POINTS 4
211 +#define THERMAL_NAME "mtk-thermal"
215 +struct mtk_thermal_bank {
216 + struct mtk_thermal *mt;
217 + struct thermal_zone_device *tz;
221 +struct mtk_thermal {
222 + struct device *dev;
223 + void __iomem *thermal_base;
224 + void __iomem *auxadc_base;
226 + u64 auxadc_phys_base;
227 + u64 apmixed_phys_base;
228 + struct reset_control *reset;
229 + struct clk *clk_peri_therm;
230 + struct clk *clk_auxadc;
232 + struct mtk_thermal_bank banks[MT8173_NUM_BANKS];
236 + /* Calibration values */
244 +struct mtk_thermal_bank_cfg {
245 + unsigned int enable_mask;
246 + unsigned int sensors[4];
249 +static int sensor_mux_values[MT8173_NUM_SENSORS] = { 0, 1, 2, 3, 16 };
252 + * The MT8173 thermal controller has four banks. Each bank can read up to
253 + * four temperature sensors simultaneously. The MT8173 has a total of 5
254 + * temperature sensors. We use each bank to measure a certain area of the
255 + * SoC. Since TS2 is located centrally in the SoC it is influenced by multiple
256 + * areas, hence is used in different banks.
258 +static struct mtk_thermal_bank_cfg bank_data[] = {
261 + .sensors = { MT8173_TS2, MT8173_TS3 },
264 + .sensors = { MT8173_TS2, MT8173_TS4 },
267 + .sensors = { MT8173_TS1, MT8173_TS2, MT8173_TSABB },
270 + .sensors = { MT8173_TS2 },
274 +static int tempmsr_ofs[MT8173_NUM_SENSING_POINTS] = {
275 + TEMPMSR0, TEMPMSR1, TEMPMSR2, TEMPMSR3
278 +static int tempadcpnp_ofs[MT8173_NUM_SENSING_POINTS] = {
279 + TEMPADCPNP0, TEMPADCPNP1, TEMPADCPNP2, TEMPADCPNP3
283 + * raw_to_mcelsius - convert a raw ADC value to mcelsius
284 + * @mt: The thermal controller
285 + * @raw: raw ADC value
287 + * This converts the raw ADC value to mcelsius using the SoC specific
288 + * calibration constants
290 +static int raw_to_mcelsius(struct mtk_thermal *mt, u32 raw)
292 + s32 format_1, format_2, format_3, format_4;
298 + gain = (10000 + mt->adc_ge);
300 + xtoomt = ((((mt->vts + 3350 - mt->adc_oe) * 10000) / 4096) * 10000) /
303 + format_1 = ((mt->degc_cali * 10) >> 1);
304 + format_2 = (raw - mt->adc_oe);
305 + format_3 = (((((format_2) * 10000) >> 12) * 10000) / gain) - xtoomt;
306 + format_3 = format_3 * 15 / 18;
307 + format_4 = ((format_3 * 100) / (165 + mt->o_slope));
308 + format_4 = format_4 - (format_4 << 1);
310 + return (format_1 + format_4) * 100;
314 + * mcelsius_to_raw - convert mcelsius to raw ADC value
315 + * @mt: The thermal controller
316 + * @temp: The temperature in mcelsius
318 + * This converts a temperature in mcelsius to a raw ADC value, needed to
319 + * calculate the trigger values for interrupt generation.
321 +static u32 mcelsius_to_raw(struct mtk_thermal *mt, int temp)
323 + s32 format_1, format_2, format_3, format_4;
327 + gain = (10000 + mt->adc_ge);
329 + xtoomt = ((((mt->vts + 3350 - mt->adc_oe) * 10000) / 4096) * 10000) /
332 + format_1 = temp - (mt->degc_cali * 1000 / 2);
333 + format_2 = format_1 * (165 + mt->o_slope) * 18 / 15;
334 + format_2 = format_2 - 2 * format_2;
335 + format_3 = format_2 / 1000 + xtoomt * 10;
336 + format_4 = (format_3 * 4096 / 10000 * gain) / 100000 + mt->adc_oe;
342 + * mtk_thermal_get_bank - get bank
345 + * The bank registers are banked, we have to select a bank in the
346 + * PTPCORESEL register to access it.
348 +static void mtk_thermal_get_bank(struct mtk_thermal_bank *bank)
350 + struct mtk_thermal *mt = bank->mt;
353 + mutex_lock(&mt->lock);
355 + val = readl(mt->thermal_base + PTPCORESEL);
358 + writel(val, mt->thermal_base + PTPCORESEL);
362 + * mtk_thermal_put_bank - release bank
365 + * release a bank previously taken with mtk_thermal_get_bank,
367 +static void mtk_thermal_put_bank(struct mtk_thermal_bank *bank)
369 + struct mtk_thermal *mt = bank->mt;
371 + mutex_unlock(&mt->lock);
375 + * mtk_thermal_bank_temperature - get the temperature of a bank
378 + * The temperature of a bank is considered the maximum temperature of
379 + * the sensors associated to the bank.
381 +static int mtk_thermal_bank_temperature(struct mtk_thermal_bank *bank)
383 + struct mtk_thermal *mt = bank->mt;
387 + temp = max = -INT_MAX;
389 + for (i = 0; i < 4; i++) {
392 + if (!(bank_data[bank->id].enable_mask & (1 << i)))
395 + raw = readl(mt->thermal_base + tempmsr_ofs[i]);
397 + sensno = bank_data[bank->id].sensors[i];
398 + temp = raw_to_mcelsius(mt, raw);
407 +static void mtk_thermal_irq_bank(struct mtk_thermal_bank *bank)
409 + struct mtk_thermal *mt = bank->mt;
412 + bool update = false;
414 + mtk_thermal_get_bank(bank);
416 + irqstat = readl(mt->thermal_base + TEMPMONINTSTS);
418 + mtk_thermal_put_bank(bank);
420 + for (sp = 0; sp < 3; sp++) {
421 + if (irqstat & TEMPMONINT_LOW_OFS(sp)) {
423 + dev_vdbg(mt->dev, "bank %d sensor %d low offset interrupt\n",
427 + if (irqstat & TEMPMONINT_HIGH_OFS(sp)) {
429 + dev_vdbg(mt->dev, "bank %d sensor %d high offset interrupt\n",
435 + thermal_zone_device_update(bank->tz);
438 +static irqreturn_t mtk_thermal_irq(int irq, void *dev_id)
440 + struct mtk_thermal *mt = dev_id;
444 + irqstat = readl(mt->thermal_base + THERMINTST);
446 + dev_vdbg(mt->dev, "thermal_interrupt_handler : THERMINTST = 0x%x\n",
449 + for (i = 0; i < MT8173_NUM_BANKS; i++) {
450 + if (!(irqstat & (1 << i)))
451 + mtk_thermal_irq_bank(&mt->banks[i]);
454 + return IRQ_HANDLED;
457 +static int mtk_read_temp(void *data, int *temp)
459 + struct mtk_thermal_bank *bank = data;
461 + mtk_thermal_get_bank(bank);
463 + *temp = mtk_thermal_bank_temperature(bank);
465 + mtk_thermal_put_bank(bank);
470 +static int mtk_set_trips(void *data, int low, int high)
472 + struct mtk_thermal_bank *bank = data;
473 + struct mtk_thermal *mt = bank->mt;
475 + u32 val, enable_mask;
476 + u32 raw_low, raw_high;
478 + raw_low = mcelsius_to_raw(mt, low);
479 + raw_high = mcelsius_to_raw(mt, high);
481 + mtk_thermal_get_bank(bank);
483 + writel(0x0, mt->thermal_base + TEMPMONINT);
485 + writel(TEMPPROTCTL_SELECTED, mt->thermal_base + TEMPPROTCTL);
487 + writel(raw_low, mt->thermal_base + TEMPOFFSETL);
488 + writel(raw_high, mt->thermal_base + TEMPOFFSETH);
490 + enable_mask = readl(mt->thermal_base + TEMPMONCTL0);
493 + for (i = 0; i < MT8173_NUM_SENSING_POINTS; i++)
494 + if (enable_mask & (1 << i))
495 + val |= TEMPMONINT_LOW_OFS(i) | TEMPMONINT_HIGH_OFS(i);
497 + writel(val, mt->thermal_base + TEMPMONINT);
499 + mtk_thermal_put_bank(bank);
501 + dev_dbg(mt->dev, "new boundaries: %d (0x%04x) < x < %d (0x%04x)\n",
502 + low, mcelsius_to_raw(mt, low),
503 + high, mcelsius_to_raw(mt, high));
508 +static const struct thermal_zone_of_device_ops mtk_thermal_ops = {
509 + .get_temp = mtk_read_temp,
510 + .set_trips = mtk_set_trips,
513 +static void mtk_thermal_init_bank(struct mtk_thermal_bank *bank)
515 + struct mtk_thermal *mt = bank->mt;
516 + struct mtk_thermal_bank_cfg *cfg = &bank_data[bank->id];
519 + mtk_thermal_get_bank(bank);
521 + /* bus clock 66M counting unit is 12 * 15.15ns * 256 = 46.540us */
522 + writel(0x0000000c, mt->thermal_base + TEMPMONCTL1);
525 + * filt interval is 1 * 46.540us = 46.54us,
526 + * sen interval is 429 * 46.540us = 19.96ms
528 + writel(0x000101ad, mt->thermal_base + TEMPMONCTL2);
530 + /* poll is set to 10u */
531 + writel(0x00000300, mt->thermal_base + TEMPAHBPOLL);
533 + /* temperature sampling control, 1 sample */
534 + writel(0x00000000, mt->thermal_base + TEMPMSRCTL0);
536 + /* exceed this polling time, IRQ would be inserted */
537 + writel(0xffffffff, mt->thermal_base + TEMPAHBTO);
539 + /* number of interrupts per event, 1 is enough */
540 + writel(0x0, mt->thermal_base + TEMPMONIDET0);
541 + writel(0x0, mt->thermal_base + TEMPMONIDET1);
544 + * The MT8173 thermal controller does not have its own ADC. Instead it
545 + * uses AHB bus accesses to control the AUXADC. To do this the thermal
546 + * controller has to be programmed with the physical addresses of the
547 + * AUXADC registers and with the various bit positions in the AUXADC.
548 + * Also the thermal controller controls a mux in the APMIXEDSYS register
553 + * this value will be stored to TEMPPNPMUXADDR (TEMPSPARE0)
554 + * automatically by hw
556 + writel(1 << MT8173_TEMP_AUXADC_CHANNEL, mt->thermal_base + TEMPADCMUX);
558 + /* AHB address for auxadc mux selection */
559 + writel(mt->auxadc_phys_base + 0x00c,
560 + mt->thermal_base + TEMPADCMUXADDR);
562 + /* AHB address for pnp sensor mux selection */
563 + writel(mt->apmixed_phys_base + 0x0604,
564 + mt->thermal_base + TEMPPNPMUXADDR);
566 + /* AHB value for auxadc enable */
567 + writel(1 << MT8173_TEMP_AUXADC_CHANNEL, mt->thermal_base + TEMPADCEN);
569 + /* AHB address for auxadc enable (channel 0 immediate mode selected) */
570 + writel(mt->auxadc_phys_base + AUXADC_CON1_SET_V,
571 + mt->thermal_base + TEMPADCENADDR);
573 + /* AHB address for auxadc valid bit */
574 + writel(mt->auxadc_phys_base + AUXADC_DATA(MT8173_TEMP_AUXADC_CHANNEL),
575 + mt->thermal_base + TEMPADCVALIDADDR);
577 + /* AHB address for auxadc voltage output */
578 + writel(mt->auxadc_phys_base + AUXADC_DATA(MT8173_TEMP_AUXADC_CHANNEL),
579 + mt->thermal_base + TEMPADCVOLTADDR);
581 + /* read valid & voltage are at the same register */
582 + writel(0x0, mt->thermal_base + TEMPRDCTRL);
584 + /* indicate where the valid bit is */
585 + writel(TEMPADCVALIDMASK_VALID_HIGH | TEMPADCVALIDMASK_VALID_POS(12),
586 + mt->thermal_base + TEMPADCVALIDMASK);
589 + writel(0x0, mt->thermal_base + TEMPADCVOLTAGESHIFT);
591 + /* enable auxadc mux write transaction */
592 + writel(TEMPADCWRITECTRL_ADC_MUX_WRITE,
593 + mt->thermal_base + TEMPADCWRITECTRL);
595 + for (i = 0; i < MT8173_NUM_SENSING_POINTS; i++)
596 + writel(sensor_mux_values[cfg->sensors[i]],
597 + mt->thermal_base + tempadcpnp_ofs[i]);
599 + writel(cfg->enable_mask, mt->thermal_base + TEMPMONCTL0);
601 + writel(TEMPADCWRITECTRL_ADC_PNP_WRITE | TEMPADCWRITECTRL_ADC_MUX_WRITE,
602 + mt->thermal_base + TEMPADCWRITECTRL);
604 + mtk_thermal_put_bank(bank);
607 +static u64 of_get_phys_base(struct device_node *np)
610 + const __be32 *regaddr_p;
612 + regaddr_p = of_get_address(np, 0, &size64, NULL);
614 + return OF_BAD_ADDR;
616 + return of_translate_address(np, regaddr_p);
619 +static int mtk_thermal_probe(struct platform_device *pdev)
622 + struct device_node *auxadc, *apmixedsys, *np = pdev->dev.of_node;
624 + struct mtk_thermal *mt;
625 + struct resource *res;
627 + mt = devm_kzalloc(&pdev->dev, sizeof(*mt), GFP_KERNEL);
631 + mt->clk_peri_therm = devm_clk_get(&pdev->dev, "therm");
632 + if (IS_ERR(mt->clk_peri_therm))
633 + return PTR_ERR(mt->clk_peri_therm);
635 + mt->clk_auxadc = devm_clk_get(&pdev->dev, "auxadc");
636 + if (IS_ERR(mt->clk_auxadc))
637 + return PTR_ERR(mt->clk_auxadc);
639 + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
640 + mt->thermal_base = devm_ioremap_resource(&pdev->dev, res);
641 + if (IS_ERR(mt->thermal_base))
642 + return PTR_ERR(mt->thermal_base);
644 + mt->reset = devm_reset_control_get(&pdev->dev, "therm");
645 + if (IS_ERR(mt->reset)) {
646 + ret = PTR_ERR(mt->reset);
647 + dev_err(&pdev->dev, "cannot get reset: %d\n", ret);
651 + mutex_init(&mt->lock);
653 + mt->dev = &pdev->dev;
655 + auxadc = of_parse_phandle(np, "auxadc", 0);
657 + dev_err(&pdev->dev, "missing auxadc node\n");
661 + mt->auxadc_phys_base = of_get_phys_base(auxadc);
662 + if (mt->auxadc_phys_base == OF_BAD_ADDR) {
663 + dev_err(&pdev->dev, "Can't get auxadc phys address\n");
667 + apmixedsys = of_parse_phandle(np, "apmixedsys", 0);
669 + dev_err(&pdev->dev, "missing apmixedsys node\n");
673 + mt->apmixed_phys_base = of_get_phys_base(apmixedsys);
674 + if (mt->apmixed_phys_base == OF_BAD_ADDR) {
675 + dev_err(&pdev->dev, "Can't get auxadc phys address\n");
679 + irq = platform_get_irq(pdev, 0);
681 + dev_err(&pdev->dev, "Can't find irq\n");
685 + ret = devm_request_threaded_irq(&pdev->dev, irq, NULL, mtk_thermal_irq,
686 + IRQF_ONESHOT, THERMAL_NAME, mt);
688 + dev_err(&pdev->dev, "Can't request irq %d: %d\n", irq, ret);
692 + ret = clk_prepare_enable(mt->clk_auxadc);
694 + dev_err(&pdev->dev, "Can't enable auxadc clk: %d\n", ret);
698 + reset_control_reset(mt->reset);
700 + ret = clk_prepare_enable(mt->clk_peri_therm);
702 + dev_err(&pdev->dev, "Can't enable peri clk: %d\n", ret);
703 + goto err_enable_clk;
707 + * These calibration values should finally be provided by the
708 + * firmware or fuses. For now use default values.
710 + mt->adc_ge = ((512 - 512) * 10000) / 4096;
711 + mt->adc_oe = 512 - 512;
712 + mt->degc_cali = 40;
716 + for (i = 0; i < MT8173_NUM_BANKS; i++) {
717 + struct mtk_thermal_bank *bank = &mt->banks[i];
721 + mtk_thermal_init_bank(&mt->banks[i]);
724 + platform_set_drvdata(pdev, mt);
727 + * This is needed after initialising the banks because otherwise
728 + * the first temperature read contains bogus high temperatures which
729 + * immediately cause a system shutdown.
733 + for (i = 0; i < MT8173_NUM_BANKS; i++) {
734 + struct mtk_thermal_bank *bank = &mt->banks[i];
736 + bank->tz = thermal_zone_of_sensor_register(&pdev->dev, i, bank,
743 + clk_disable_unprepare(mt->clk_peri_therm);
748 +static int mtk_thermal_remove(struct platform_device *pdev)
750 + struct mtk_thermal *mt = platform_get_drvdata(pdev);
753 + for (i = 0; i < MT8173_NUM_BANKS; i++) {
754 + struct mtk_thermal_bank *bank = &mt->banks[i];
757 + thermal_zone_of_sensor_unregister(&pdev->dev, bank->tz);
760 + clk_disable_unprepare(mt->clk_peri_therm);
761 + clk_disable_unprepare(mt->clk_auxadc);
766 +static const struct of_device_id mtk_thermal_of_match[] = {
768 + .compatible = "mediatek,mt8173-thermal",
773 +static struct platform_driver mtk_thermal_driver = {
774 + .probe = mtk_thermal_probe,
775 + .remove = mtk_thermal_remove,
777 + .name = THERMAL_NAME,
778 + .of_match_table = mtk_thermal_of_match,
782 +module_platform_driver(mtk_thermal_driver);