1 From 047222cfefe97ef8706f03117bc8deada4cb4ddd Mon Sep 17 00:00:00 2001
2 From: Leilk Liu <leilk.liu@mediatek.com>
3 Date: Fri, 8 May 2015 16:55:42 +0800
4 Subject: [PATCH 26/76] spi: mediatek: Add spi bus for Mediatek MT8173
6 This patch adds basic spi bus for MT8173.
8 Signed-off-by: Leilk Liu <leilk.liu@mediatek.com>
10 drivers/spi/Kconfig | 10 +
11 drivers/spi/Makefile | 1 +
12 drivers/spi/spi-mt65xx.c | 622 ++++++++++++++++++++++++++++++++++++++++++++++
13 3 files changed, 633 insertions(+)
14 create mode 100644 drivers/spi/spi-mt65xx.c
16 diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
17 index 72b0590..53dbea3 100644
18 --- a/drivers/spi/Kconfig
19 +++ b/drivers/spi/Kconfig
20 @@ -325,6 +325,16 @@ config SPI_MESON_SPIFC
21 This enables master mode support for the SPIFC (SPI flash
22 controller) available in Amlogic Meson SoCs.
25 + tristate "MediaTek SPI controller"
26 + depends on ARCH_MEDIATEK || COMPILE_TEST
29 + This selects the MediaTek(R) SPI bus driver.
30 + If you want to use MediaTek(R) SPI interface,
31 + say Y or M here.If you are not sure, say N.
32 + SPI drivers for Mediatek mt65XX series ARM SoCs.
35 tristate "OpenCores tiny SPI"
37 diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
38 index d8cbf65..ab332ef 100644
39 --- a/drivers/spi/Makefile
40 +++ b/drivers/spi/Makefile
41 @@ -48,6 +48,7 @@ obj-$(CONFIG_SPI_MESON_SPIFC) += spi-meson-spifc.o
42 obj-$(CONFIG_SPI_MPC512x_PSC) += spi-mpc512x-psc.o
43 obj-$(CONFIG_SPI_MPC52xx_PSC) += spi-mpc52xx-psc.o
44 obj-$(CONFIG_SPI_MPC52xx) += spi-mpc52xx.o
45 +obj-$(CONFIG_SPI_MT65XX) += spi-mt65xx.o
46 obj-$(CONFIG_SPI_MXS) += spi-mxs.o
47 obj-$(CONFIG_SPI_NUC900) += spi-nuc900.o
48 obj-$(CONFIG_SPI_OC_TINY) += spi-oc-tiny.o
49 diff --git a/drivers/spi/spi-mt65xx.c b/drivers/spi/spi-mt65xx.c
51 index 0000000..92c119d
53 +++ b/drivers/spi/spi-mt65xx.c
56 + * Copyright (c) 2015 MediaTek Inc.
57 + * Author: Leilk Liu <leilk.liu@mediatek.com>
59 + * This program is free software; you can redistribute it and/or modify
60 + * it under the terms of the GNU General Public License version 2 as
61 + * published by the Free Software Foundation.
63 + * This program is distributed in the hope that it will be useful,
64 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
65 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
66 + * GNU General Public License for more details.
69 +#include <linux/init.h>
70 +#include <linux/module.h>
71 +#include <linux/device.h>
72 +#include <linux/ioport.h>
73 +#include <linux/errno.h>
74 +#include <linux/spi/spi.h>
75 +#include <linux/workqueue.h>
76 +#include <linux/dma-mapping.h>
77 +#include <linux/platform_device.h>
78 +#include <linux/interrupt.h>
79 +#include <linux/irqreturn.h>
80 +#include <linux/types.h>
81 +#include <linux/delay.h>
82 +#include <linux/clk.h>
83 +#include <linux/err.h>
84 +#include <linux/io.h>
85 +#include <linux/sched.h>
86 +#include <linux/of.h>
87 +#include <linux/of_irq.h>
88 +#include <linux/of_address.h>
89 +#include <linux/kernel.h>
90 +#include <linux/spi/spi_bitbang.h>
91 +#include <linux/gpio.h>
92 +#include <linux/module.h>
93 +#include <linux/of_gpio.h>
95 +#define SPI_CFG0_REG 0x0000
96 +#define SPI_CFG1_REG 0x0004
97 +#define SPI_TX_SRC_REG 0x0008
98 +#define SPI_RX_DST_REG 0x000c
99 +#define SPI_CMD_REG 0x0018
100 +#define SPI_STATUS0_REG 0x001c
101 +#define SPI_PAD_SEL_REG 0x0024
103 +#define SPI_CFG0_SCK_HIGH_OFFSET 0
104 +#define SPI_CFG0_SCK_LOW_OFFSET 8
105 +#define SPI_CFG0_CS_HOLD_OFFSET 16
106 +#define SPI_CFG0_CS_SETUP_OFFSET 24
108 +#define SPI_CFG0_SCK_HIGH_MASK 0xff
109 +#define SPI_CFG0_SCK_LOW_MASK 0xff00
110 +#define SPI_CFG0_CS_HOLD_MASK 0xff0000
111 +#define SPI_CFG0_CS_SETUP_MASK 0xff000000
113 +#define SPI_CFG1_CS_IDLE_OFFSET 0
114 +#define SPI_CFG1_PACKET_LOOP_OFFSET 8
115 +#define SPI_CFG1_PACKET_LENGTH_OFFSET 16
116 +#define SPI_CFG1_GET_TICK_DLY_OFFSET 30
118 +#define SPI_CFG1_CS_IDLE_MASK 0xff
119 +#define SPI_CFG1_PACKET_LOOP_MASK 0xff00
120 +#define SPI_CFG1_PACKET_LENGTH_MASK 0x3ff0000
121 +#define SPI_CFG1_GET_TICK_DLY_MASK 0xc0000000
123 +#define SPI_CMD_ACT_OFFSET 0
124 +#define SPI_CMD_RESUME_OFFSET 1
125 +#define SPI_CMD_RST_OFFSET 2
126 +#define SPI_CMD_PAUSE_EN_OFFSET 4
127 +#define SPI_CMD_DEASSERT_OFFSET 5
128 +#define SPI_CMD_CPHA_OFFSET 8
129 +#define SPI_CMD_CPOL_OFFSET 9
130 +#define SPI_CMD_RX_DMA_OFFSET 10
131 +#define SPI_CMD_TX_DMA_OFFSET 11
132 +#define SPI_CMD_TXMSBF_OFFSET 12
133 +#define SPI_CMD_RXMSBF_OFFSET 13
134 +#define SPI_CMD_RX_ENDIAN_OFFSET 14
135 +#define SPI_CMD_TX_ENDIAN_OFFSET 15
136 +#define SPI_CMD_FINISH_IE_OFFSET 16
137 +#define SPI_CMD_PAUSE_IE_OFFSET 17
139 +#define SPI_CMD_RESUME_MASK 0x2
140 +#define SPI_CMD_RST_MASK 0x4
141 +#define SPI_CMD_PAUSE_EN_MASK 0x10
142 +#define SPI_CMD_DEASSERT_MASK 0x20
143 +#define SPI_CMD_CPHA_MASK 0x100
144 +#define SPI_CMD_CPOL_MASK 0x200
145 +#define SPI_CMD_RX_DMA_MASK 0x400
146 +#define SPI_CMD_TX_DMA_MASK 0x800
147 +#define SPI_CMD_TXMSBF_MASK 0x1000
148 +#define SPI_CMD_RXMSBF_MASK 0x2000
149 +#define SPI_CMD_RX_ENDIAN_MASK 0x4000
150 +#define SPI_CMD_TX_ENDIAN_MASK 0x8000
151 +#define SPI_CMD_FINISH_IE_MASK 0x10000
153 +#define COMPAT_MT6589 (0x1 << 0)
154 +#define COMPAT_MT8173 (0x1 << 1)
156 +#define MT8173_MAX_PAD_SEL 3
159 +#define INPROGRESS 1
162 +#define PACKET_SIZE 1024
164 +struct mtk_chip_config {
180 +struct mtk_spi_ddata {
181 + struct spi_bitbang bitbang;
182 + void __iomem *base;
185 + u32 platform_compat;
191 + u32 tx_len, rx_len;
192 + struct completion done;
196 + * A piece of default chip info unless the platform
199 +static const struct mtk_chip_config mtk_default_chip_info = {
215 +static const struct of_device_id mtk_spi_of_match[] = {
216 + { .compatible = "mediatek,mt6589-spi", .data = (void *)COMPAT_MT6589},
217 + { .compatible = "mediatek,mt8173-spi", .data = (void *)COMPAT_MT8173},
220 +MODULE_DEVICE_TABLE(of, mtk_spi_of_match);
222 +static void mtk_spi_reset(struct mtk_spi_ddata *mdata)
226 + /*set the software reset bit in SPI_CMD_REG.*/
227 + reg_val = readl(mdata->base + SPI_CMD_REG);
228 + reg_val &= ~SPI_CMD_RST_MASK;
229 + reg_val |= 1 << SPI_CMD_RST_OFFSET;
230 + writel(reg_val, mdata->base + SPI_CMD_REG);
231 + reg_val = readl(mdata->base + SPI_CMD_REG);
232 + reg_val &= ~SPI_CMD_RST_MASK;
233 + writel(reg_val, mdata->base + SPI_CMD_REG);
236 +static void mtk_set_pause_bit(struct mtk_spi_ddata *mdata)
240 + reg_val = readl(mdata->base + SPI_CMD_REG);
241 + reg_val |= 1 << SPI_CMD_PAUSE_EN_OFFSET;
242 + reg_val |= 1 << SPI_CMD_PAUSE_IE_OFFSET;
243 + writel(reg_val, mdata->base + SPI_CMD_REG);
246 +static void mtk_clear_pause_bit(struct mtk_spi_ddata *mdata)
250 + reg_val = readl(mdata->base + SPI_CMD_REG);
251 + reg_val &= ~SPI_CMD_PAUSE_EN_MASK;
252 + writel(reg_val, mdata->base + SPI_CMD_REG);
255 +static int mtk_spi_config(struct mtk_spi_ddata *mdata,
256 + struct mtk_chip_config *chip_config)
260 + /* set the timing */
261 + reg_val = readl(mdata->base + SPI_CFG0_REG);
262 + reg_val &= ~(SPI_CFG0_SCK_HIGH_MASK | SPI_CFG0_SCK_LOW_MASK);
263 + reg_val &= ~(SPI_CFG0_CS_HOLD_MASK | SPI_CFG0_CS_SETUP_MASK);
264 + reg_val |= ((chip_config->high_time - 1) << SPI_CFG0_SCK_HIGH_OFFSET);
265 + reg_val |= ((chip_config->low_time - 1) << SPI_CFG0_SCK_LOW_OFFSET);
266 + reg_val |= ((chip_config->holdtime - 1) << SPI_CFG0_CS_HOLD_OFFSET);
267 + reg_val |= ((chip_config->setuptime - 1) << SPI_CFG0_CS_SETUP_OFFSET);
268 + writel(reg_val, mdata->base + SPI_CFG0_REG);
270 + reg_val = readl(mdata->base + SPI_CFG1_REG);
271 + reg_val &= ~SPI_CFG1_CS_IDLE_MASK;
272 + reg_val |= ((chip_config->cs_idletime - 1) << SPI_CFG1_CS_IDLE_OFFSET);
273 + reg_val &= ~SPI_CFG1_GET_TICK_DLY_MASK;
274 + reg_val |= ((chip_config->tckdly) << SPI_CFG1_GET_TICK_DLY_OFFSET);
275 + writel(reg_val, mdata->base + SPI_CFG1_REG);
277 + /* set the mlsbx and mlsbtx */
278 + reg_val = readl(mdata->base + SPI_CMD_REG);
279 + reg_val &= ~(SPI_CMD_TX_ENDIAN_MASK | SPI_CMD_RX_ENDIAN_MASK);
280 + reg_val &= ~(SPI_CMD_TXMSBF_MASK | SPI_CMD_RXMSBF_MASK);
281 + reg_val |= (chip_config->tx_mlsb << SPI_CMD_TXMSBF_OFFSET);
282 + reg_val |= (chip_config->rx_mlsb << SPI_CMD_RXMSBF_OFFSET);
283 + reg_val |= (chip_config->tx_endian << SPI_CMD_TX_ENDIAN_OFFSET);
284 + reg_val |= (chip_config->rx_endian << SPI_CMD_RX_ENDIAN_OFFSET);
285 + writel(reg_val, mdata->base + SPI_CMD_REG);
287 + /* set finish and pause interrupt always enable */
288 + reg_val = readl(mdata->base + SPI_CMD_REG);
289 + reg_val &= ~SPI_CMD_FINISH_IE_MASK;
290 + reg_val |= (chip_config->finish_intr << SPI_CMD_FINISH_IE_OFFSET);
291 + writel(reg_val, mdata->base + SPI_CMD_REG);
293 + reg_val = readl(mdata->base + SPI_CMD_REG);
294 + reg_val |= 1 << SPI_CMD_TX_DMA_OFFSET;
295 + reg_val |= 1 << SPI_CMD_RX_DMA_OFFSET;
296 + writel(reg_val, mdata->base + SPI_CMD_REG);
298 + /* set deassert mode */
299 + reg_val = readl(mdata->base + SPI_CMD_REG);
300 + reg_val &= ~SPI_CMD_DEASSERT_MASK;
301 + reg_val |= (chip_config->deassert << SPI_CMD_DEASSERT_OFFSET);
302 + writel(reg_val, mdata->base + SPI_CMD_REG);
305 + if (mdata->platform_compat & COMPAT_MT8173)
306 + writel(mdata->pad_sel, mdata->base + SPI_PAD_SEL_REG);
311 +static int mtk_spi_setup_transfer(struct spi_device *spi,
312 + struct spi_transfer *t)
315 + struct spi_master *master = spi->master;
316 + struct mtk_spi_ddata *mdata = spi_master_get_devdata(master);
317 + struct spi_message *m = master->cur_msg;
318 + struct mtk_chip_config *chip_config;
320 + u8 cpha = spi->mode & SPI_CPHA ? 1 : 0;
321 + u8 cpol = spi->mode & SPI_CPOL ? 1 : 0;
323 + reg_val = readl(mdata->base + SPI_CMD_REG);
324 + reg_val &= ~(SPI_CMD_CPHA_MASK | SPI_CMD_CPOL_MASK);
325 + reg_val |= (cpha << SPI_CMD_CPHA_OFFSET);
326 + reg_val |= (cpol << SPI_CMD_CPOL_OFFSET);
327 + writel(reg_val, mdata->base + SPI_CMD_REG);
329 + if (t->cs_change) {
330 + if (!(list_is_last(&t->transfer_list, &m->transfers)))
331 + mdata->state = IDLE;
333 + mdata->state = IDLE;
334 + mtk_spi_reset(mdata);
337 + chip_config = (struct mtk_chip_config *)spi->controller_data;
338 + if (!chip_config) {
339 + chip_config = (void *)&mtk_default_chip_info;
340 + spi->controller_data = chip_config;
341 + mdata->state = IDLE;
344 + mtk_spi_config(mdata, chip_config);
349 +static void mtk_spi_chipselect(struct spi_device *spi, int is_on)
351 + struct mtk_spi_ddata *mdata = spi_master_get_devdata(spi->master);
354 + case BITBANG_CS_ACTIVE:
355 + mtk_set_pause_bit(mdata);
357 + case BITBANG_CS_INACTIVE:
358 + mtk_clear_pause_bit(mdata);
363 +static void mtk_spi_start_transfer(struct mtk_spi_ddata *mdata)
367 + reg_val = readl(mdata->base + SPI_CMD_REG);
368 + reg_val |= 1 << SPI_CMD_ACT_OFFSET;
369 + writel(reg_val, mdata->base + SPI_CMD_REG);
372 +static void mtk_spi_resume_transfer(struct mtk_spi_ddata *mdata)
376 + reg_val = readl(mdata->base + SPI_CMD_REG);
377 + reg_val &= ~SPI_CMD_RESUME_MASK;
378 + reg_val |= 1 << SPI_CMD_RESUME_OFFSET;
379 + writel(reg_val, mdata->base + SPI_CMD_REG);
382 +static int mtk_spi_setup_packet(struct mtk_spi_ddata *mdata,
383 + struct spi_transfer *xfer)
385 + struct device *dev = &mdata->bitbang.master->dev;
386 + u32 packet_size, packet_loop, reg_val;
388 + packet_size = min_t(unsigned, xfer->len, PACKET_SIZE);
390 + /* mtk hw has the restriction that xfer len must be a multiple of 1024,
391 + * when it is greater than 1024bytes.
393 + if (xfer->len % packet_size) {
394 + dev_err(dev, "ERROR!The lens must be a multiple of %d, your len %d\n",
395 + PACKET_SIZE, xfer->len);
399 + packet_loop = xfer->len / packet_size;
401 + reg_val = readl(mdata->base + SPI_CFG1_REG);
402 + reg_val &= ~(SPI_CFG1_PACKET_LENGTH_MASK + SPI_CFG1_PACKET_LOOP_MASK);
403 + reg_val |= (packet_size - 1) << SPI_CFG1_PACKET_LENGTH_OFFSET;
404 + reg_val |= (packet_loop - 1) << SPI_CFG1_PACKET_LOOP_OFFSET;
405 + writel(reg_val, mdata->base + SPI_CFG1_REG);
410 +static int mtk_spi_txrx_bufs(struct spi_device *spi, struct spi_transfer *xfer)
412 + struct spi_master *master = spi->master;
413 + struct mtk_spi_ddata *mdata = spi_master_get_devdata(master);
414 + struct device *dev = &mdata->bitbang.master->dev;
417 + /* mtk spi hw tx/rx have 4bytes aligned restriction,
418 + * so kmalloc tx/rx buffer to workaround here.
420 + mdata->tx_buf = NULL;
421 + mdata->rx_buf = NULL;
422 + if (xfer->tx_buf) {
423 + mdata->tx_buf = kmalloc(xfer->len, GFP_KERNEL);
424 + if (!mdata->tx_buf) {
425 + dev_err(dev, "malloc tx_buf failed.\n");
429 + memcpy((void *)mdata->tx_buf, xfer->tx_buf, xfer->len);
431 + if (xfer->rx_buf) {
432 + mdata->rx_buf = kmalloc(xfer->len, GFP_KERNEL);
433 + if (!mdata->rx_buf) {
434 + dev_err(dev, "malloc rx_buf failed.\n");
440 + reinit_completion(&mdata->done);
442 + xfer->tx_dma = DMA_ERROR_CODE;
443 + xfer->rx_dma = DMA_ERROR_CODE;
444 + if (xfer->tx_buf) {
445 + xfer->tx_dma = dma_map_single(dev, (void *)mdata->tx_buf,
446 + xfer->len, DMA_TO_DEVICE);
447 + if (dma_mapping_error(dev, xfer->tx_dma)) {
448 + dev_err(dev, "dma mapping tx_buf error.\n");
453 + if (xfer->rx_buf) {
454 + xfer->rx_dma = dma_map_single(dev, mdata->rx_buf,
455 + xfer->len, DMA_FROM_DEVICE);
456 + if (dma_mapping_error(dev, xfer->rx_dma)) {
458 + dma_unmap_single(dev, xfer->tx_dma,
459 + xfer->len, DMA_TO_DEVICE);
460 + dev_err(dev, "dma mapping rx_buf error.\n");
466 + ret = mtk_spi_setup_packet(mdata, xfer);
470 + /* Here is mt8173 HW issue: RX must enable TX, then TX transfer
471 + * dummy data; TX don't need to enable RX. so enable TX dma for
472 + * RX to workaround.
474 + cmd = readl(mdata->base + SPI_CMD_REG);
475 + if (xfer->tx_buf || (mdata->platform_compat & COMPAT_MT8173))
476 + cmd |= 1 << SPI_CMD_TX_DMA_OFFSET;
478 + cmd |= 1 << SPI_CMD_RX_DMA_OFFSET;
479 + writel(cmd, mdata->base + SPI_CMD_REG);
481 + /* set up the DMA bus address */
482 + if (xfer->tx_dma != DMA_ERROR_CODE)
483 + writel(cpu_to_le32(xfer->tx_dma), mdata->base + SPI_TX_SRC_REG);
484 + if (xfer->rx_dma != DMA_ERROR_CODE)
485 + writel(cpu_to_le32(xfer->rx_dma), mdata->base + SPI_RX_DST_REG);
487 + if (mdata->state == IDLE)
488 + mtk_spi_start_transfer(mdata);
489 + else if (mdata->state == PAUSED)
490 + mtk_spi_resume_transfer(mdata);
492 + mdata->state = INPROGRESS;
494 + wait_for_completion(&mdata->done);
496 + if (xfer->tx_dma != DMA_ERROR_CODE) {
497 + dma_unmap_single(dev, xfer->tx_dma, xfer->len, DMA_TO_DEVICE);
498 + xfer->tx_dma = DMA_ERROR_CODE;
500 + if (xfer->rx_dma != DMA_ERROR_CODE) {
501 + dma_unmap_single(dev, xfer->rx_dma, xfer->len, DMA_FROM_DEVICE);
502 + xfer->rx_dma = DMA_ERROR_CODE;
505 + /* spi disable dma */
506 + cmd = readl(mdata->base + SPI_CMD_REG);
507 + cmd &= ~SPI_CMD_TX_DMA_MASK;
508 + cmd &= ~SPI_CMD_RX_DMA_MASK;
509 + writel(cmd, mdata->base + SPI_CMD_REG);
512 + memcpy(xfer->rx_buf, mdata->rx_buf, xfer->len);
517 + kfree(mdata->tx_buf);
518 + kfree(mdata->rx_buf);
522 +static irqreturn_t mtk_spi_interrupt(int irq, void *dev_id)
524 + struct mtk_spi_ddata *mdata = dev_id;
527 + reg_val = readl(mdata->base + SPI_STATUS0_REG);
529 + mdata->state = PAUSED;
531 + mdata->state = IDLE;
532 + complete(&mdata->done);
534 + return IRQ_HANDLED;
537 +static unsigned long mtk_get_device_prop(struct platform_device *pdev)
539 + const struct of_device_id *match;
541 + match = of_match_node(mtk_spi_of_match, pdev->dev.of_node);
542 + return (unsigned long)match->data;
545 +static int mtk_spi_probe(struct platform_device *pdev)
547 + struct spi_master *master;
548 + struct mtk_spi_ddata *mdata;
549 + struct resource *res;
552 + master = spi_alloc_master(&pdev->dev, sizeof(struct mtk_spi_ddata));
554 + dev_err(&pdev->dev, "failed to alloc spi master\n");
558 + platform_set_drvdata(pdev, master);
560 + master->dev.of_node = pdev->dev.of_node;
561 + master->bus_num = pdev->id;
562 + master->num_chipselect = 1;
563 + master->mode_bits = SPI_CPOL | SPI_CPHA;
565 + mdata = spi_master_get_devdata(master);
567 + mdata->bitbang.master = master;
568 + mdata->bitbang.chipselect = mtk_spi_chipselect;
569 + mdata->bitbang.setup_transfer = mtk_spi_setup_transfer;
570 + mdata->bitbang.txrx_bufs = mtk_spi_txrx_bufs;
571 + mdata->platform_compat = mtk_get_device_prop(pdev);
573 + if (mdata->platform_compat & COMPAT_MT8173) {
574 + ret = of_property_read_u32(pdev->dev.of_node, "pad-select",
577 + dev_err(&pdev->dev, "failed to read pad select: %d\n",
582 + if (mdata->pad_sel > MT8173_MAX_PAD_SEL) {
583 + dev_err(&pdev->dev, "wrong pad-select: %u\n",
589 + init_completion(&mdata->done);
591 + mdata->clk = devm_clk_get(&pdev->dev, "main");
592 + if (IS_ERR(mdata->clk)) {
593 + ret = PTR_ERR(mdata->clk);
594 + dev_err(&pdev->dev, "failed to get clock: %d\n", ret);
598 + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
601 + dev_err(&pdev->dev, "failed to determine base address\n");
605 + mdata->base = devm_ioremap_resource(&pdev->dev, res);
606 + if (IS_ERR(mdata->base)) {
607 + ret = PTR_ERR(mdata->base);
611 + ret = platform_get_irq(pdev, 0);
613 + dev_err(&pdev->dev, "failed to get irq (%d)\n", ret);
619 + if (!pdev->dev.dma_mask)
620 + pdev->dev.dma_mask = &pdev->dev.coherent_dma_mask;
622 + mdata->bitbang.master->dev.dma_mask = pdev->dev.dma_mask;
624 + ret = clk_prepare_enable(mdata->clk);
626 + dev_err(&pdev->dev, "failed to enable clock (%d)\n", ret);
630 + ret = devm_request_irq(&pdev->dev, mdata->irq, mtk_spi_interrupt,
631 + IRQF_TRIGGER_NONE, dev_name(&pdev->dev), mdata);
633 + dev_err(&pdev->dev, "failed to register irq (%d)\n", ret);
634 + goto err_disable_clk;
637 + ret = spi_bitbang_start(&mdata->bitbang);
639 + dev_err(&pdev->dev, "spi_bitbang_start failed (%d)\n", ret);
641 + clk_disable_unprepare(mdata->clk);
643 + spi_master_put(master);
649 +static int mtk_spi_remove(struct platform_device *pdev)
651 + struct spi_master *master = platform_get_drvdata(pdev);
652 + struct mtk_spi_ddata *mdata = spi_master_get_devdata(master);
654 + spi_bitbang_stop(&mdata->bitbang);
655 + mtk_spi_reset(mdata);
656 + clk_disable_unprepare(mdata->clk);
657 + spi_master_put(master);
662 +struct platform_driver mtk_spi_driver = {
665 + .of_match_table = mtk_spi_of_match,
667 + .probe = mtk_spi_probe,
668 + .remove = mtk_spi_remove,
671 +module_platform_driver(mtk_spi_driver);
673 +MODULE_DESCRIPTION("MTK SPI Controller driver");
674 +MODULE_AUTHOR("Leilk Liu <leilk.liu@mediatek.com>");
675 +MODULE_LICENSE("GPL v2");
676 +MODULE_ALIAS("platform: mtk_spi");