target/linux/mediatek/patches/0028-pwm-add-Mediatek-display-PWM-driver-support.patch

   1 From 77e664940f6daa86965d16a2047188519341a31a Mon Sep 17 00:00:00 2001
   2 From: YH Huang <yh.huang@mediatek.com>
   3 Date: Mon, 11 May 2015 17:26:22 +0800
   4 Subject: [PATCH 28/76] pwm: add Mediatek display PWM driver support
   5
   6 Add display PWM driver support to modify backlight for MT8173/MT6595.
   7
   8 Signed-off-by: YH Huang <yh.huang@mediatek.com>
   9 ---
  10  drivers/pwm/Kconfig             |    9 ++
  11  drivers/pwm/Makefile            |    1 +
  12  drivers/pwm/pwm-disp-mediatek.c |  225 +++++++++++++++++++++++++++++++++++++++
  13  3 files changed, 235 insertions(+)
  14  create mode 100644 drivers/pwm/pwm-disp-mediatek.c
  15
  16 diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig
  17 index b1541f4..9edbb5a 100644
  18 --- a/drivers/pwm/Kconfig
  19 +++ b/drivers/pwm/Kconfig
  20 @@ -111,6 +111,15 @@ config PWM_CLPS711X
  21           To compile this driver as a module, choose M here: the module
  22           will be called pwm-clps711x.
  23
  24 +config PWM_DISP_MEDIATEK
  25 +       tristate "MEDIATEK display PWM driver"
  26 +       depends on OF
  27 +       help
  28 +         Generic PWM framework driver for mediatek disp-pwm device.
  29 +
  30 +         To compile this driver as a module, choose M here: the module
  31 +         will be called pwm-disp-mediatek.
  32 +
  33  config PWM_EP93XX
  34         tristate "Cirrus Logic EP93xx PWM support"
  35         depends on ARCH_EP93XX
  36 diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile
  37 index ec50eb5..c5ff72a 100644
  38 --- a/drivers/pwm/Makefile
  39 +++ b/drivers/pwm/Makefile
  40 @@ -8,6 +8,7 @@ obj-$(CONFIG_PWM_BCM_KONA)      += pwm-bcm-kona.o
  41  obj-$(CONFIG_PWM_BCM2835)      += pwm-bcm2835.o
  42  obj-$(CONFIG_PWM_BFIN)         += pwm-bfin.o
  43  obj-$(CONFIG_PWM_CLPS711X)     += pwm-clps711x.o
  44 +obj-$(CONFIG_PWM_DISP_MEDIATEK)        += pwm-disp-mediatek.o
  45  obj-$(CONFIG_PWM_EP93XX)       += pwm-ep93xx.o
  46  obj-$(CONFIG_PWM_FSL_FTM)      += pwm-fsl-ftm.o
  47  obj-$(CONFIG_PWM_IMG)          += pwm-img.o
  48 diff --git a/drivers/pwm/pwm-disp-mediatek.c b/drivers/pwm/pwm-disp-mediatek.c
  49 new file mode 100644
  50 index 0000000..38293af
  51 --- /dev/null
  52 +++ b/drivers/pwm/pwm-disp-mediatek.c
  53 @@ -0,0 +1,225 @@
  54 +/*
  55 + * Mediatek display pulse-width-modulation controller driver.
  56 + * Copyright (c) 2015 MediaTek Inc.
  57 + * Author: YH Huang <yh.huang@mediatek.com>
  58 + *
  59 + * This program is free software; you can redistribute it and/or modify
  60 + * it under the terms of the GNU General Public License version 2 as
  61 + * published by the Free Software Foundation.
  62 + *
  63 + * This program is distributed in the hope that it will be useful,
  64 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  65 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  66 + * GNU General Public License for more details.
  67 + */
  68 +
  69 +#include <linux/clk.h>
  70 +#include <linux/err.h>
  71 +#include <linux/io.h>
  72 +#include <linux/module.h>
  73 +#include <linux/of.h>
  74 +#include <linux/pwm.h>
  75 +#include <linux/platform_device.h>
  76 +#include <linux/slab.h>
  77 +
  78 +#define DISP_PWM_EN_OFF                        (0x0)
  79 +#define PWM_ENABLE_SHIFT               (0x0)
  80 +#define PWM_ENABLE_MASK                        (0x1 << PWM_ENABLE_SHIFT)
  81 +
  82 +#define DISP_PWM_COMMIT_OFF            (0x08)
  83 +#define PWM_COMMIT_SHIFT               (0x0)
  84 +#define PWM_COMMIT_MASK                        (0x1 << PWM_COMMIT_SHIFT)
  85 +
  86 +#define DISP_PWM_CON_0_OFF             (0x10)
  87 +#define PWM_CLKDIV_SHIFT               (0x10)
  88 +#define PWM_CLKDIV_MASK                        (0x3ff << PWM_CLKDIV_SHIFT)
  89 +#define PWM_CLKDIV_MAX                 (0x000003ff)
  90 +
  91 +#define DISP_PWM_CON_1_OFF             (0x14)
  92 +#define PWM_PERIOD_SHIFT               (0x0)
  93 +#define PWM_PERIOD_MASK                        (0xfff << PWM_PERIOD_SHIFT)
  94 +#define PWM_PERIOD_MAX                 (0x00000fff)
  95 +/* Shift log2(PWM_PERIOD_MAX + 1) as divisor */
  96 +#define PWM_PERIOD_BIT_SHIFT           12
  97 +
  98 +#define PWM_HIGH_WIDTH_SHIFT           (0x10)
  99 +#define PWM_HIGH_WIDTH_MASK            (0x1fff << PWM_HIGH_WIDTH_SHIFT)
 100 +
 101 +#define NUM_PWM 1
 102 +
 103 +struct mtk_disp_pwm_chip {
 104 +       struct pwm_chip chip;
 105 +       struct device   *dev;
 106 +       struct clk      *clk_main;
 107 +       struct clk      *clk_mm;
 108 +       void __iomem    *mmio_base;
 109 +};
 110 +
 111 +static void mtk_disp_pwm_setting(void __iomem *address, u32 value, u32 mask)
 112 +{
 113 +       u32 val;
 114 +
 115 +       val = readl(address);
 116 +       val &= ~mask;
 117 +       val |= value;
 118 +       writel(val, address);
 119 +}
 120 +
 121 +static int mtk_disp_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
 122 +                              int duty_ns, int period_ns)
 123 +{
 124 +       struct mtk_disp_pwm_chip *mpc;
 125 +       u64 div, rate;
 126 +       u32 clk_div, period, high_width, rem;
 127 +
 128 +       /*
 129 +        * Find period, high_width and clk_div to suit duty_ns and period_ns.
 130 +        * Calculate proper div value to keep period value in the bound.
 131 +        *
 132 +        * period_ns = 10^9 * (clk_div + 1) * (period +1) / PWM_CLK_RATE
 133 +        * duty_ns = 10^9 * (clk_div + 1) * (high_width + 1) / PWM_CLK_RATE
 134 +        *
 135 +        * period = (PWM_CLK_RATE * period_ns) / (10^9 * (clk_div + 1)) - 1
 136 +        * high_width = (PWM_CLK_RATE * duty_ns) / (10^9 * (clk_div + 1)) - 1
 137 +        */
 138 +       mpc = container_of(chip, struct mtk_disp_pwm_chip, chip);
 139 +       rate = clk_get_rate(mpc->clk_main);
 140 +       clk_div = div_u64_rem(rate * period_ns, NSEC_PER_SEC, &rem) >>
 141 +                               PWM_PERIOD_BIT_SHIFT;
 142 +       if (clk_div > PWM_CLKDIV_MAX)
 143 +               return -EINVAL;
 144 +
 145 +       div = clk_div + 1;
 146 +       period = div64_u64(rate * period_ns, NSEC_PER_SEC * div);
 147 +       if (period > 0)
 148 +               period--;
 149 +       high_width = div64_u64(rate * duty_ns, NSEC_PER_SEC * div);
 150 +       if (high_width > 0)
 151 +               high_width--;
 152 +
 153 +       mtk_disp_pwm_setting(mpc->mmio_base + DISP_PWM_CON_0_OFF,
 154 +                            clk_div << PWM_CLKDIV_SHIFT, PWM_CLKDIV_MASK);
 155 +       mtk_disp_pwm_setting(mpc->mmio_base + DISP_PWM_CON_1_OFF,
 156 +                            (period << PWM_PERIOD_SHIFT) |
 157 +                       (high_width << PWM_HIGH_WIDTH_SHIFT),
 158 +                       PWM_PERIOD_MASK | PWM_HIGH_WIDTH_MASK);
 159 +
 160 +       mtk_disp_pwm_setting(mpc->mmio_base + DISP_PWM_COMMIT_OFF,
 161 +                            1 << PWM_COMMIT_SHIFT, PWM_COMMIT_MASK);
 162 +       mtk_disp_pwm_setting(mpc->mmio_base + DISP_PWM_COMMIT_OFF,
 163 +                            0 << PWM_COMMIT_SHIFT, PWM_COMMIT_MASK);
 164 +
 165 +       return 0;
 166 +}
 167 +
 168 +static int mtk_disp_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
 169 +{
 170 +       struct mtk_disp_pwm_chip *mpc;
 171 +
 172 +       mpc = container_of(chip, struct mtk_disp_pwm_chip, chip);
 173 +       mtk_disp_pwm_setting(mpc->mmio_base + DISP_PWM_EN_OFF,
 174 +                            1 << PWM_ENABLE_SHIFT, PWM_ENABLE_MASK);
 175 +
 176 +       return 0;
 177 +}
 178 +
 179 +static void mtk_disp_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
 180 +{
 181 +       struct mtk_disp_pwm_chip *mpc;
 182 +
 183 +       mpc = container_of(chip, struct mtk_disp_pwm_chip, chip);
 184 +       mtk_disp_pwm_setting(mpc->mmio_base + DISP_PWM_EN_OFF,
 185 +                            0 << PWM_ENABLE_SHIFT, PWM_ENABLE_MASK);
 186 +}
 187 +
 188 +static const struct pwm_ops mtk_disp_pwm_ops = {
 189 +       .config = mtk_disp_pwm_config,
 190 +       .enable = mtk_disp_pwm_enable,
 191 +       .disable = mtk_disp_pwm_disable,
 192 +       .owner = THIS_MODULE,
 193 +};
 194 +
 195 +static int mtk_disp_pwm_probe(struct platform_device *pdev)
 196 +{
 197 +       struct mtk_disp_pwm_chip *pwm;
 198 +       struct resource *r;
 199 +       int ret;
 200 +
 201 +       pwm = devm_kzalloc(&pdev->dev, sizeof(*pwm), GFP_KERNEL);
 202 +       if (!pwm)
 203 +               return -ENOMEM;
 204 +
 205 +       pwm->dev = &pdev->dev;
 206 +
 207 +       r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 208 +       pwm->mmio_base = devm_ioremap_resource(&pdev->dev, r);
 209 +       if (IS_ERR(pwm->mmio_base))
 210 +               return PTR_ERR(pwm->mmio_base);
 211 +
 212 +       pwm->clk_main = devm_clk_get(&pdev->dev, "main");
 213 +       if (IS_ERR(pwm->clk_main))
 214 +               return PTR_ERR(pwm->clk_main);
 215 +       pwm->clk_mm = devm_clk_get(&pdev->dev, "mm");
 216 +       if (IS_ERR(pwm->clk_mm))
 217 +               return PTR_ERR(pwm->clk_mm);
 218 +
 219 +       ret = clk_prepare_enable(pwm->clk_main);
 220 +       if (ret < 0)
 221 +               return ret;
 222 +       ret = clk_prepare_enable(pwm->clk_mm);
 223 +       if (ret < 0) {
 224 +               clk_disable_unprepare(pwm->clk_main);
 225 +               return ret;
 226 +       }
 227 +
 228 +       platform_set_drvdata(pdev, pwm);
 229 +
 230 +       pwm->chip.dev = &pdev->dev;
 231 +       pwm->chip.ops = &mtk_disp_pwm_ops;
 232 +       pwm->chip.base = -1;
 233 +       pwm->chip.npwm = NUM_PWM;
 234 +
 235 +       ret = pwmchip_add(&pwm->chip);
 236 +       if (ret < 0) {
 237 +               dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret);
 238 +               return ret;
 239 +       }
 240 +
 241 +       return 0;
 242 +}
 243 +
 244 +static int mtk_disp_pwm_remove(struct platform_device *pdev)
 245 +{
 246 +       struct mtk_disp_pwm_chip *pc = platform_get_drvdata(pdev);
 247 +
 248 +       if (WARN_ON(!pc))
 249 +               return -ENODEV;
 250 +
 251 +       clk_disable_unprepare(pc->clk_main);
 252 +       clk_disable_unprepare(pc->clk_mm);
 253 +
 254 +       return pwmchip_remove(&pc->chip);
 255 +}
 256 +
 257 +static const struct of_device_id mtk_disp_pwm_of_match[] = {
 258 +       { .compatible = "mediatek,mt6595-disp-pwm" },
 259 +       { }
 260 +};
 261 +
 262 +MODULE_DEVICE_TABLE(of, mtk_disp_pwm_of_match);
 263 +
 264 +static struct platform_driver mtk_disp_pwm_driver = {
 265 +       .driver = {
 266 +               .name = "mediatek-disp-pwm",
 267 +               .owner = THIS_MODULE,
 268 +               .of_match_table = mtk_disp_pwm_of_match,
 269 +       },
 270 +       .probe = mtk_disp_pwm_probe,
 271 +       .remove = mtk_disp_pwm_remove,
 272 +};
 273 +
 274 +module_platform_driver(mtk_disp_pwm_driver);
 275 +
 276 +MODULE_AUTHOR("YH Huang <yh.huang@mediatek.com>");
 277 +MODULE_DESCRIPTION("MediaTek SoC display PWM driver");
 278 +MODULE_LICENSE("GPL v2");
 279 --
 280 1.7.10.4
 281