1 From 2471bc43c6079ab956a04f29ffd1ab8371b7bd73 Mon Sep 17 00:00:00 2001
2 From: Xudong Chen <xudong.chen@mediatek.com>
3 Date: Wed, 6 May 2015 16:37:06 +0800
4 Subject: [PATCH 30/76] I2C: mediatek: Add driver for MediaTek I2C controller
6 The mediatek SoCs have I2C controller that handle I2C transfer.
7 This patch include common I2C bus driver.
8 This driver is compatible with I2C controller on mt65xx/mt81xx.
10 Signed-off-by: Xudong Chen <xudong.chen@mediatek.com>
11 Signed-off-by: Liguo Zhang <liguo.zhang@mediatek.com>
12 Signed-off-by: Eddie Huang <eddie.huang@mediatek.com>
14 drivers/i2c/busses/Kconfig | 9 +
15 drivers/i2c/busses/Makefile | 1 +
16 drivers/i2c/busses/i2c-mt65xx.c | 700 +++++++++++++++++++++++++++++++++++++++
17 3 files changed, 710 insertions(+)
18 create mode 100644 drivers/i2c/busses/i2c-mt65xx.c
20 diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
21 index 2255af2..14c7266 100644
22 --- a/drivers/i2c/busses/Kconfig
23 +++ b/drivers/i2c/busses/Kconfig
24 @@ -620,6 +620,15 @@ config I2C_MPC
25 This driver can also be built as a module. If so, the module
26 will be called i2c-mpc.
29 + tristate "MediaTek I2C adapter"
30 + depends on ARCH_MEDIATEK || COMPILE_TEST
32 + This selects the MediaTek(R) Integrated Inter Circuit bus driver
33 + for MT65xx and MT81xx.
34 + If you want to use MediaTek(R) I2C interface, say Y or M here.
38 tristate "Marvell mv64xxx I2C Controller"
39 depends on MV64X60 || PLAT_ORION || ARCH_SUNXI
40 diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile
41 index cdf941d..abbf422 100644
42 --- a/drivers/i2c/busses/Makefile
43 +++ b/drivers/i2c/busses/Makefile
44 @@ -60,6 +60,7 @@ obj-$(CONFIG_I2C_JZ4780) += i2c-jz4780.o
45 obj-$(CONFIG_I2C_KEMPLD) += i2c-kempld.o
46 obj-$(CONFIG_I2C_MESON) += i2c-meson.o
47 obj-$(CONFIG_I2C_MPC) += i2c-mpc.o
48 +obj-$(CONFIG_I2C_MT65XX) += i2c-mt65xx.o
49 obj-$(CONFIG_I2C_MV64XXX) += i2c-mv64xxx.o
50 obj-$(CONFIG_I2C_MXS) += i2c-mxs.o
51 obj-$(CONFIG_I2C_NOMADIK) += i2c-nomadik.o
52 diff --git a/drivers/i2c/busses/i2c-mt65xx.c b/drivers/i2c/busses/i2c-mt65xx.c
54 index 0000000..faecf7e
56 +++ b/drivers/i2c/busses/i2c-mt65xx.c
59 + * Copyright (c) 2014 MediaTek Inc.
60 + * Author: Xudong.chen <xudong.chen@mediatek.com>
62 + * This program is free software; you can redistribute it and/or modify
63 + * it under the terms of the GNU General Public License version 2 as
64 + * published by the Free Software Foundation.
66 + * This program is distributed in the hope that it will be useful,
67 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
68 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
69 + * GNU General Public License for more details.
72 +#include <linux/kernel.h>
73 +#include <linux/module.h>
74 +#include <linux/slab.h>
75 +#include <linux/i2c.h>
76 +#include <linux/init.h>
77 +#include <linux/interrupt.h>
78 +#include <linux/sched.h>
79 +#include <linux/delay.h>
80 +#include <linux/errno.h>
81 +#include <linux/err.h>
82 +#include <linux/device.h>
83 +#include <linux/platform_device.h>
84 +#include <linux/mm.h>
85 +#include <linux/dma-mapping.h>
86 +#include <linux/scatterlist.h>
87 +#include <linux/io.h>
88 +#include <linux/of_address.h>
89 +#include <linux/of_irq.h>
90 +#include <linux/clk.h>
91 +#include <linux/completion.h>
93 +#define I2C_HS_NACKERR (1 << 2)
94 +#define I2C_ACKERR (1 << 1)
95 +#define I2C_TRANSAC_COMP (1 << 0)
96 +#define I2C_TRANSAC_START (1 << 0)
97 +#define I2C_TIMING_STEP_DIV_MASK (0x3f << 0)
98 +#define I2C_TIMING_SAMPLE_COUNT_MASK (0x7 << 0)
99 +#define I2C_TIMING_SAMPLE_DIV_MASK (0x7 << 8)
100 +#define I2C_TIMING_DATA_READ_MASK (0x7 << 12)
101 +#define I2C_DCM_DISABLE 0x0000
102 +#define I2C_IO_CONFIG_OPEN_DRAIN 0x0003
103 +#define I2C_IO_CONFIG_PUSH_PULL 0x0000
104 +#define I2C_SOFT_RST 0x0001
105 +#define I2C_FIFO_ADDR_CLR 0x0001
106 +#define I2C_DELAY_LEN 0x0002
107 +#define I2C_ST_START_CON 0x8001
108 +#define I2C_FS_START_CON 0x1800
109 +#define I2C_TIME_CLR_VALUE 0x0000
110 +#define I2C_TIME_DEFAULT_VALUE 0x0003
111 +#define I2C_FS_TIME_INIT_VALUE 0x1303
112 +#define I2C_WRRD_TRANAC_VALUE 0x0002
113 +#define I2C_RD_TRANAC_VALUE 0x0001
115 +#define I2C_DMA_CON_TX 0x0000
116 +#define I2C_DMA_CON_RX 0x0001
117 +#define I2C_DMA_START_EN 0x0001
118 +#define I2C_DMA_INT_FLAG_NONE 0x0000
119 +#define I2C_DMA_CLR_FLAG 0x0000
121 +#define I2C_DEFAUT_SPEED 100000 /* hz */
122 +#define MAX_FS_MODE_SPEED 400000
123 +#define MAX_HS_MODE_SPEED 3400000
124 +#define MAX_MSG_NUM_MT6577 1
125 +#define MAX_DMA_TRANS_SIZE_MT6577 255
126 +#define MAX_WRRD_TRANS_SIZE_MT6577 31
127 +#define MAX_SAMPLE_CNT_DIV 8
128 +#define MAX_STEP_CNT_DIV 64
129 +#define MAX_HS_STEP_CNT_DIV 8
131 +#define I2C_CONTROL_RS (0x1 << 1)
132 +#define I2C_CONTROL_DMA_EN (0x1 << 2)
133 +#define I2C_CONTROL_CLK_EXT_EN (0x1 << 3)
134 +#define I2C_CONTROL_DIR_CHANGE (0x1 << 4)
135 +#define I2C_CONTROL_ACKERR_DET_EN (0x1 << 5)
136 +#define I2C_CONTROL_TRANSFER_LEN_CHANGE (0x1 << 6)
137 +#define I2C_CONTROL_WRAPPER (0x1 << 0)
139 +#define I2C_DRV_NAME "mt-i2c"
141 +enum DMA_REGS_OFFSET {
142 + OFFSET_INT_FLAG = 0x0,
143 + OFFSET_INT_EN = 0x04,
146 + OFFSET_TX_MEM_ADDR = 0x1c,
147 + OFFSET_RX_MEM_ADDR = 0x20,
148 + OFFSET_TX_LEN = 0x24,
149 + OFFSET_RX_LEN = 0x28,
152 +enum i2c_trans_st_rs {
153 + I2C_TRANS_STOP = 0,
154 + I2C_TRANS_REPEATED_START,
163 +enum I2C_REGS_OFFSET {
164 + OFFSET_DATA_PORT = 0x0,
165 + OFFSET_SLAVE_ADDR = 0x04,
166 + OFFSET_INTR_MASK = 0x08,
167 + OFFSET_INTR_STAT = 0x0c,
168 + OFFSET_CONTROL = 0x10,
169 + OFFSET_TRANSFER_LEN = 0x14,
170 + OFFSET_TRANSAC_LEN = 0x18,
171 + OFFSET_DELAY_LEN = 0x1c,
172 + OFFSET_TIMING = 0x20,
173 + OFFSET_START = 0x24,
174 + OFFSET_EXT_CONF = 0x28,
175 + OFFSET_FIFO_STAT = 0x30,
176 + OFFSET_FIFO_THRESH = 0x34,
177 + OFFSET_FIFO_ADDR_CLR = 0x38,
178 + OFFSET_IO_CONFIG = 0x40,
179 + OFFSET_RSV_DEBUG = 0x44,
181 + OFFSET_SOFTRESET = 0x50,
182 + OFFSET_DCM_EN = 0x54,
183 + OFFSET_PATH_DIR = 0x60,
184 + OFFSET_DEBUGSTAT = 0x64,
185 + OFFSET_DEBUGCTRL = 0x68,
186 + OFFSET_TRANSFER_LEN_AUX = 0x6c,
189 +struct mtk_i2c_data {
190 + unsigned int clk_frequency; /* bus speed in Hz */
191 + unsigned int flags;
192 + unsigned int clk_src_div;
195 +struct mtk_i2c_compatible {
196 + const struct i2c_adapter_quirks *quirks;
197 + unsigned char pmic_i2c;
202 + struct i2c_adapter adap; /* i2c host adapter */
203 + struct device *dev;
204 + struct completion msg_complete;
206 + /* set in i2c probe */
207 + void __iomem *base; /* i2c base addr */
208 + void __iomem *pdmabase; /* dma base address*/
209 + struct clk *clk_main; /* main clock for i2c bus */
210 + struct clk *clk_dma; /* DMA clock for i2c via DMA */
211 + struct clk *clk_pmic; /* PMIC clock for i2c from PMIC */
212 + bool have_pmic; /* can use i2c pins from PMIC */
213 + bool use_push_pull; /* IO config push-pull mode */
215 + u16 irq_stat; /* interrupt status */
216 + unsigned int speed_hz; /* The speed in transfer */
217 + enum mtk_trans_op op;
219 + u16 high_speed_reg;
220 + const struct mtk_i2c_compatible *dev_comp;
223 +static const struct i2c_adapter_quirks mt6577_i2c_quirks = {
224 + .flags = I2C_AQ_COMB_WRITE_THEN_READ,
225 + .max_num_msgs = MAX_MSG_NUM_MT6577,
226 + .max_write_len = MAX_DMA_TRANS_SIZE_MT6577,
227 + .max_read_len = MAX_DMA_TRANS_SIZE_MT6577,
228 + .max_comb_1st_msg_len = MAX_DMA_TRANS_SIZE_MT6577,
229 + .max_comb_2nd_msg_len = MAX_WRRD_TRANS_SIZE_MT6577,
232 +static const struct mtk_i2c_compatible mt6577_compat = {
233 + .quirks = &mt6577_i2c_quirks,
238 +static const struct mtk_i2c_compatible mt6589_compat = {
239 + .quirks = &mt6577_i2c_quirks,
244 +static const struct of_device_id mtk_i2c_of_match[] = {
245 + { .compatible = "mediatek,mt6577-i2c", .data = (void *)&mt6577_compat },
246 + { .compatible = "mediatek,mt6589-i2c", .data = (void *)&mt6589_compat },
249 +MODULE_DEVICE_TABLE(of, mtk_i2c_of_match);
251 +static inline void mtk_i2c_writew(u16 value, struct mtk_i2c *i2c, u8 offset)
253 + writew(value, i2c->base + offset);
256 +static inline u16 mtk_i2c_readw(struct mtk_i2c *i2c, u8 offset)
258 + return readw(i2c->base + offset);
261 +static inline void mtk_i2c_writel_dma(u32 value, struct mtk_i2c *i2c, u8 offset)
263 + writel(value, i2c->pdmabase + offset);
266 +static int mtk_i2c_clock_enable(struct mtk_i2c *i2c)
270 + ret = clk_prepare_enable(i2c->clk_dma);
274 + ret = clk_prepare_enable(i2c->clk_main);
278 + if (i2c->have_pmic) {
279 + ret = clk_prepare_enable(i2c->clk_pmic);
286 + clk_disable_unprepare(i2c->clk_main);
288 + clk_disable_unprepare(i2c->clk_dma);
293 +static void mtk_i2c_clock_disable(struct mtk_i2c *i2c)
295 + if (i2c->have_pmic)
296 + clk_disable_unprepare(i2c->clk_pmic);
298 + clk_disable_unprepare(i2c->clk_main);
299 + clk_disable_unprepare(i2c->clk_dma);
302 +static void mtk_i2c_init_hw(struct mtk_i2c *i2c)
306 + mtk_i2c_writew(I2C_SOFT_RST, i2c, OFFSET_SOFTRESET);
308 + if (i2c->use_push_pull)
309 + mtk_i2c_writew(I2C_IO_CONFIG_PUSH_PULL, i2c, OFFSET_IO_CONFIG);
311 + mtk_i2c_writew(I2C_IO_CONFIG_OPEN_DRAIN, i2c, OFFSET_IO_CONFIG);
313 + if (i2c->dev_comp->dcm)
314 + mtk_i2c_writew(I2C_DCM_DISABLE, i2c, OFFSET_DCM_EN);
316 + mtk_i2c_writew(i2c->timing_reg, i2c, OFFSET_TIMING);
317 + mtk_i2c_writew(i2c->high_speed_reg, i2c, OFFSET_HS);
319 + /* If use i2c pin from PMIC mt6397 side, need set PATH_DIR first */
320 + if (i2c->have_pmic)
321 + mtk_i2c_writew(I2C_CONTROL_WRAPPER, i2c, OFFSET_PATH_DIR);
323 + control_reg = I2C_CONTROL_ACKERR_DET_EN |
324 + I2C_CONTROL_CLK_EXT_EN | I2C_CONTROL_DMA_EN;
325 + mtk_i2c_writew(control_reg, i2c, OFFSET_CONTROL);
326 + mtk_i2c_writew(I2C_DELAY_LEN, i2c, OFFSET_DELAY_LEN);
329 +/* calculate i2c port speed */
330 +static int mtk_i2c_set_speed(struct mtk_i2c *i2c, unsigned int clk_src_in_hz)
333 + unsigned int step_cnt;
334 + unsigned int sample_cnt;
337 + unsigned int max_step_cnt;
338 + unsigned int sample_div = MAX_SAMPLE_CNT_DIV;
339 + unsigned int step_div;
340 + unsigned int min_div;
341 + unsigned int best_mul;
342 + unsigned int cnt_mul;
344 + if (i2c->speed_hz > MAX_HS_MODE_SPEED)
346 + else if (i2c->speed_hz > MAX_FS_MODE_SPEED)
347 + max_step_cnt = MAX_HS_STEP_CNT_DIV;
349 + max_step_cnt = MAX_STEP_CNT_DIV;
351 + step_div = max_step_cnt;
352 + /* Find the best combination */
353 + khz = i2c->speed_hz / 1000;
354 + hclk = clk_src_in_hz / 1000;
355 + min_div = ((hclk >> 1) + khz - 1) / khz;
356 + best_mul = MAX_SAMPLE_CNT_DIV * max_step_cnt;
358 + for (sample_cnt = 1; sample_cnt <= MAX_SAMPLE_CNT_DIV; sample_cnt++) {
359 + step_cnt = (min_div + sample_cnt - 1) / sample_cnt;
360 + cnt_mul = step_cnt * sample_cnt;
361 + if (step_cnt > max_step_cnt)
364 + if (cnt_mul < best_mul) {
365 + best_mul = cnt_mul;
366 + sample_div = sample_cnt;
367 + step_div = step_cnt;
368 + if (best_mul == min_div)
373 + sample_cnt = sample_div;
374 + step_cnt = step_div;
375 + sclk = hclk / (2 * sample_cnt * step_cnt);
377 + dev_dbg(i2c->dev, "%s mode: unsupported speed (%ldkhz)\n",
378 + (i2c->speed_hz > MAX_HS_MODE_SPEED) ? "HS" : "ST/FT",
386 + if (i2c->speed_hz > MAX_FS_MODE_SPEED) {
387 + /* Set the hign speed mode register */
388 + i2c->timing_reg = I2C_FS_TIME_INIT_VALUE;
389 + i2c->high_speed_reg = I2C_TIME_DEFAULT_VALUE |
390 + (sample_cnt & I2C_TIMING_SAMPLE_COUNT_MASK) << 12 |
391 + (step_cnt & I2C_TIMING_SAMPLE_COUNT_MASK) << 8;
394 + (sample_cnt & I2C_TIMING_SAMPLE_COUNT_MASK) << 8 |
395 + (step_cnt & I2C_TIMING_STEP_DIV_MASK) << 0;
396 + /* Disable the high speed transaction */
397 + i2c->high_speed_reg = I2C_TIME_CLR_VALUE;
403 +static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs)
407 + dma_addr_t rpaddr = 0;
408 + dma_addr_t wpaddr = 0;
413 + reinit_completion(&i2c->msg_complete);
415 + control_reg = mtk_i2c_readw(i2c, OFFSET_CONTROL) &
416 + ~(I2C_CONTROL_DIR_CHANGE | I2C_CONTROL_RS);
417 + if (i2c->speed_hz > 400000)
418 + control_reg |= I2C_CONTROL_RS;
419 + if (i2c->op == I2C_MASTER_WRRD)
420 + control_reg |= I2C_CONTROL_DIR_CHANGE | I2C_CONTROL_RS;
421 + mtk_i2c_writew(control_reg, i2c, OFFSET_CONTROL);
423 + /* set start condition */
424 + if (i2c->speed_hz <= 100000)
425 + mtk_i2c_writew(I2C_ST_START_CON, i2c, OFFSET_EXT_CONF);
427 + mtk_i2c_writew(I2C_FS_START_CON, i2c, OFFSET_EXT_CONF);
429 + addr_reg = msgs->addr << 1;
430 + if (i2c->op == I2C_MASTER_RD)
432 + mtk_i2c_writew(addr_reg, i2c, OFFSET_SLAVE_ADDR);
434 + /* Clear interrupt status */
435 + mtk_i2c_writew(I2C_HS_NACKERR | I2C_ACKERR | I2C_TRANSAC_COMP,
436 + i2c, OFFSET_INTR_STAT);
437 + mtk_i2c_writew(I2C_FIFO_ADDR_CLR, i2c, OFFSET_FIFO_ADDR_CLR);
439 + /* Enable interrupt */
440 + mtk_i2c_writew(I2C_HS_NACKERR | I2C_ACKERR | I2C_TRANSAC_COMP,
441 + i2c, OFFSET_INTR_MASK);
443 + /* Set transfer and transaction len */
444 + if (i2c->op == I2C_MASTER_WRRD) {
445 + mtk_i2c_writew(msgs->len | ((msgs + 1)->len) << 8,
446 + i2c, OFFSET_TRANSFER_LEN);
447 + mtk_i2c_writew(I2C_WRRD_TRANAC_VALUE, i2c, OFFSET_TRANSAC_LEN);
449 + mtk_i2c_writew(msgs->len, i2c, OFFSET_TRANSFER_LEN);
450 + mtk_i2c_writew(I2C_RD_TRANAC_VALUE, i2c, OFFSET_TRANSAC_LEN);
453 + /* Prepare buffer data to start transfer */
454 + if (i2c->op == I2C_MASTER_RD) {
455 + mtk_i2c_writel_dma(I2C_DMA_INT_FLAG_NONE, i2c, OFFSET_INT_FLAG);
456 + mtk_i2c_writel_dma(I2C_DMA_CON_RX, i2c, OFFSET_CON);
457 + rpaddr = dma_map_single(i2c->adap.dev.parent, msgs->buf,
458 + msgs->len, DMA_FROM_DEVICE);
459 + if (dma_mapping_error(i2c->adap.dev.parent, rpaddr))
461 + mtk_i2c_writel_dma((u32)rpaddr, i2c, OFFSET_RX_MEM_ADDR);
462 + mtk_i2c_writel_dma(msgs->len, i2c, OFFSET_RX_LEN);
463 + } else if (i2c->op == I2C_MASTER_WR) {
464 + mtk_i2c_writel_dma(I2C_DMA_INT_FLAG_NONE, i2c, OFFSET_INT_FLAG);
465 + mtk_i2c_writel_dma(I2C_DMA_CON_TX, i2c, OFFSET_CON);
466 + wpaddr = dma_map_single(i2c->adap.dev.parent, msgs->buf,
467 + msgs->len, DMA_TO_DEVICE);
468 + if (dma_mapping_error(i2c->adap.dev.parent, wpaddr))
470 + mtk_i2c_writel_dma((u32)wpaddr, i2c, OFFSET_TX_MEM_ADDR);
471 + mtk_i2c_writel_dma(msgs->len, i2c, OFFSET_TX_LEN);
473 + mtk_i2c_writel_dma(I2C_DMA_CLR_FLAG, i2c, OFFSET_INT_FLAG);
474 + mtk_i2c_writel_dma(I2C_DMA_CLR_FLAG, i2c, OFFSET_CON);
475 + wpaddr = dma_map_single(i2c->adap.dev.parent, msgs->buf,
476 + msgs->len, DMA_TO_DEVICE);
477 + if (dma_mapping_error(i2c->adap.dev.parent, wpaddr))
479 + rpaddr = dma_map_single(i2c->adap.dev.parent, (msgs + 1)->buf,
482 + if (dma_mapping_error(i2c->adap.dev.parent, rpaddr)) {
483 + dma_unmap_single(i2c->adap.dev.parent, wpaddr,
484 + msgs->len, DMA_TO_DEVICE);
487 + mtk_i2c_writel_dma((u32)wpaddr, i2c, OFFSET_TX_MEM_ADDR);
488 + mtk_i2c_writel_dma((u32)rpaddr, i2c, OFFSET_RX_MEM_ADDR);
489 + mtk_i2c_writel_dma(msgs->len, i2c, OFFSET_TX_LEN);
490 + mtk_i2c_writel_dma((msgs + 1)->len, i2c, OFFSET_RX_LEN);
493 + /* flush before sending start */
495 + mtk_i2c_writel_dma(I2C_DMA_START_EN, i2c, OFFSET_EN);
496 + mtk_i2c_writew(I2C_TRANSAC_START, i2c, OFFSET_START);
498 + ret = wait_for_completion_timeout(&i2c->msg_complete,
499 + i2c->adap.timeout);
501 + /* Clear interrupt mask */
502 + mtk_i2c_writew(~(I2C_HS_NACKERR | I2C_ACKERR
503 + | I2C_TRANSAC_COMP), i2c, OFFSET_INTR_MASK);
505 + if (i2c->op == I2C_MASTER_WR) {
506 + dma_unmap_single(i2c->adap.dev.parent, wpaddr,
507 + msgs->len, DMA_TO_DEVICE);
508 + } else if (i2c->op == I2C_MASTER_RD) {
509 + dma_unmap_single(i2c->adap.dev.parent, rpaddr,
510 + msgs->len, DMA_FROM_DEVICE);
512 + dma_unmap_single(i2c->adap.dev.parent, wpaddr, msgs->len,
514 + dma_unmap_single(i2c->adap.dev.parent, rpaddr, (msgs + 1)->len,
519 + dev_dbg(i2c->dev, "addr: %x, transfer timeout\n", msgs->addr);
520 + mtk_i2c_init_hw(i2c);
524 + completion_done(&i2c->msg_complete);
526 + if (i2c->irq_stat & (I2C_HS_NACKERR | I2C_ACKERR)) {
527 + dev_dbg(i2c->dev, "addr: %x, transfer ACK error\n", msgs->addr);
528 + mtk_i2c_init_hw(i2c);
535 +static int mtk_i2c_transfer(struct i2c_adapter *adap,
536 + struct i2c_msg msgs[], int num)
539 + int left_num = num;
540 + struct mtk_i2c *i2c = i2c_get_adapdata(adap);
542 + ret = mtk_i2c_clock_enable(i2c);
546 + if (msgs->buf == NULL) {
547 + dev_dbg(i2c->dev, "data buffer is NULL.\n");
552 + if (msgs->flags & I2C_M_RD)
553 + i2c->op = I2C_MASTER_RD;
555 + i2c->op = I2C_MASTER_WR;
558 + /* combined two messages into one transaction */
559 + i2c->op = I2C_MASTER_WRRD;
563 + /* always use DMA mode. */
564 + ret = mtk_i2c_do_transfer(i2c, msgs);
568 + /* the return value is number of executed messages */
572 + mtk_i2c_clock_disable(i2c);
576 +static irqreturn_t mtk_i2c_irq(int irqno, void *dev_id)
578 + struct mtk_i2c *i2c = dev_id;
580 + i2c->irq_stat = mtk_i2c_readw(i2c, OFFSET_INTR_STAT);
581 + mtk_i2c_writew(I2C_HS_NACKERR | I2C_ACKERR
582 + | I2C_TRANSAC_COMP, i2c, OFFSET_INTR_STAT);
584 + complete(&i2c->msg_complete);
586 + return IRQ_HANDLED;
589 +static u32 mtk_i2c_functionality(struct i2c_adapter *adap)
591 + return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
594 +static const struct i2c_algorithm mtk_i2c_algorithm = {
595 + .master_xfer = mtk_i2c_transfer,
596 + .functionality = mtk_i2c_functionality,
599 +static int mtk_i2c_parse_dt(struct device_node *np, struct mtk_i2c *i2c,
600 + unsigned int *clk_src_div)
604 + ret = of_property_read_u32(np, "clock-frequency", &i2c->speed_hz);
606 + i2c->speed_hz = I2C_DEFAUT_SPEED;
608 + ret = of_property_read_u32(np, "clock-div", clk_src_div);
612 + if (*clk_src_div == 0)
615 + i2c->have_pmic = of_property_read_bool(np, "mediatek,have-pmic");
616 + i2c->use_push_pull =
617 + of_property_read_bool(np, "mediatek,use-push-pull");
622 +static int mtk_i2c_probe(struct platform_device *pdev)
624 + const struct of_device_id *of_id;
626 + struct mtk_i2c *i2c;
628 + unsigned int clk_src_in_hz;
629 + unsigned int clk_src_div;
630 + struct resource *res;
633 + i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL);
637 + ret = mtk_i2c_parse_dt(pdev->dev.of_node, i2c, &clk_src_div);
641 + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
642 + i2c->base = devm_ioremap_resource(&pdev->dev, res);
643 + if (IS_ERR(i2c->base))
644 + return PTR_ERR(i2c->base);
646 + res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
647 + i2c->pdmabase = devm_ioremap_resource(&pdev->dev, res);
648 + if (IS_ERR(i2c->pdmabase))
649 + return PTR_ERR(i2c->pdmabase);
651 + irq = platform_get_irq(pdev, 0);
655 + init_completion(&i2c->msg_complete);
657 + of_id = of_match_node(mtk_i2c_of_match, pdev->dev.of_node);
661 + i2c->dev_comp = of_id->data;
662 + i2c->adap.dev.of_node = pdev->dev.of_node;
663 + i2c->dev = &i2c->adap.dev;
664 + i2c->adap.dev.parent = &pdev->dev;
665 + i2c->adap.owner = THIS_MODULE;
666 + i2c->adap.algo = &mtk_i2c_algorithm;
667 + i2c->adap.quirks = i2c->dev_comp->quirks;
668 + i2c->adap.timeout = 2 * HZ;
669 + i2c->adap.retries = 1;
671 + if (i2c->have_pmic && !i2c->dev_comp->pmic_i2c)
674 + i2c->clk_main = devm_clk_get(&pdev->dev, "main");
675 + if (IS_ERR(i2c->clk_main)) {
676 + dev_err(&pdev->dev, "cannot get main clock\n");
677 + return PTR_ERR(i2c->clk_main);
680 + i2c->clk_dma = devm_clk_get(&pdev->dev, "dma");
681 + if (IS_ERR(i2c->clk_dma)) {
682 + dev_err(&pdev->dev, "cannot get dma clock\n");
683 + return PTR_ERR(i2c->clk_dma);
686 + clk = i2c->clk_main;
687 + if (i2c->have_pmic) {
688 + i2c->clk_pmic = devm_clk_get(&pdev->dev, "pmic");
689 + if (IS_ERR(i2c->clk_pmic)) {
690 + dev_err(&pdev->dev, "cannot get pmic clock\n");
691 + return PTR_ERR(i2c->clk_pmic);
693 + clk = i2c->clk_pmic;
695 + clk_src_in_hz = clk_get_rate(clk) / clk_src_div;
697 + dev_dbg(&pdev->dev, "clock source %p,clock src frequency %d\n",
698 + i2c->clk_main, clk_src_in_hz);
699 + strlcpy(i2c->adap.name, I2C_DRV_NAME, sizeof(i2c->adap.name));
701 + ret = mtk_i2c_set_speed(i2c, clk_src_in_hz);
703 + dev_err(&pdev->dev, "Failed to set the speed.\n");
707 + ret = mtk_i2c_clock_enable(i2c);
709 + dev_err(&pdev->dev, "clock enable failed!\n");
712 + mtk_i2c_init_hw(i2c);
713 + mtk_i2c_clock_disable(i2c);
715 + ret = devm_request_irq(&pdev->dev, irq, mtk_i2c_irq,
716 + IRQF_TRIGGER_NONE, I2C_DRV_NAME, i2c);
718 + dev_err(&pdev->dev,
719 + "Request I2C IRQ %d fail\n", irq);
723 + i2c_set_adapdata(&i2c->adap, i2c);
724 + ret = i2c_add_adapter(&i2c->adap);
726 + dev_err(&pdev->dev, "Failed to add i2c bus to i2c core\n");
730 + platform_set_drvdata(pdev, i2c);
735 +static int mtk_i2c_remove(struct platform_device *pdev)
737 + struct mtk_i2c *i2c = platform_get_drvdata(pdev);
739 + i2c_del_adapter(&i2c->adap);
744 +static struct platform_driver mtk_i2c_driver = {
745 + .probe = mtk_i2c_probe,
746 + .remove = mtk_i2c_remove,
748 + .name = I2C_DRV_NAME,
749 + .of_match_table = of_match_ptr(mtk_i2c_of_match),
753 +module_platform_driver(mtk_i2c_driver);
755 +MODULE_LICENSE("GPL v2");
756 +MODULE_DESCRIPTION("MediaTek I2C Bus Driver");
757 +MODULE_AUTHOR("Xudong Chen <xudong.chen@mediatek.com>");