1 From d83532fe7eb9cc7b8cc39dd9f2bbd9873d4e390b Mon Sep 17 00:00:00 2001
2 From: "pi-cheng.chen" <pi-cheng.chen@linaro.org>
3 Date: Mon, 8 Jun 2015 20:29:20 +0800
4 Subject: [PATCH 32/76] dt-bindings: mediatek: Add MT8173 cpufreq driver
7 This patch adds device tree binding document for MT8173 cpufreq driver.
9 Signed-off-by: Pi-Cheng Chen <pi-cheng.chen@linaro.org>
11 .../devicetree/bindings/cpufreq/cpufreq-mt8173.txt | 127 ++++++++++++++++++++
12 1 file changed, 127 insertions(+)
13 create mode 100644 Documentation/devicetree/bindings/cpufreq/cpufreq-mt8173.txt
16 +++ b/Documentation/devicetree/bindings/cpufreq/cpufreq-mt8173.txt
19 +Mediatek MT8173 cpufreq driver
22 +Mediatek MT8173 cpufreq driver for CPU frequency scaling.
25 +- clocks: A list of phandle + clock-specifier pairs for the clocks listed in clock names.
26 +- clock-names: Should contain the following:
27 + "cpu" - The multiplexer for clock input of CPU cluster.
28 + "intermediate" - A parent of "cpu" clock which is used as "intermediate" clock
29 + source (usually MAINPLL) when the original CPU PLL is under
30 + transition and not stable yet.
31 +- operating-points: Table of frequencies and voltage CPU could be transitioned into,
32 + Frequency should be in KHz units and voltage should be in microvolts.
33 +- proc-supply: Regulator for Vproc of CPU cluster.
36 +- sram-supply: Regulator for Vsram of CPU cluster. When present, the cpufreq driver
37 + needs to do "voltage trace" to step by step scale up/down Vproc and
38 + Vsram to fit SoC specific needs. When absent, the voltage scaling
39 + flow is handled by hardware, hence no software "voltage trace" is
45 + device_type = "cpu";
46 + compatible = "arm,cortex-a53";
48 + enable-method = "psci";
49 + cpu-idle-states = <&CPU_SLEEP_0>;
50 + clocks = <&infracfg CLK_INFRA_CA53SEL>,
51 + <&apmixedsys CLK_APMIXED_MAINPLL>;
52 + clock-names = "cpu", "intermediate";
53 + operating-points = <
66 + device_type = "cpu";
67 + compatible = "arm,cortex-a53";
69 + enable-method = "psci";
70 + cpu-idle-states = <&CPU_SLEEP_0>;
71 + clocks = <&infracfg CLK_INFRA_CA53SEL>,
72 + <&apmixedsys CLK_APMIXED_MAINPLL>;
73 + clock-names = "cpu", "intermediate";
74 + operating-points = <
87 + device_type = "cpu";
88 + compatible = "arm,cortex-a57";
90 + enable-method = "psci";
91 + cpu-idle-states = <&CPU_SLEEP_0>;
92 + clocks = <&infracfg CLK_INFRA_CA57SEL>,
93 + <&apmixedsys CLK_APMIXED_MAINPLL>;
94 + clock-names = "cpu", "intermediate";
95 + operating-points = <
108 + device_type = "cpu";
109 + compatible = "arm,cortex-a57";
111 + enable-method = "psci";
112 + cpu-idle-states = <&CPU_SLEEP_0>;
113 + clocks = <&infracfg CLK_INFRA_CA57SEL>,
114 + <&apmixedsys CLK_APMIXED_MAINPLL>;
115 + clock-names = "cpu", "intermediate";
116 + operating-points = <
129 + proc-supply = <&mt6397_vpca15_reg>;
133 + proc-supply = <&mt6397_vpca15_reg>;
137 + proc-supply = <&da9211_vcpu_reg>;
138 + sram-supply = <&mt6397_vsramca7_reg>;
142 + proc-supply = <&da9211_vcpu_reg>;
143 + sram-supply = <&mt6397_vsramca7_reg>;