1 From 32ea3b91046bea40cd1a7a4f16a24d75f53ca92a Mon Sep 17 00:00:00 2001
2 From: Hongzhou Yang <hongzhou.yang@mediatek.com>
3 Date: Mon, 18 May 2015 23:11:16 -0700
4 Subject: [PATCH 52/76] pinctrl: mediatek: add ies/smt control to common code.
6 Input enable and smt setting have different register,
9 Several mediatek soc use similar input enable/smt setting
10 procedure as mt8173, some soc use generic input enable/smt
11 setting, some soc has no input enable/smt setting. Adding
12 common code to handle all those cases, so future soc driver
15 Signed-off-by: Hongzhou Yang <hongzhou.yang@mediatek.com>
17 drivers/pinctrl/mediatek/pinctrl-mt8173.c | 201 +++++++++++++------------
18 drivers/pinctrl/mediatek/pinctrl-mtk-common.c | 82 +++++++---
19 drivers/pinctrl/mediatek/pinctrl-mtk-common.h | 31 +++-
20 3 files changed, 198 insertions(+), 116 deletions(-)
22 diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8173.c b/drivers/pinctrl/mediatek/pinctrl-mt8173.c
23 index cc44b27..a7e5b24 100644
24 --- a/drivers/pinctrl/mediatek/pinctrl-mt8173.c
25 +++ b/drivers/pinctrl/mediatek/pinctrl-mt8173.c
27 #include <linux/of_device.h>
28 #include <linux/pinctrl/pinctrl.h>
29 #include <linux/regmap.h>
30 +#include <linux/pinctrl/pinconf-generic.h>
31 #include <dt-bindings/pinctrl/mt65xx.h>
33 #include "pinctrl-mtk-common.h"
36 #define DRV_BASE 0xb00
39 - * struct mtk_pin_ies_smt_set - For special pins' ies and smt setting.
40 - * @start: The start pin number of those special pins.
41 - * @end: The end pin number of those special pins.
42 - * @offset: The offset of special setting register.
43 - * @bit: The bit of special setting register.
45 -struct mtk_pin_ies_smt_set {
48 - unsigned int offset;
52 -#define MTK_PIN_IES_SMT_SET(_start, _end, _offset, _bit) \
57 - .offset = _offset, \
60 static const struct mtk_pin_spec_pupd_set_samereg mt8173_spec_pupd[] = {
61 MTK_PIN_PUPD_SPEC_SR(119, 0xe00, 2, 1, 0), /* KROW0 */
62 MTK_PIN_PUPD_SPEC_SR(120, 0xe00, 6, 5, 4), /* KROW1 */
63 @@ -97,80 +76,114 @@ static int mt8173_spec_pull_set(struct regmap *regmap, unsigned int pin,
64 ARRAY_SIZE(mt8173_spec_pupd), pin, align, isup, r1r0);
67 -static const struct mtk_pin_ies_smt_set mt8173_ies_smt_set[] = {
68 - MTK_PIN_IES_SMT_SET(0, 4, 0x930, 1),
69 - MTK_PIN_IES_SMT_SET(5, 9, 0x930, 2),
70 - MTK_PIN_IES_SMT_SET(10, 13, 0x930, 10),
71 - MTK_PIN_IES_SMT_SET(14, 15, 0x940, 10),
72 - MTK_PIN_IES_SMT_SET(16, 16, 0x930, 0),
73 - MTK_PIN_IES_SMT_SET(17, 17, 0x950, 2),
74 - MTK_PIN_IES_SMT_SET(18, 21, 0x940, 3),
75 - MTK_PIN_IES_SMT_SET(29, 32, 0x930, 3),
76 - MTK_PIN_IES_SMT_SET(33, 33, 0x930, 4),
77 - MTK_PIN_IES_SMT_SET(34, 36, 0x930, 5),
78 - MTK_PIN_IES_SMT_SET(37, 38, 0x930, 6),
79 - MTK_PIN_IES_SMT_SET(39, 39, 0x930, 7),
80 - MTK_PIN_IES_SMT_SET(40, 41, 0x930, 9),
81 - MTK_PIN_IES_SMT_SET(42, 42, 0x940, 0),
82 - MTK_PIN_IES_SMT_SET(43, 44, 0x930, 11),
83 - MTK_PIN_IES_SMT_SET(45, 46, 0x930, 12),
84 - MTK_PIN_IES_SMT_SET(57, 64, 0xc20, 13),
85 - MTK_PIN_IES_SMT_SET(65, 65, 0xc10, 13),
86 - MTK_PIN_IES_SMT_SET(66, 66, 0xc00, 13),
87 - MTK_PIN_IES_SMT_SET(67, 67, 0xd10, 13),
88 - MTK_PIN_IES_SMT_SET(68, 68, 0xd00, 13),
89 - MTK_PIN_IES_SMT_SET(69, 72, 0x940, 14),
90 - MTK_PIN_IES_SMT_SET(73, 76, 0xc60, 13),
91 - MTK_PIN_IES_SMT_SET(77, 77, 0xc40, 13),
92 - MTK_PIN_IES_SMT_SET(78, 78, 0xc50, 13),
93 - MTK_PIN_IES_SMT_SET(79, 82, 0x940, 15),
94 - MTK_PIN_IES_SMT_SET(83, 83, 0x950, 0),
95 - MTK_PIN_IES_SMT_SET(84, 85, 0x950, 1),
96 - MTK_PIN_IES_SMT_SET(86, 91, 0x950, 2),
97 - MTK_PIN_IES_SMT_SET(92, 92, 0x930, 13),
98 - MTK_PIN_IES_SMT_SET(93, 95, 0x930, 14),
99 - MTK_PIN_IES_SMT_SET(96, 99, 0x930, 15),
100 - MTK_PIN_IES_SMT_SET(100, 103, 0xca0, 13),
101 - MTK_PIN_IES_SMT_SET(104, 104, 0xc80, 13),
102 - MTK_PIN_IES_SMT_SET(105, 105, 0xc90, 13),
103 - MTK_PIN_IES_SMT_SET(106, 107, 0x940, 4),
104 - MTK_PIN_IES_SMT_SET(108, 112, 0x940, 1),
105 - MTK_PIN_IES_SMT_SET(113, 116, 0x940, 2),
106 - MTK_PIN_IES_SMT_SET(117, 118, 0x940, 5),
107 - MTK_PIN_IES_SMT_SET(119, 124, 0x940, 6),
108 - MTK_PIN_IES_SMT_SET(125, 126, 0x940, 7),
109 - MTK_PIN_IES_SMT_SET(127, 127, 0x940, 0),
110 - MTK_PIN_IES_SMT_SET(128, 128, 0x950, 8),
111 - MTK_PIN_IES_SMT_SET(129, 130, 0x950, 9),
112 - MTK_PIN_IES_SMT_SET(131, 132, 0x950, 8),
113 - MTK_PIN_IES_SMT_SET(133, 134, 0x910, 8)
114 +static const struct mtk_pin_ies_smt_set mt8173_smt_set[] = {
115 + MTK_PIN_IES_SMT_SPEC(0, 4, 0x930, 1),
116 + MTK_PIN_IES_SMT_SPEC(5, 9, 0x930, 2),
117 + MTK_PIN_IES_SMT_SPEC(10, 13, 0x930, 10),
118 + MTK_PIN_IES_SMT_SPEC(14, 15, 0x940, 10),
119 + MTK_PIN_IES_SMT_SPEC(16, 16, 0x930, 0),
120 + MTK_PIN_IES_SMT_SPEC(17, 17, 0x950, 2),
121 + MTK_PIN_IES_SMT_SPEC(18, 21, 0x940, 3),
122 + MTK_PIN_IES_SMT_SPEC(29, 32, 0x930, 3),
123 + MTK_PIN_IES_SMT_SPEC(33, 33, 0x930, 4),
124 + MTK_PIN_IES_SMT_SPEC(34, 36, 0x930, 5),
125 + MTK_PIN_IES_SMT_SPEC(37, 38, 0x930, 6),
126 + MTK_PIN_IES_SMT_SPEC(39, 39, 0x930, 7),
127 + MTK_PIN_IES_SMT_SPEC(40, 41, 0x930, 9),
128 + MTK_PIN_IES_SMT_SPEC(42, 42, 0x940, 0),
129 + MTK_PIN_IES_SMT_SPEC(43, 44, 0x930, 11),
130 + MTK_PIN_IES_SMT_SPEC(45, 46, 0x930, 12),
131 + MTK_PIN_IES_SMT_SPEC(57, 64, 0xc20, 13),
132 + MTK_PIN_IES_SMT_SPEC(65, 65, 0xc10, 13),
133 + MTK_PIN_IES_SMT_SPEC(66, 66, 0xc00, 13),
134 + MTK_PIN_IES_SMT_SPEC(67, 67, 0xd10, 13),
135 + MTK_PIN_IES_SMT_SPEC(68, 68, 0xd00, 13),
136 + MTK_PIN_IES_SMT_SPEC(69, 72, 0x940, 14),
137 + MTK_PIN_IES_SMT_SPEC(73, 76, 0xc60, 13),
138 + MTK_PIN_IES_SMT_SPEC(77, 77, 0xc40, 13),
139 + MTK_PIN_IES_SMT_SPEC(78, 78, 0xc50, 13),
140 + MTK_PIN_IES_SMT_SPEC(79, 82, 0x940, 15),
141 + MTK_PIN_IES_SMT_SPEC(83, 83, 0x950, 0),
142 + MTK_PIN_IES_SMT_SPEC(84, 85, 0x950, 1),
143 + MTK_PIN_IES_SMT_SPEC(86, 91, 0x950, 2),
144 + MTK_PIN_IES_SMT_SPEC(92, 92, 0x930, 13),
145 + MTK_PIN_IES_SMT_SPEC(93, 95, 0x930, 14),
146 + MTK_PIN_IES_SMT_SPEC(96, 99, 0x930, 15),
147 + MTK_PIN_IES_SMT_SPEC(100, 103, 0xca0, 13),
148 + MTK_PIN_IES_SMT_SPEC(104, 104, 0xc80, 13),
149 + MTK_PIN_IES_SMT_SPEC(105, 105, 0xc90, 13),
150 + MTK_PIN_IES_SMT_SPEC(106, 107, 0x940, 4),
151 + MTK_PIN_IES_SMT_SPEC(108, 112, 0x940, 1),
152 + MTK_PIN_IES_SMT_SPEC(113, 116, 0x940, 2),
153 + MTK_PIN_IES_SMT_SPEC(117, 118, 0x940, 5),
154 + MTK_PIN_IES_SMT_SPEC(119, 124, 0x940, 6),
155 + MTK_PIN_IES_SMT_SPEC(125, 126, 0x940, 7),
156 + MTK_PIN_IES_SMT_SPEC(127, 127, 0x940, 0),
157 + MTK_PIN_IES_SMT_SPEC(128, 128, 0x950, 8),
158 + MTK_PIN_IES_SMT_SPEC(129, 130, 0x950, 9),
159 + MTK_PIN_IES_SMT_SPEC(131, 132, 0x950, 8),
160 + MTK_PIN_IES_SMT_SPEC(133, 134, 0x910, 8)
163 -static int spec_ies_smt_set(struct regmap *regmap, unsigned int pin,
164 - unsigned char align, int value)
166 - unsigned int i, reg_addr, bit;
169 - for (i = 0; i < ARRAY_SIZE(mt8173_ies_smt_set); i++) {
170 - if (pin >= mt8173_ies_smt_set[i].start &&
171 - pin <= mt8173_ies_smt_set[i].end) {
181 - reg_addr = mt8173_ies_smt_set[i].offset + align;
183 - reg_addr = mt8173_ies_smt_set[i].offset + (align << 1);
184 +static const struct mtk_pin_ies_smt_set mt8173_ies_set[] = {
185 + MTK_PIN_IES_SMT_SPEC(0, 4, 0x900, 1),
186 + MTK_PIN_IES_SMT_SPEC(5, 9, 0x900, 2),
187 + MTK_PIN_IES_SMT_SPEC(10, 13, 0x900, 10),
188 + MTK_PIN_IES_SMT_SPEC(14, 15, 0x910, 10),
189 + MTK_PIN_IES_SMT_SPEC(16, 16, 0x900, 0),
190 + MTK_PIN_IES_SMT_SPEC(17, 17, 0x920, 2),
191 + MTK_PIN_IES_SMT_SPEC(18, 21, 0x910, 3),
192 + MTK_PIN_IES_SMT_SPEC(29, 32, 0x900, 3),
193 + MTK_PIN_IES_SMT_SPEC(33, 33, 0x900, 4),
194 + MTK_PIN_IES_SMT_SPEC(34, 36, 0x900, 5),
195 + MTK_PIN_IES_SMT_SPEC(37, 38, 0x900, 6),
196 + MTK_PIN_IES_SMT_SPEC(39, 39, 0x900, 7),
197 + MTK_PIN_IES_SMT_SPEC(40, 41, 0x900, 9),
198 + MTK_PIN_IES_SMT_SPEC(42, 42, 0x910, 0),
199 + MTK_PIN_IES_SMT_SPEC(43, 44, 0x900, 11),
200 + MTK_PIN_IES_SMT_SPEC(45, 46, 0x900, 12),
201 + MTK_PIN_IES_SMT_SPEC(57, 64, 0xc20, 14),
202 + MTK_PIN_IES_SMT_SPEC(65, 65, 0xc10, 14),
203 + MTK_PIN_IES_SMT_SPEC(66, 66, 0xc00, 14),
204 + MTK_PIN_IES_SMT_SPEC(67, 67, 0xd10, 14),
205 + MTK_PIN_IES_SMT_SPEC(68, 68, 0xd00, 14),
206 + MTK_PIN_IES_SMT_SPEC(69, 72, 0x910, 14),
207 + MTK_PIN_IES_SMT_SPEC(73, 76, 0xc60, 14),
208 + MTK_PIN_IES_SMT_SPEC(77, 77, 0xc40, 14),
209 + MTK_PIN_IES_SMT_SPEC(78, 78, 0xc50, 14),
210 + MTK_PIN_IES_SMT_SPEC(79, 82, 0x910, 15),
211 + MTK_PIN_IES_SMT_SPEC(83, 83, 0x920, 0),
212 + MTK_PIN_IES_SMT_SPEC(84, 85, 0x920, 1),
213 + MTK_PIN_IES_SMT_SPEC(86, 91, 0x920, 2),
214 + MTK_PIN_IES_SMT_SPEC(92, 92, 0x900, 13),
215 + MTK_PIN_IES_SMT_SPEC(93, 95, 0x900, 14),
216 + MTK_PIN_IES_SMT_SPEC(96, 99, 0x900, 15),
217 + MTK_PIN_IES_SMT_SPEC(100, 103, 0xca0, 14),
218 + MTK_PIN_IES_SMT_SPEC(104, 104, 0xc80, 14),
219 + MTK_PIN_IES_SMT_SPEC(105, 105, 0xc90, 14),
220 + MTK_PIN_IES_SMT_SPEC(106, 107, 0x91, 4),
221 + MTK_PIN_IES_SMT_SPEC(108, 112, 0x910, 1),
222 + MTK_PIN_IES_SMT_SPEC(113, 116, 0x910, 2),
223 + MTK_PIN_IES_SMT_SPEC(117, 118, 0x910, 5),
224 + MTK_PIN_IES_SMT_SPEC(119, 124, 0x910, 6),
225 + MTK_PIN_IES_SMT_SPEC(125, 126, 0x910, 7),
226 + MTK_PIN_IES_SMT_SPEC(127, 127, 0x910, 0),
227 + MTK_PIN_IES_SMT_SPEC(128, 128, 0x920, 8),
228 + MTK_PIN_IES_SMT_SPEC(129, 130, 0x920, 9),
229 + MTK_PIN_IES_SMT_SPEC(131, 132, 0x920, 8),
230 + MTK_PIN_IES_SMT_SPEC(133, 134, 0x910, 8)
233 - bit = BIT(mt8173_ies_smt_set[i].bit);
234 - regmap_write(regmap, reg_addr, bit);
236 +static int mt8173_ies_smt_set(struct regmap *regmap, unsigned int pin,
237 + unsigned char align, int value, enum pin_config_param arg)
239 + if (arg == PIN_CONFIG_INPUT_ENABLE)
240 + return mtk_pconf_spec_set_ies_smt_range(regmap, mt8173_ies_set,
241 + ARRAY_SIZE(mt8173_ies_set), pin, align, value);
242 + else if (arg == PIN_CONFIG_INPUT_SCHMITT_ENABLE)
243 + return mtk_pconf_spec_set_ies_smt_range(regmap, mt8173_smt_set,
244 + ARRAY_SIZE(mt8173_smt_set), pin, align, value);
248 static const struct mtk_drv_group_desc mt8173_drv_grp[] = {
249 @@ -307,7 +320,7 @@ static const struct mtk_pinctrl_devdata mt8173_pinctrl_data = {
250 .pin_drv_grp = mt8173_pin_drv,
251 .n_pin_drv_grps = ARRAY_SIZE(mt8173_pin_drv),
252 .spec_pull_set = mt8173_spec_pull_set,
253 - .spec_ies_smt_set = spec_ies_smt_set,
254 + .spec_ies_smt_set = mt8173_ies_smt_set,
255 .dir_offset = 0x0000,
256 .pullen_offset = 0x0100,
257 .pullsel_offset = 0x0200,
258 diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
259 index 0d51145..97fe2ab 100644
260 --- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
261 +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
262 @@ -107,28 +107,38 @@ static void mtk_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
263 regmap_write(mtk_get_regmap(pctl, offset), reg_addr, bit);
266 -static void mtk_pconf_set_ies_smt(struct mtk_pinctrl *pctl, unsigned pin,
267 - int value, enum pin_config_param param)
268 +static int mtk_pconf_set_ies_smt(struct mtk_pinctrl *pctl, unsigned pin,
269 + int value, enum pin_config_param arg)
271 unsigned int reg_addr, offset;
276 + * Due to some soc are not support ies/smt config, add this special
277 + * control to handle it.
279 + if (!pctl->devdata->spec_ies_smt_set &&
280 + pctl->devdata->ies_offset == MTK_PINCTRL_NOT_SUPPORT &&
281 + arg == PIN_CONFIG_INPUT_ENABLE)
284 + if (!pctl->devdata->spec_ies_smt_set &&
285 + pctl->devdata->smt_offset == MTK_PINCTRL_NOT_SUPPORT &&
286 + arg == PIN_CONFIG_INPUT_SCHMITT_ENABLE)
290 * Due to some pins are irregular, their input enable and smt
291 - * control register are discontinuous, but they are mapping together.
292 - * So we need this special handle.
293 + * control register are discontinuous, so we need this special handle.
295 if (pctl->devdata->spec_ies_smt_set) {
296 - ret = pctl->devdata->spec_ies_smt_set(mtk_get_regmap(pctl, pin),
297 - pin, pctl->devdata->port_align, value);
300 + return pctl->devdata->spec_ies_smt_set(mtk_get_regmap(pctl, pin),
301 + pin, pctl->devdata->port_align, value, arg);
304 bit = BIT(pin & 0xf);
306 - if (param == PIN_CONFIG_INPUT_ENABLE)
307 + if (arg == PIN_CONFIG_INPUT_ENABLE)
308 offset = pctl->devdata->ies_offset;
310 offset = pctl->devdata->smt_offset;
311 @@ -139,6 +149,33 @@ static void mtk_pconf_set_ies_smt(struct mtk_pinctrl *pctl, unsigned pin,
312 reg_addr = CLR_ADDR(mtk_get_port(pctl, pin) + offset, pctl);
314 regmap_write(mtk_get_regmap(pctl, pin), reg_addr, bit);
318 +int mtk_pconf_spec_set_ies_smt_range(struct regmap *regmap,
319 + const struct mtk_pin_ies_smt_set *ies_smt_infos, unsigned int info_num,
320 + unsigned int pin, unsigned char align, int value)
322 + unsigned int i, reg_addr, bit;
324 + for (i = 0; i < info_num; i++) {
325 + if (pin >= ies_smt_infos[i].start &&
326 + pin <= ies_smt_infos[i].end) {
335 + reg_addr = ies_smt_infos[i].offset + align;
337 + reg_addr = ies_smt_infos[i].offset + (align << 1);
339 + bit = BIT(ies_smt_infos[i].bit);
340 + regmap_write(regmap, reg_addr, bit);
344 static const struct mtk_pin_drv_grp *mtk_find_pin_drv_grp_by_pin(
345 @@ -295,36 +332,37 @@ static int mtk_pconf_parse_conf(struct pinctrl_dev *pctldev,
346 unsigned int pin, enum pin_config_param param,
347 enum pin_config_param arg)
350 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
353 case PIN_CONFIG_BIAS_DISABLE:
354 - mtk_pconf_set_pull_select(pctl, pin, false, false, arg);
355 + ret = mtk_pconf_set_pull_select(pctl, pin, false, false, arg);
357 case PIN_CONFIG_BIAS_PULL_UP:
358 - mtk_pconf_set_pull_select(pctl, pin, true, true, arg);
359 + ret = mtk_pconf_set_pull_select(pctl, pin, true, true, arg);
361 case PIN_CONFIG_BIAS_PULL_DOWN:
362 - mtk_pconf_set_pull_select(pctl, pin, true, false, arg);
363 + ret = mtk_pconf_set_pull_select(pctl, pin, true, false, arg);
365 case PIN_CONFIG_INPUT_ENABLE:
366 - mtk_pconf_set_ies_smt(pctl, pin, arg, param);
367 + ret = mtk_pconf_set_ies_smt(pctl, pin, arg, param);
369 case PIN_CONFIG_OUTPUT:
370 mtk_gpio_set(pctl->chip, pin, arg);
371 - mtk_pmx_gpio_set_direction(pctldev, NULL, pin, false);
372 + ret = mtk_pmx_gpio_set_direction(pctldev, NULL, pin, false);
374 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
375 - mtk_pconf_set_ies_smt(pctl, pin, arg, param);
376 + ret = mtk_pconf_set_ies_smt(pctl, pin, arg, param);
378 case PIN_CONFIG_DRIVE_STRENGTH:
379 - mtk_pconf_set_driving(pctl, pin, arg);
380 + ret = mtk_pconf_set_driving(pctl, pin, arg);
391 static int mtk_pconf_group_get(struct pinctrl_dev *pctldev,
392 @@ -343,12 +381,14 @@ static int mtk_pconf_group_set(struct pinctrl_dev *pctldev, unsigned group,
394 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
395 struct mtk_pinctrl_group *g = &pctl->groups[group];
399 for (i = 0; i < num_configs; i++) {
400 - mtk_pconf_parse_conf(pctldev, g->pin,
401 + ret = mtk_pconf_parse_conf(pctldev, g->pin,
402 pinconf_to_config_param(configs[i]),
403 pinconf_to_config_argument(configs[i]));
407 g->config = configs[i];
409 diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.h b/drivers/pinctrl/mediatek/pinctrl-mtk-common.h
410 index 2a4b7be..c703e7d 100644
411 --- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.h
412 +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.h
415 #include <linux/pinctrl/pinctrl.h>
416 #include <linux/regmap.h>
417 +#include <linux/pinctrl/pinconf-generic.h>
419 #define NO_EINT_SUPPORT 255
420 #define MT_EDGE_SENSITIVE 0
422 #define EINT_DBNC_RST_BIT (0x1 << 1)
423 #define EINT_DBNC_SET_EN (0x1 << 0)
425 +#define MTK_PINCTRL_NOT_SUPPORT (0xffff)
427 struct mtk_desc_function {
429 unsigned char muxval;
430 @@ -143,6 +146,28 @@ struct mtk_pin_spec_pupd_set_samereg {
435 + * struct mtk_pin_ies_set - For special pins' ies and smt setting.
436 + * @start: The start pin number of those special pins.
437 + * @end: The end pin number of those special pins.
438 + * @offset: The offset of special setting register.
439 + * @bit: The bit of special setting register.
441 +struct mtk_pin_ies_smt_set {
442 + unsigned short start;
443 + unsigned short end;
444 + unsigned short offset;
448 +#define MTK_PIN_IES_SMT_SPEC(_start, _end, _offset, _bit) \
453 + .offset = _offset, \
456 struct mtk_eint_offsets {
459 @@ -208,7 +233,7 @@ struct mtk_pinctrl_devdata {
460 int (*spec_pull_set)(struct regmap *reg, unsigned int pin,
461 unsigned char align, bool isup, unsigned int arg);
462 int (*spec_ies_smt_set)(struct regmap *reg, unsigned int pin,
463 - unsigned char align, int value);
464 + unsigned char align, int value, enum pin_config_param arg);
465 unsigned int dir_offset;
466 unsigned int ies_offset;
467 unsigned int smt_offset;
468 @@ -251,4 +276,8 @@ int mtk_pctrl_spec_pull_set_samereg(struct regmap *regmap,
469 unsigned int info_num, unsigned int pin,
470 unsigned char align, bool isup, unsigned int r1r0);
472 +int mtk_pconf_spec_set_ies_smt_range(struct regmap *regmap,
473 + const struct mtk_pin_ies_smt_set *ies_smt_infos, unsigned int info_num,
474 + unsigned int pin, unsigned char align, int value);
476 #endif /* __PINCTRL_MTK_COMMON_H */