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mediatek: add support for the new MT7623 Arm SoC
[openwrt/staging/lynxis/omap.git] / target / linux / mediatek / patches / 0066-arm-mediatek-add-m7623-devicetree.patch
1 From a6bf117b5fe3acd76bbc45cc87fd80f589136e59 Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Sat, 27 Jun 2015 13:14:42 +0200
4 Subject: [PATCH 66/76] arm: mediatek: add m7623 devicetree
5
6 Signed-off-by: John Crispin <blogic@openwrt.org>
7 ---
8 arch/arm/boot/dts/Makefile | 1 +
9 arch/arm/boot/dts/mt7623-evb.dts | 162 ++++++++++++++++++
10 arch/arm/boot/dts/mt7623.dtsi | 348 ++++++++++++++++++++++++++++++++++++++
11 3 files changed, 511 insertions(+)
12 create mode 100644 arch/arm/boot/dts/mt7623-evb.dts
13 create mode 100644 arch/arm/boot/dts/mt7623.dtsi
14
15 diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
16 index 992736b..525392e 100644
17 --- a/arch/arm/boot/dts/Makefile
18 +++ b/arch/arm/boot/dts/Makefile
19 @@ -658,6 +658,7 @@ dtb-$(CONFIG_MACH_DOVE) += \
20 dtb-$(CONFIG_ARCH_MEDIATEK) += \
21 mt6589-aquaris5.dtb \
22 mt6592-evb.dtb \
23 + mt7623-evb.dtb \
24 mt8127-moose.dtb \
25 mt8135-evbp1.dtb
26 endif
27 diff --git a/arch/arm/boot/dts/mt7623-evb.dts b/arch/arm/boot/dts/mt7623-evb.dts
28 new file mode 100644
29 index 0000000..759142f
30 --- /dev/null
31 +++ b/arch/arm/boot/dts/mt7623-evb.dts
32 @@ -0,0 +1,162 @@
33 +/*
34 + * Copyright (c) 2014 MediaTek Inc.
35 + * Author: Joe.C <yingjoe.chen@mediatek.com>
36 + *
37 + * This program is free software; you can redistribute it and/or modify
38 + * it under the terms of the GNU General Public License version 2 as
39 + * published by the Free Software Foundation.
40 + *
41 + * This program is distributed in the hope that it will be useful,
42 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
43 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
44 + * GNU General Public License for more details.
45 + */
46 +
47 +/dts-v1/;
48 +#include <dt-bindings/gpio/gpio.h>
49 +#include "mt7623.dtsi"
50 +
51 +/ {
52 + model = "MediaTek MT7623 Evaluation Board";
53 + compatible = "mediatek,mt7623-evb", "mediatek,mt7623";
54 +
55 + chosen {
56 + stdout-path = &uart2;
57 + };
58 +
59 + memory {
60 + reg = <0 0x80000000 0 0x10000000>;
61 + };
62 +
63 + usb_p1_vbus: fixedregulator@0 {
64 + compatible = "regulator-fixed";
65 + regulator-name = "usb_vbus";
66 + regulator-min-microvolt = <5000000>;
67 + regulator-max-microvolt = <5000000>;
68 + gpio = <&pio 130 GPIO_ACTIVE_HIGH>;
69 + enable-active-high;
70 + };
71 +};
72 +
73 +
74 +&pio {
75 + pinctrl_uart2_default: uart2@0 {
76 + pins {
77 + pinmux = <MT7623_PIN_14_GPIO14_FUNC_URXD2>,
78 + <MT7623_PIN_15_GPIO15_FUNC_UTXD2>;
79 + };
80 + };
81 +
82 + pinctrl_i2c0_default: i2c@0 {
83 + pins {
84 + pinmux = <MT7623_PIN_75_SDA0_FUNC_SDA0>,
85 + <MT7623_PIN_76_SCL0_FUNC_SCL0>;
86 + };
87 + };
88 +
89 + pinctrl_pcie_default: pcie@0 {
90 + pins {
91 + pinmux = <MT7623_PIN_24_EINT2_FUNC_PCIE2_PERST_N>,
92 + <MT7623_PIN_208_AUD_EXT_CK1_FUNC_PCIE0_PERST_N>,
93 + <MT7623_PIN_209_AUD_EXT_CK2_FUNC_PCIE1_PERST_N>,
94 + <MT7623_PIN_250_GPIO250_FUNC_PCIE0_CLKREQ_N>,
95 + <MT7623_PIN_251_GPIO251_FUNC_PCIE0_WAKE_N>,
96 + <MT7623_PIN_252_GPIO252_FUNC_PCIE1_CLKREQ_N>,
97 + <MT7623_PIN_253_GPIO253_FUNC_PCIE1_WAKE_N>,
98 + <MT7623_PIN_254_GPIO254_FUNC_PCIE2_CLKREQ_N>,
99 + <MT7623_PIN_255_GPIO255_FUNC_PCIE2_WAKE_N>;
100 + };
101 + };
102 +
103 + pinctrl_spi_default: spi@0 {
104 + pins {
105 + pinmux = <MT7623_PIN_7_SPI1_CSN_FUNC_SPI1_CS>,
106 + <MT7623_PIN_8_SPI1_MI_FUNC_SPI1_MI>,
107 + <MT7623_PIN_9_SPI1_MO_FUNC_SPI1_MO>,
108 + <MT7623_PIN_199_SPI1_CK_FUNC_SPI1_CK>;
109 + bias-disable;
110 + };
111 + };
112 +};
113 +
114 +&thermal {
115 + status = "okay";
116 +};
117 +
118 +&uart2 {
119 + status = "okay";
120 +
121 + pinctrl-names = "default";
122 + pinctrl-0 = <&pinctrl_uart2_default>;
123 +};
124 +
125 +&i2c0 {
126 + status = "okay";
127 +
128 + pinctrl-names = "default";
129 + pinctrl-0 = <&pinctrl_i2c0_default>;
130 +};
131 +
132 +&spi {
133 + status = "okay";
134 +
135 + pinctrl-names = "default";
136 + pinctrl-0 = <&pinctrl_spi_default>;
137 +
138 + m25p80@0 {
139 + #address-cells = <1>;
140 + #size-cells = <1>;
141 + compatible = "mx25l12805d";
142 + reg = <0 0 0 0>;
143 + linux,modalias = "m25p80", "w25q128";
144 + spi-max-frequency = <10000000>;
145 +
146 + partition@0 {
147 + label = "u-boot";
148 + reg = <0x0 0x30000>;
149 + read-only;
150 + };
151 +
152 + partition@30000 {
153 + label = "u-boot-env";
154 + reg = <0x30000 0x10000>;
155 + read-only;
156 + };
157 +
158 + factory: partition@40000 {
159 + label = "factory";
160 + reg = <0x40000 0x10000>;
161 + read-only;
162 + };
163 +
164 + partition@50000 {
165 + label = "firmware";
166 + reg = <0x50000 0xfb0000>;
167 + };
168 + };
169 +};
170 +
171 +&mmc0 {
172 + status = "okay";
173 +
174 +// pinctrl-names = "default", "state_uhs";
175 +// pinctrl-0 = <&mmc0_pins_default>;
176 +// pinctrl-1 = <&mmc0_pins_uhs>;
177 + bus-width = <8>;
178 + max-frequency = <50000000>;
179 + cap-mmc-highspeed;
180 +// vmmc-supply = <&mt6397_vemc_3v3_reg>;
181 +// vqmmc-supply = <&mt6397_vio18_reg>;
182 + non-removable;
183 +};
184 +
185 +&u3phy {
186 + reg-p1-vbus-supply = <&usb_p1_vbus>;
187 +};
188 +
189 +&pcie {
190 + status = "okay";
191 +
192 + pinctrl-names = "default";
193 + pinctrl-0 = <&pinctrl_pcie_default>;
194 +};
195 diff --git a/arch/arm/boot/dts/mt7623.dtsi b/arch/arm/boot/dts/mt7623.dtsi
196 new file mode 100644
197 index 0000000..ba74ed9
198 --- /dev/null
199 +++ b/arch/arm/boot/dts/mt7623.dtsi
200 @@ -0,0 +1,348 @@
201 +/*
202 + * Copyright (c) 2014 MediaTek Inc.
203 + * Author: Joe.C <yingjoe.chen@mediatek.com>
204 + *
205 + * This program is free software; you can redistribute it and/or modify
206 + * it under the terms of the GNU General Public License version 2 as
207 + * published by the Free Software Foundation.
208 + *
209 + * This program is distributed in the hope that it will be useful,
210 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
211 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
212 + * GNU General Public License for more details.
213 + */
214 +
215 +#include <dt-bindings/clock/mt7623-clk.h>
216 +#include <dt-bindings/interrupt-controller/irq.h>
217 +#include <dt-bindings/interrupt-controller/arm-gic.h>
218 +#include <dt-bindings/pinctrl/mt7623-pinfunc.h>
219 +#include <dt-bindings/reset-controller/mt7623-resets.h>
220 +#include "skeleton64.dtsi"
221 +
222 +/ {
223 + compatible = "mediatek,mt7623";
224 + interrupt-parent = <&sysirq>;
225 +
226 + cpus {
227 + #address-cells = <1>;
228 + #size-cells = <0>;
229 + enable-method = "mediatek,mt65xx-smp";
230 + cpu@0 {
231 + device_type = "cpu";
232 + compatible = "arm,cortex-a7";
233 + reg = <0x0>;
234 + };
235 + cpu@1 {
236 + device_type = "cpu";
237 + compatible = "arm,cortex-a7";
238 + reg = <0x1>;
239 + };
240 + cpu@2 {
241 + device_type = "cpu";
242 + compatible = "arm,cortex-a7";
243 + reg = <0x2>;
244 + };
245 + cpu@3 {
246 + device_type = "cpu";
247 + compatible = "arm,cortex-a7";
248 + reg = <0x3>;
249 + };
250 +
251 + };
252 +
253 + clk26m: oscillator@0 {
254 + compatible = "fixed-clock";
255 + #clock-cells = <0>;
256 + clock-frequency = <26000000>;
257 + clock-output-names = "clk26m";
258 + };
259 +
260 + clk32k: oscillator@1 {
261 + compatible = "fixed-clock";
262 + #clock-cells = <0>;
263 + clock-frequency = <32000>;
264 + clock-output-names = "clk32k";
265 + };
266 +
267 + timer {
268 + compatible = "arm,armv7-timer";
269 + interrupt-parent = <&gic>;
270 + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) |
271 + IRQ_TYPE_LEVEL_LOW)>,
272 + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) |
273 + IRQ_TYPE_LEVEL_LOW)>,
274 + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) |
275 + IRQ_TYPE_LEVEL_LOW)>,
276 + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) |
277 + IRQ_TYPE_LEVEL_LOW)>;
278 + clock-frequency = <13000000>;
279 + arm,cpu-registers-not-fw-configured;
280 + };
281 +
282 + thermal-zones {
283 + cpu_thermal: cpu_thermal {
284 + polling-delay-passive = <1000>;
285 + polling-delay = <5000>;
286 +
287 + thermal-sensors = <&thermal 1>;
288 + };
289 + };
290 +
291 + soc {
292 + #address-cells = <2>;
293 + #size-cells = <2>;
294 + compatible = "simple-bus";
295 + ranges;
296 +
297 + topckgen: topckgen@10000000 {
298 + compatible = "mediatek,mt7623-topckgen";
299 + reg = <0 0x10000000 0 0x1000>;
300 + #clock-cells = <1>;
301 + };
302 +
303 + infracfg: infracfg@10001000 {
304 + compatible = "mediatek,mt7623-infracfg", "syscon";
305 + reg = <0 0x10001000 0 0x1000>;
306 + #clock-cells = <1>;
307 + #reset-cells = <1>;
308 + };
309 +
310 + pericfg: pericfg@10003000 {
311 + compatible = "mediatek,mt7623-pericfg", "syscon";
312 + reg = <0 0x10003000 0 0x1000>;
313 + #clock-cells = <1>;
314 + #reset-cells = <1>;
315 + };
316 +
317 + /*
318 + * Pinctrl access register at 0x10005000 through regmap.
319 + * Register 0x1000b000 is used by EINT.
320 + */
321 + pio: pinctrl@10005000 {
322 + compatible = "mediatek,mt7623-pinctrl";
323 + reg = <0 0x1000b000 0 0x1000>;
324 + mediatek,pctl-regmap = <&syscfg_pctl_a>;
325 + pins-are-numbered;
326 + gpio-controller;
327 + #gpio-cells = <2>;
328 + interrupt-controller;
329 + #interrupt-cells = <2>;
330 + interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
331 + };
332 +
333 + syscfg_pctl_a: syscfg_pctl_a@10005000 {
334 + compatible = "mediatek,mt7623-pctl-a-syscfg", "syscon";
335 + reg = <0 0x10005000 0 0x1000>;
336 + };
337 +
338 + wdt: watchdog@10007000 {
339 + compatible = "mediatek,mt7623-wdt", "mediatek,mt6589-wdt";
340 + reg = <0 0x10007000 0 0x18>;
341 + };
342 +
343 + timer: timer@10008000 {
344 + compatible = "mediatek,mt7623-timer",
345 + "mediatek,mt6577-timer";
346 + reg = <0 0x10008000 0 0x80>;
347 + interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_LOW>;
348 + clocks = <&topckgen CLK_TOP_AXI_SEL>,
349 + <&topckgen CLK_TOP_RTC_SEL>;
350 + clock-names = "system-clk", "rtc-clk";
351 + };
352 +
353 + sysirq: interrupt-controller@10200100 {
354 + compatible = "mediatek,mt7623-sysirq",
355 + "mediatek,mt6577-sysirq";
356 + interrupt-controller;
357 + #interrupt-cells = <3>;
358 + interrupt-parent = <&gic>;
359 + reg = <0 0x10200100 0 0x1c>;
360 + };
361 +
362 + apmixedsys: apmixedsys@10209000 {
363 + compatible = "mediatek,mt7623-apmixedsys";
364 + reg = <0 0x10209000 0 0x1000>;
365 + #clock-cells = <1>;
366 + };
367 +
368 + gic: interrupt-controller@10211000 {
369 + compatible = "arm,cortex-a7-gic";
370 + interrupt-controller;
371 + #interrupt-cells = <3>;
372 + interrupt-parent = <&gic>;
373 + reg = <0 0x10211000 0 0x1000>,
374 + <0 0x10212000 0 0x1000>,
375 + <0 0x10214000 0 0x2000>,
376 + <0 0x10216000 0 0x2000>;
377 + };
378 +
379 + auxadc: auxadc@11001000 {
380 + compatible = "mediatek,mt7623-auxadc", "mediatek,mt8173-auxadc";
381 + reg = <0 0x11001000 0 0x1000>;
382 + };
383 +
384 + uart0: serial@11006000 {
385 + compatible = "mediatek,mt7623-uart","mediatek,mt6577-uart";
386 + reg = <0 0x11002000 0 0x400>;
387 + interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>;
388 + clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>;
389 + clock-names = "baud", "bus";
390 +
391 + status = "disabled";
392 + };
393 +
394 + uart1: serial@11007000 {
395 + compatible = "mediatek,mt7623-uart","mediatek,mt6577-uart";
396 + reg = <0 0x11003000 0 0x400>;
397 + interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
398 + clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>;
399 + clock-names = "baud", "bus";
400 +
401 + status = "disabled";
402 + };
403 +
404 + uart2: serial@11008000 {
405 + compatible = "mediatek,mt7623-uart","mediatek,mt6577-uart";
406 + reg = <0 0x11004000 0 0x400>;
407 + interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>;
408 + clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>;
409 + clock-names = "baud", "bus";
410 +
411 + status = "disabled";
412 + };
413 +
414 + uart3: serial@11009000 {
415 + compatible = "mediatek,mt7623-uart","mediatek,mt6577-uart";
416 + reg = <0 0x11005000 0 0x400>;
417 + interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>;
418 + clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>;
419 + clock-names = "baud", "bus";
420 +
421 + status = "disabled";
422 + };
423 +
424 + spi: spi@1100a000 {
425 + compatible = "medi/THEatek,mt7623-spi", "mediatek,mt6589-spi";
426 + reg = <0 0x1100a000 0 0x1000>;
427 + interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>;
428 + clocks = <&pericfg CLK_PERI_SPI0>;
429 + clock-names = "main";
430 +
431 + status = "disabled";
432 + };
433 +
434 + thermal: thermal@1100b000 {
435 + #thermal-sensor-cells = <1>;
436 + compatible = "mediatek,mt7623-thermal", "mediatek,mt8173-thermal";
437 + reg = <0 0x1100b000 0 0x1000>;
438 + interrupts = <0 38 IRQ_TYPE_LEVEL_LOW>;
439 + clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>;
440 + clock-names = "therm", "auxadc";
441 + resets = <&pericfg MT7623_PERI_THERM_SW_RST>;
442 + reset-names = "therm";
443 + auxadc = <&auxadc>;
444 + apmixedsys = <&apmixedsys>;
445 +
446 + status = "disabled";
447 + };
448 +
449 + i2c0: i2c@11007000 {
450 + compatible = "mediatek,mt7623-i2c", "mediatek,mt6577-i2c";
451 + reg = <0 0x11007000 0 0x70>,
452 + <0 0x11000300 0 0x80>;
453 + interrupts = <0 44 IRQ_TYPE_LEVEL_LOW>;
454 + clock-frequency = <400000>;
455 + clock-div = <16>;
456 + clocks = <&pericfg CLK_PERI_I2C0>, <&pericfg CLK_PERI_AP_DMA>;
457 + clock-names = "main", "dma";
458 +
459 + status = "disabled";
460 + };
461 +
462 + mmc0: mmc@11230000 {
463 + compatible = "mediatek,mt7623-mmc",
464 + "mediatek,mt8135-mmc";
465 + reg = <0 0x11230000 0 0x1000>;
466 + interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_LOW>;
467 + clocks = <&pericfg CLK_PERI_MSDC20_1>,
468 + <&topckgen CLK_TOP_MSDC30_0_SEL>;
469 + clock-names = "source", "hclk";
470 + status = "disabled";
471 + };
472 +
473 + usb: usb30@11270000 {
474 + compatible = "mediatek,mt7623-xhci", "mediatek,mt8173-xhci", "generic-xhci";
475 + reg = <0 0x11270000 0 0x1000>;
476 + interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>;
477 + usb-phy = <&u3phy>;
478 + usb3-lpm-capable;
479 + };
480 +
481 + u3phy: usb-phy@11271000 {
482 + compatible = "mediatek,mt7623-u3phy", "mediatek,mt8173-u3phy";
483 + reg = <0 0x11271000 0 0x3000>,
484 + <0 0x11280000 0 0x20000>;
485 +// power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>;
486 +// reg-vusb33-supply = <&mt6397_vusb_reg>;
487 + clocks = <&pericfg CLK_PERI_USB0>,
488 + <&pericfg CLK_PERI_USB1>,
489 + <&topckgen CLK_TOP_USB20_SEL>;
490 +// <&apmixedsys CLK_APMIXED_REF2USB_TX>;
491 + clock-names = "wakeup_deb_p0",
492 + "wakeup_deb_p1",
493 + "sys_mac";
494 +// "u3phya_ref";
495 + disable-usb2-p1;
496 + };
497 + };
498 +
499 + ethernet@1B100000 {
500 + compatible = "mediatek,mt7623-net";
501 + interrupts = <0 200 IRQ_TYPE_LEVEL_LOW>;
502 + };
503 +
504 + pcie: pcie@1a140000 {
505 + compatible = "mediatek,mt7623-pcie";
506 + reg = <0 0x1a140000 0 0x10000>;
507 +
508 + #address-cells = <3>;
509 + #size-cells = <2>;
510 +
511 + device_type = "pci";
512 +
513 + bus-range = <0 255>;
514 + ranges = <
515 + 0x02000000 0 0 0x00000000 0x60000000 0 0x10000000 /* pci memory */
516 + 0x01000000 0 0 0x00000000 0x1A160000 0 0x00010000 /* io space */
517 + >;
518 +
519 + pcie0 {
520 + reg = <0x0000 0 0 0 0>;
521 +
522 + #address-cells = <3>;
523 + #size-cells = <2>;
524 +
525 + device_type = "pci";
526 + };
527 +
528 + pcie1 {
529 + reg = <0x0800 0 0 0 0>;
530 +
531 + #address-cells = <3>;
532 + #size-cells = <2>;
533 +
534 + device_type = "pci";
535 + };
536 +
537 + pcie2 {
538 + reg = <0x1000 0 0 0 0>;
539 +
540 + #address-cells = <3>;
541 + #size-cells = <2>;
542 +
543 + device_type = "pci";
544 + };
545 +
546 + status = "disabled";
547 + };
548 +};
549 --
550 1.7.10.4
551
lynxis staging tree for omap