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[openwrt/staging/blogic.git] / target / linux / mediatek / patches / 0071-clk.patch
1 From c3a3617a8c37b43db7ff622a31f171d3ce870173 Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Fri, 3 Jul 2015 05:44:57 +0200
4 Subject: [PATCH 71/76] clk
5
6 ---
7 drivers/clk/mediatek/clk-mt7623.c | 194 ++++++++++++++++---------------------
8 1 file changed, 83 insertions(+), 111 deletions(-)
9
10 diff --git a/drivers/clk/mediatek/clk-mt7623.c b/drivers/clk/mediatek/clk-mt7623.c
11 index 07843bb..d46b2ad 100644
12 --- a/drivers/clk/mediatek/clk-mt7623.c
13 +++ b/drivers/clk/mediatek/clk-mt7623.c
14 @@ -20,6 +20,7 @@
15
16 #include "clk-mtk.h"
17 #include "clk-gate.h"
18 +#include "clk-cpumux.h"
19
20 static DEFINE_SPINLOCK(mt7623_clk_lock);
21
22 @@ -37,18 +38,11 @@ static void mtk_clk_enable_critical(void)
23 clk_prepare_enable(mt7623_top_clk_data->clks[CLK_TOP_RTC_SEL]);
24 }
25
26 -static const struct mtk_fixed_factor root_clk_alias[] __initconst = {
27 - FACTOR(CLK_TOP_DSI0_LNTC_DSICLK, "dsi0_lntc_dsiclk", "clk_null", 1, 1),
28 - FACTOR(CLK_TOP_HDMITX_CLKDIG_CTS, "hdmitx_clkdig_cts", "clk_null", 1, 1),
29 - FACTOR(CLK_TOP_CLKPH_MCK, "clkph_mck", "clk_null", 1, 1),
30 - FACTOR(CLK_TOP_CPUM_TCK_IN, "cpum_tck_in", "clk_null", 1, 1),
31 -};
32 -
33 static const struct mtk_fixed_factor top_divs[] __initconst = {
34 - FACTOR(CLK_TOP_MAINPLL_806M, "mainpll_650m", "mainpll", 1, 2),
35 - FACTOR(CLK_TOP_MAINPLL_537P3M, "mainpll_433p3m", "mainpll", 1, 3),
36 - FACTOR(CLK_TOP_MAINPLL_322P4M, "mainpll_260m", "mainpll", 1, 5),
37 - FACTOR(CLK_TOP_MAINPLL_230P3M, "mainpll_185p6m", "mainpll", 1, 7),
38 + FACTOR(CLK_TOP_MAINPLL_650M, "mainpll_650m", "mainpll", 1, 2),
39 + FACTOR(CLK_TOP_MAINPLL_433P3M, "mainpll_433p3m", "mainpll", 1, 3),
40 + FACTOR(CLK_TOP_MAINPLL_260M, "mainpll_260m", "mainpll", 1, 5),
41 + FACTOR(CLK_TOP_MAINPLL_185P6M, "mainpll_185p6m", "mainpll", 1, 7),
42
43 FACTOR(CLK_TOP_UNIVPLL_624M, "univpll_624m", "univpll", 1, 2),
44 FACTOR(CLK_TOP_UNIVPLL_416M, "univpll_416m", "univpll", 1, 3),
45 @@ -61,13 +55,6 @@ static const struct mtk_fixed_factor top_divs[] __initconst = {
46 FACTOR(CLK_TOP_AUDPLL_D16, "audpll_d16", "audpll", 1, 16),
47 FACTOR(CLK_TOP_AUDPLL_24, "audpll_d24", "audpll", 1, 24),
48
49 - FACTOR(CLK_TOP_LVDSPLL_D2, "lvdspll_d2", "lvdspll", 1, 2),
50 - FACTOR(CLK_TOP_LVDSPLL_D4, "lvdspll_d4", "lvdspll", 1, 4),
51 - FACTOR(CLK_TOP_LVDSPLL_D8, "lvdspll_d8", "lvdspll", 1, 8),
52 - FACTOR(CLK_TOP_LVDS_ETH, "lvdspll_eth", "lvdspll", 1, 16),
53 -
54 - FACTOR(CLK_TOP_MMPLL_D2, "mmpll_d2", "mmpll", 1, 2),
55 -
56 FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll", 1, 2),
57
58 FACTOR(CLK_TOP_SYSPLL1_D2, "syspll1_d2", "mainpll_650m", 1, 2),
59 @@ -85,9 +72,6 @@ static const struct mtk_fixed_factor top_divs[] __initconst = {
60 FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "mainpll_260m", 1, 1),
61 FACTOR(CLK_TOP_SYSPLL_D7, "syspll_d7", "mainpll_185p6m", 1, 1),
62
63 - FACTOR(CLK_TOP_TVDPLL_d2, "tvdpll_d2", "tvdpll", 1, 2),
64 - FACTOR(CLK_TOP_TVDPLL_D4, "tvdpll_d4", "tvdpll", 1, 4),
65 -
66 FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univpll_624m", 1, 2),
67 FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univpll_624m", 1, 4),
68 FACTOR(CLK_TOP_UNIVPLL1_D8, "univpll1_d8", "univpll_624m", 1, 8),
69 @@ -110,9 +94,6 @@ static const struct mtk_fixed_factor top_divs[] __initconst = {
70
71 FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll_249p6m", 1, 1),
72 FACTOR(CLK_TOP_UNIVPLL_D26, "univpll_d26", "univpll_48m", 1, 1),
73 -
74 -
75 - FACTOR(CLK_TOP_MEMPLL_MCK_D4, "mempll_mck_d4", "clkph_mck", 1, 4),
76 };
77
78 static const char * const axi_parents[] __initconst = {
79 @@ -155,18 +136,6 @@ static const char * const pwm_parents[] __initconst = {
80 "univpll1_d4",
81 };
82
83 -static const char * const vdec_parents[] __initconst = {
84 - "clk26m",
85 - "syspll1_d2",
86 - "syspll_d5",
87 - "syspll1_d4",
88 - "univpll_d5",
89 - "univpll2_d2",
90 - "univpll2_d4",
91 - "msdcpll_d2",
92 - "mmpll_d2",
93 -};
94 -
95 static const char * const mfg_parents[] __initconst = {
96 "clk26m",
97 "mmpll_ck",
98 @@ -178,17 +147,6 @@ static const char * const mfg_parents[] __initconst = {
99 "univpll1_d2",
100 };
101
102 -static const char * const cam_parents[] __initconst = {
103 - "clk26m",
104 - "univpll_d26",
105 - "univpll2_d2",
106 - "syspll3_d2",
107 - "syspll3_d4",
108 - "msdcpll_d2",
109 - "mmpll_d2",
110 - "clk26m",
111 -};
112 -
113 static const char * const uart_parents[] __initconst = {
114 "clk26m",
115 "univpll2_d8",
116 @@ -277,35 +235,6 @@ static const char * const scp_parents[] __initconst = {
117 "dmpll_d4",
118 };
119
120 -static const char * const dpi0_parents[] __initconst = {
121 - "clk26m",
122 - "mipipll",
123 - "mipipll_d2",
124 - "mipipll_d4",
125 - "lvdspll",
126 - "lvdspll_d2",
127 - "lvdspll_d4",
128 - "lvdspll_d8",
129 -};
130 -
131 -static const char * const dpi1_parents[] __initconst = {
132 - "clk26m",
133 - "tvdpll",
134 - "tvdpll_d2",
135 - "tvdpll_d4",
136 -};
137 -
138 -static const char * const tve_parents[] __initconst = {
139 - "clk26m",
140 - "mipipll",
141 - "mipipll_d2",
142 - "mipipll_d4",
143 - "clk26m",
144 - "tvdpll",
145 - "tvdpll_d2",
146 - "tvdpll_d4",
147 -};
148 -
149 static const char * const apll_parents[] __initconst = {
150 "clk26m",
151 "audpll",
152 @@ -317,17 +246,6 @@ static const char * const apll_parents[] __initconst = {
153 "clk26m",
154 };
155
156 -static const char * const dpilvds_parents[] __initconst = {
157 - "clk26m",
158 - "lvdspll",
159 - "lvdspll_d2",
160 - "lvdspll_d4",
161 - "lvdspll_d8",
162 - "fpc_ck",
163 - "clk26m",
164 - "clk26m",
165 -};
166 -
167 static const char * const rtc_parents[] __initconst = {
168 "clk32k",
169 "external_32k",
170 @@ -367,9 +285,7 @@ static const struct mtk_composite top_muxes[] __initconst = {
171 0x0140, 24, 3, INVALID_MUX_GATE_BIT),
172 /* CLK_CFG_1 */
173 MUX_GATE(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x0050, 0, 2, 7),
174 - MUX_GATE(CLK_TOP_VDEC_SEL, "vdec_sel", vdec_parents, 0x0050, 8, 4, 15),
175 MUX_GATE(CLK_TOP_MFG_SEL, "mfg_sel", mfg_parents, 0x0050, 16, 3, 23),
176 - MUX_GATE(CLK_TOP_CAM_SEL, "cam_sel", cam_parents, 0x0050, 24, 3, 31),
177 /* CLK_CFG_2 */
178 MUX_GATE(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x0060, 0, 1, 7),
179 MUX_GATE(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x0060, 8, 3, 15),
180 @@ -384,12 +300,8 @@ static const struct mtk_composite top_muxes[] __initconst = {
181 /* CLK_CFG_4 */
182 MUX_GATE(CLK_TOP_PMICSPI_SEL, "pmicspi_sel", pmic_spi_parents, 0x0080, 0, 4, 7),
183 MUX_GATE(CLK_TOP_SCP_SEL, "scp_sel", scp_parents, 0x0080, 8, 2, 15),
184 - MUX_GATE(CLK_TOP_DPI0_SEL, "dpi0_sel", dpi0_parents, 0x0080, 16, 3, 23),
185 - MUX_GATE(CLK_TOP_DPI1_SEL, "dpi1_sel", dpi1_parents, 0x0080, 24, 2, 31),
186 /* CLK_CFG_5 */
187 - MUX_GATE(CLK_TOP_TVE_SEL, "tve_sel", tve_parents, 0x0090, 0, 3, 7),
188 MUX_GATE(CLK_TOP_APLL_SEL, "apll_sel", apll_parents, 0x0090, 16, 3, 23),
189 - MUX_GATE(CLK_TOP_DPILVDS_SEL, "dpilvds_sel", dpilvds_parents, 0x0090, 24, 3, 31),
190 /* CLK_CFG_6 */
191 MUX_GATE(CLK_TOP_RTC_SEL, "rtc_sel", rtc_parents, 0x00a0, 0, 2, 7),
192 MUX_GATE(CLK_TOP_NFI2X_SEL, "nfi2x_sel", nfi2x_parents, 0x00a0, 8, 3, 15),
193 @@ -428,6 +340,17 @@ static const struct mtk_gate infra_clks[] __initconst = {
194 GATE_ICG(CLK_INFRA_PMIC_WRAP, "pmic_wrap_ck", "axi_sel", 23),
195 };
196
197 +static const char * const ca7_parents[] __initconst = {
198 + "clk26m",
199 + "armpll",
200 + "mainpll",
201 + "univpll"
202 +};
203 +
204 +static struct mtk_composite cpu_muxes[] __initdata = {
205 + MUX(CLK_INFRA_CA7SEL, "infra_ca7_sel", ca7_parents, 0x0000, 2, 2),
206 +};
207 +
208 static const struct mtk_gate_regs peri0_cg_regs = {
209 .set_ofs = 0x0008,
210 .clr_ofs = 0x0010,
211 @@ -499,6 +422,29 @@ static const struct mtk_gate peri_gates[] __initconst = {
212 GATE_PERI1(CLK_PERI_NFI_PAD, "nfi_pad_ck", "axi_sel", 2),
213 };
214
215 +static const struct mtk_gate_regs hifsys_cg_regs = {
216 + .set_ofs = 0x0034,
217 + .clr_ofs = 0x0014,
218 + .sta_ofs = 0x0038,
219 +};
220 +
221 +#define GATE_HIFSYS(_id, _name, _parent, _shift) { \
222 + .id = _id, \
223 + .name = _name, \
224 + .parent_name = _parent, \
225 + .regs = &hifsys_cg_regs, \
226 + .shift = _shift, \
227 + .ops = &mtk_clk_gate_ops_setclr, \
228 + }
229 +
230 +static const struct mtk_gate hifsys_gates[] __initconst = {
231 + GATE_HIFSYS(CLK_HIFSYS_USB0_PHY, "usb0_phy_ck", "axi_sel", 21),
232 + GATE_HIFSYS(CLK_HIFSYS_USB1_PHY, "usb1_phy_ck", "axi_sel", 22),
233 + GATE_HIFSYS(CLK_HIFSYS_PCIE0, "pcie0_ck", "axi_sel", 24),
234 + GATE_HIFSYS(CLK_HIFSYS_PCIE1, "pcie1_ck", "axi_sel", 25),
235 + GATE_HIFSYS(CLK_HIFSYS_PCIE2, "pcie2_ck", "axi_sel", 26),
236 +};
237 +
238 static const char * const uart_ck_sel_parents[] __initconst = {
239 "clk26m",
240 "uart_sel",
241 @@ -525,10 +471,9 @@ static void __init mtk_topckgen_init(struct device_node *node)
242
243 mt7623_top_clk_data = clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK);
244
245 - mtk_clk_register_factors(root_clk_alias, ARRAY_SIZE(root_clk_alias), clk_data);
246 mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data);
247 mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), base,
248 - &mt7623_clk_lock, clk_data);
249 + &mt7623_clk_lock, clk_data);
250
251 r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
252 if (r)
253 @@ -547,7 +492,10 @@ static void __init mtk_infrasys_init(struct device_node *node)
254 clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK);
255
256 mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
257 - clk_data);
258 + clk_data);
259 +
260 + mtk_clk_register_cpumuxes(node, cpu_muxes, ARRAY_SIZE(cpu_muxes),
261 + clk_data);
262
263 clk_prepare_enable(clk_data->clks[CLK_INFRA_M4U]);
264
265 @@ -588,35 +536,59 @@ static void __init mtk_pericfg_init(struct device_node *node)
266 }
267 CLK_OF_DECLARE(mtk_pericfg, "mediatek,mt7623-pericfg", mtk_pericfg_init);
268
269 -#define MT7623_PLL_FMAX (2000 * MHZ)
270 -#define CON0_MT7623_RST_BAR BIT(27)
271 +static void __init mtk_hifsys_init(struct device_node *node)
272 +{
273 + struct clk_onecell_data *clk_data;
274 + int r;
275 + void __iomem *base;
276 +
277 + base = of_iomap(node, 0);
278 + if (!base) {
279 + pr_err("%s(): ioremap failed\n", __func__);
280 + return;
281 + }
282 +
283 + clk_data = mtk_alloc_clk_data(CLK_HIFSYS_NR_CLK);
284 +
285 + mtk_clk_register_gates(node, hifsys_gates, ARRAY_SIZE(hifsys_gates),
286 + clk_data);
287 +
288 + r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
289 + if (r)
290 + pr_err("%s(): could not register clock provider: %d\n",
291 + __func__, r);
292 +
293 + mtk_register_reset_controller(node, 1, 0x34);
294 +}
295 +CLK_OF_DECLARE(mtk_hifsys, "mediatek,mt7623-hifsys", mtk_hifsys_init);
296 +
297 +#define MT7623_PLL_FMAX (1300 * MHZ)
298 +#define CON0_MT7623_RST_BAR BIT(24)
299
300 -#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift) { \
301 +#define PLL(_id, _name, _con0_reg, _con1_reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pcw_shift, _pd_shift) { \
302 .id = _id, \
303 .name = _name, \
304 - .reg = _reg, \
305 + .reg = _con0_reg, \
306 .pwr_reg = _pwr_reg, \
307 .en_mask = _en_mask, \
308 .flags = _flags, \
309 .rst_bar_mask = CON0_MT7623_RST_BAR, \
310 .fmax = MT7623_PLL_FMAX, \
311 .pcwbits = _pcwbits, \
312 - .pd_reg = _pd_reg, \
313 + .pd_reg = _con0_reg, \
314 .pd_shift = _pd_shift, \
315 - .tuner_reg = _tuner_reg, \
316 - .pcw_reg = _pcw_reg, \
317 + .pcw_reg = _con1_reg, \
318 .pcw_shift = _pcw_shift, \
319 }
320
321 static const struct mtk_pll_data plls[] = {
322 - PLL(CLK_APMIXED_ARMPLL, "armpll", 0x200, 0x20c, 0x00000001, 0, 21, 0x204, 24, 0x0, 0x204, 0),
323 - PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x210, 0x21c, 0x78000001, HAVE_RST_BAR, 21, 0x214, 6, 0x0, 0x214, 0),
324 - PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x220, 0x22c, 0xFC000001, HAVE_RST_BAR, 7, 0x224, 6, 0x0, 0x224, 0),
325 - PLL(CLK_APMIXED_MMPLL, "mmpll", 0x230, 0x23c, 0x00000001, 0, 21, 0x254, 6, 0x0, 0x258, 0),
326 - PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x240, 0x24c, 0x00000001, 0, 21, 0x244, 6, 0x0, 0x244, 0),
327 - PLL(CLK_APMIXED_AUDPLL, "audpll", 0x250, 0x25c, 0x00000001, 0, 31, 0x2e8, 6, 0x2f8, 0x254, 0),
328 - PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x260, 0x26c, 0x00000001, 0, 31, 0x294, 6, 0x0, 0x298, 0),
329 - PLL(CLK_APMIXED_LVDSPLL, "lvdspll", 0x270, 0x27c, 0x00000001, 0, 21, 0x2b0, 6, 0x0, 0x2b4, 0),
330 + PLL(CLK_APMIXED_ARMPLL, "armpll", 0x200, 0x204, 0x20c, 0x00000001, 0, 21, 0, 4 ),
331 + PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x210, 0x214, 0x21c, 0x78000001, HAVE_RST_BAR, 21, 0, 4 ),
332 + PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x220, 0x224, 0x22c, 0xFC000001, HAVE_RST_BAR, 7, 14, 4 ),
333 + PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x240, 0x244, 0x24c, 0x00000001, 0, 21, 0, 4 ),
334 + PLL(CLK_APMIXED_AUDPLL, "audpll", 0x270, 0x274, 0x27c, 0x00000001, 0, 31, 0, 4 ),
335 + PLL(CLK_APMIXED_TRGPLL, "trgpll", 0x280, 0x284, 0x28c, 0x00000001, 0, 31, 0, 4 ),
336 + PLL(CLK_APMIXED_ETHPLL, "ethpll", 0x290, 0x294, 0x29c, 0x00000001, 0, 31, 0, 4 ),
337 };
338
339 static void __init mtk_apmixedsys_init(struct device_node *node)
340 --
341 1.7.10.4
342
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