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mac80211: install new firmware for ath9k-htc on target
[openwrt/staging/lynxis/omap.git] / target / linux / mediatek / patches / 0072-mfd.patch
1 From 1a4dcc30578512d687528adcf963203faee50d83 Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Fri, 3 Jul 2015 05:45:17 +0200
4 Subject: [PATCH 72/76] mfd
5
6 ---
7 drivers/mfd/mt6323-core.c | 168 +++----
8 drivers/regulator/mt6323-regulator.c | 218 ++++----
9 include/linux/mfd/mt6323/core.h | 76 +--
10 include/linux/mfd/mt6323/registers.h | 745 +++++++++++++++-------------
11 include/linux/regulator/mt6323-regulator.h | 37 ++
12 5 files changed, 636 insertions(+), 608 deletions(-)
13 create mode 100644 include/linux/regulator/mt6323-regulator.h
14
15 diff --git a/drivers/mfd/mt6323-core.c b/drivers/mfd/mt6323-core.c
16 index 012c620..9b7f5b9 100644
17 --- a/drivers/mfd/mt6323-core.c
18 +++ b/drivers/mfd/mt6323-core.c
19 @@ -18,111 +18,99 @@
20 #include <linux/of_irq.h>
21 #include <linux/regmap.h>
22 #include <linux/mfd/core.h>
23 -#include <linux/mfd/mt6397/core.h>
24 -#include <linux/mfd/mt6397/registers.h>
25 +#include <linux/mfd/mt6323/core.h>
26 +#include <linux/mfd/mt6323/registers.h>
27
28 -static const struct mfd_cell mt6397_devs[] = {
29 +static const struct mfd_cell mt6323_devs[] = {
30 {
31 - .name = "mt6397-rtc",
32 - .of_compatible = "mediatek,mt6397-rtc",
33 - }, {
34 - .name = "mt6397-regulator",
35 - .of_compatible = "mediatek,mt6397-regulator",
36 - }, {
37 - .name = "mt6397-codec",
38 - .of_compatible = "mediatek,mt6397-codec",
39 - }, {
40 - .name = "mt6397-clk",
41 - .of_compatible = "mediatek,mt6397-clk",
42 - }, {
43 - .name = "mediatek-mt6397-pinctrl",
44 - .of_compatible = "mediatek,mt6397-pinctrl",
45 + .name = "mt6323-regulator",
46 + .of_compatible = "mediatek,mt6323-regulator",
47 },
48 };
49
50 -static void mt6397_irq_lock(struct irq_data *data)
51 +static void mt6323_irq_lock(struct irq_data *data)
52 {
53 - struct mt6397_chip *mt6397 = irq_get_chip_data(data->irq);
54 + struct mt6323_chip *mt6323 = irq_get_chip_data(data->irq);
55
56 - mutex_lock(&mt6397->irqlock);
57 + mutex_lock(&mt6323->irqlock);
58 }
59
60 -static void mt6397_irq_sync_unlock(struct irq_data *data)
61 +static void mt6323_irq_sync_unlock(struct irq_data *data)
62 {
63 - struct mt6397_chip *mt6397 = irq_get_chip_data(data->irq);
64 + struct mt6323_chip *mt6323 = irq_get_chip_data(data->irq);
65
66 - regmap_write(mt6397->regmap, MT6397_INT_CON0, mt6397->irq_masks_cur[0]);
67 - regmap_write(mt6397->regmap, MT6397_INT_CON1, mt6397->irq_masks_cur[1]);
68 + regmap_write(mt6323->regmap, MT6323_INT_CON0, mt6323->irq_masks_cur[0]);
69 + regmap_write(mt6323->regmap, MT6323_INT_CON1, mt6323->irq_masks_cur[1]);
70
71 - mutex_unlock(&mt6397->irqlock);
72 + mutex_unlock(&mt6323->irqlock);
73 }
74
75 -static void mt6397_irq_disable(struct irq_data *data)
76 +static void mt6323_irq_disable(struct irq_data *data)
77 {
78 - struct mt6397_chip *mt6397 = irq_get_chip_data(data->irq);
79 + struct mt6323_chip *mt6323 = irq_get_chip_data(data->irq);
80 int shift = data->hwirq & 0xf;
81 int reg = data->hwirq >> 4;
82
83 - mt6397->irq_masks_cur[reg] &= ~BIT(shift);
84 + mt6323->irq_masks_cur[reg] &= ~BIT(shift);
85 }
86
87 -static void mt6397_irq_enable(struct irq_data *data)
88 +static void mt6323_irq_enable(struct irq_data *data)
89 {
90 - struct mt6397_chip *mt6397 = irq_get_chip_data(data->irq);
91 + struct mt6323_chip *mt6323 = irq_get_chip_data(data->irq);
92 int shift = data->hwirq & 0xf;
93 int reg = data->hwirq >> 4;
94
95 - mt6397->irq_masks_cur[reg] |= BIT(shift);
96 + mt6323->irq_masks_cur[reg] |= BIT(shift);
97 }
98
99 -static struct irq_chip mt6397_irq_chip = {
100 - .name = "mt6397-irq",
101 - .irq_bus_lock = mt6397_irq_lock,
102 - .irq_bus_sync_unlock = mt6397_irq_sync_unlock,
103 - .irq_enable = mt6397_irq_enable,
104 - .irq_disable = mt6397_irq_disable,
105 +static struct irq_chip mt6323_irq_chip = {
106 + .name = "mt6323-irq",
107 + .irq_bus_lock = mt6323_irq_lock,
108 + .irq_bus_sync_unlock = mt6323_irq_sync_unlock,
109 + .irq_enable = mt6323_irq_enable,
110 + .irq_disable = mt6323_irq_disable,
111 };
112
113 -static void mt6397_irq_handle_reg(struct mt6397_chip *mt6397, int reg,
114 +static void mt6323_irq_handle_reg(struct mt6323_chip *mt6323, int reg,
115 int irqbase)
116 {
117 unsigned int status;
118 int i, irq, ret;
119
120 - ret = regmap_read(mt6397->regmap, reg, &status);
121 + ret = regmap_read(mt6323->regmap, reg, &status);
122 if (ret) {
123 - dev_err(mt6397->dev, "Failed to read irq status: %d\n", ret);
124 + dev_err(mt6323->dev, "Failed to read irq status: %d\n", ret);
125 return;
126 }
127
128 for (i = 0; i < 16; i++) {
129 if (status & BIT(i)) {
130 - irq = irq_find_mapping(mt6397->irq_domain, irqbase + i);
131 + irq = irq_find_mapping(mt6323->irq_domain, irqbase + i);
132 if (irq)
133 handle_nested_irq(irq);
134 }
135 }
136
137 - regmap_write(mt6397->regmap, reg, status);
138 + regmap_write(mt6323->regmap, reg, status);
139 }
140
141 -static irqreturn_t mt6397_irq_thread(int irq, void *data)
142 +static irqreturn_t mt6323_irq_thread(int irq, void *data)
143 {
144 - struct mt6397_chip *mt6397 = data;
145 + struct mt6323_chip *mt6323 = data;
146
147 - mt6397_irq_handle_reg(mt6397, MT6397_INT_STATUS0, 0);
148 - mt6397_irq_handle_reg(mt6397, MT6397_INT_STATUS1, 16);
149 + mt6323_irq_handle_reg(mt6323, MT6323_INT_STATUS0, 0);
150 + mt6323_irq_handle_reg(mt6323, MT6323_INT_STATUS1, 16);
151
152 return IRQ_HANDLED;
153 }
154
155 -static int mt6397_irq_domain_map(struct irq_domain *d, unsigned int irq,
156 +static int mt6323_irq_domain_map(struct irq_domain *d, unsigned int irq,
157 irq_hw_number_t hw)
158 {
159 - struct mt6397_chip *mt6397 = d->host_data;
160 + struct mt6323_chip *mt6323 = d->host_data;
161
162 - irq_set_chip_data(irq, mt6397);
163 - irq_set_chip_and_handler(irq, &mt6397_irq_chip, handle_level_irq);
164 + irq_set_chip_data(irq, mt6323);
165 + irq_set_chip_and_handler(irq, &mt6323_irq_chip, handle_level_irq);
166 irq_set_nested_thread(irq, 1);
167 #ifdef CONFIG_ARM
168 set_irq_flags(irq, IRQF_VALID);
169 @@ -133,98 +121,98 @@ static int mt6397_irq_domain_map(struct irq_domain *d, unsigned int irq,
170 return 0;
171 }
172
173 -static struct irq_domain_ops mt6397_irq_domain_ops = {
174 - .map = mt6397_irq_domain_map,
175 +static struct irq_domain_ops mt6323_irq_domain_ops = {
176 + .map = mt6323_irq_domain_map,
177 };
178
179 -static int mt6397_irq_init(struct mt6397_chip *mt6397)
180 +static int mt6323_irq_init(struct mt6323_chip *mt6323)
181 {
182 int ret;
183
184 - mutex_init(&mt6397->irqlock);
185 + mutex_init(&mt6323->irqlock);
186
187 /* Mask all interrupt sources */
188 - regmap_write(mt6397->regmap, MT6397_INT_CON0, 0x0);
189 - regmap_write(mt6397->regmap, MT6397_INT_CON1, 0x0);
190 + regmap_write(mt6323->regmap, MT6323_INT_CON0, 0x0);
191 + regmap_write(mt6323->regmap, MT6323_INT_CON1, 0x0);
192
193 - mt6397->irq_domain = irq_domain_add_linear(mt6397->dev->of_node,
194 - MT6397_IRQ_NR, &mt6397_irq_domain_ops, mt6397);
195 - if (!mt6397->irq_domain) {
196 - dev_err(mt6397->dev, "could not create irq domain\n");
197 + mt6323->irq_domain = irq_domain_add_linear(mt6323->dev->of_node,
198 + MT6323_IRQ_NR, &mt6323_irq_domain_ops, mt6323);
199 + if (!mt6323->irq_domain) {
200 + dev_err(mt6323->dev, "could not create irq domain\n");
201 return -ENOMEM;
202 }
203
204 - ret = devm_request_threaded_irq(mt6397->dev, mt6397->irq, NULL,
205 - mt6397_irq_thread, IRQF_ONESHOT, "mt6397-pmic", mt6397);
206 + ret = devm_request_threaded_irq(mt6323->dev, mt6323->irq, NULL,
207 + mt6323_irq_thread, IRQF_ONESHOT, "mt6323-pmic", mt6323);
208 if (ret) {
209 - dev_err(mt6397->dev, "failed to register irq=%d; err: %d\n",
210 - mt6397->irq, ret);
211 + dev_err(mt6323->dev, "failed to register irq=%d; err: %d\n",
212 + mt6323->irq, ret);
213 return ret;
214 }
215
216 return 0;
217 }
218
219 -static int mt6397_probe(struct platform_device *pdev)
220 +static int mt6323_probe(struct platform_device *pdev)
221 {
222 int ret;
223 - struct mt6397_chip *mt6397;
224 + struct mt6323_chip *mt6323;
225
226 - mt6397 = devm_kzalloc(&pdev->dev, sizeof(*mt6397), GFP_KERNEL);
227 - if (!mt6397)
228 + mt6323 = devm_kzalloc(&pdev->dev, sizeof(*mt6323), GFP_KERNEL);
229 + if (!mt6323)
230 return -ENOMEM;
231
232 - mt6397->dev = &pdev->dev;
233 + mt6323->dev = &pdev->dev;
234 /*
235 - * mt6397 MFD is child device of soc pmic wrapper.
236 + * mt6323 MFD is child device of soc pmic wrapper.
237 * Regmap is set from its parent.
238 */
239 - mt6397->regmap = dev_get_regmap(pdev->dev.parent, NULL);
240 - if (!mt6397->regmap)
241 + mt6323->regmap = dev_get_regmap(pdev->dev.parent, NULL);
242 + if (!mt6323->regmap)
243 return -ENODEV;
244
245 - platform_set_drvdata(pdev, mt6397);
246 + platform_set_drvdata(pdev, mt6323);
247
248 - mt6397->irq = platform_get_irq(pdev, 0);
249 - if (mt6397->irq > 0) {
250 - ret = mt6397_irq_init(mt6397);
251 + mt6323->irq = platform_get_irq(pdev, 0);
252 + if (mt6323->irq > 0) {
253 + ret = mt6323_irq_init(mt6323);
254 if (ret)
255 return ret;
256 }
257
258 - ret = mfd_add_devices(&pdev->dev, -1, mt6397_devs,
259 - ARRAY_SIZE(mt6397_devs), NULL, 0, NULL);
260 + ret = mfd_add_devices(&pdev->dev, -1, mt6323_devs,
261 + ARRAY_SIZE(mt6323_devs), NULL, 0, NULL);
262 if (ret)
263 dev_err(&pdev->dev, "failed to add child devices: %d\n", ret);
264
265 return ret;
266 }
267
268 -static int mt6397_remove(struct platform_device *pdev)
269 +static int mt6323_remove(struct platform_device *pdev)
270 {
271 mfd_remove_devices(&pdev->dev);
272
273 return 0;
274 }
275
276 -static const struct of_device_id mt6397_of_match[] = {
277 - { .compatible = "mediatek,mt6397" },
278 +static const struct of_device_id mt6323_of_match[] = {
279 + { .compatible = "mediatek,mt6323" },
280 { }
281 };
282 -MODULE_DEVICE_TABLE(of, mt6397_of_match);
283 +MODULE_DEVICE_TABLE(of, mt6323_of_match);
284
285 -static struct platform_driver mt6397_driver = {
286 - .probe = mt6397_probe,
287 - .remove = mt6397_remove,
288 +static struct platform_driver mt6323_driver = {
289 + .probe = mt6323_probe,
290 + .remove = mt6323_remove,
291 .driver = {
292 - .name = "mt6397",
293 - .of_match_table = of_match_ptr(mt6397_of_match),
294 + .name = "mt6323",
295 + .of_match_table = of_match_ptr(mt6323_of_match),
296 },
297 };
298
299 -module_platform_driver(mt6397_driver);
300 +module_platform_driver(mt6323_driver);
301
302 MODULE_AUTHOR("Flora Fu, MediaTek");
303 -MODULE_DESCRIPTION("Driver for MediaTek MT6397 PMIC");
304 +MODULE_DESCRIPTION("Driver for MediaTek MT6323 PMIC");
305 MODULE_LICENSE("GPL");
306 -MODULE_ALIAS("platform:mt6397");
307 +MODULE_ALIAS("platform:mt6323");
308 diff --git a/drivers/regulator/mt6323-regulator.c b/drivers/regulator/mt6323-regulator.c
309 index a5b2f47..f5e3f67 100644
310 --- a/drivers/regulator/mt6323-regulator.c
311 +++ b/drivers/regulator/mt6323-regulator.c
312 @@ -16,15 +16,15 @@
313 #include <linux/of.h>
314 #include <linux/platform_device.h>
315 #include <linux/regmap.h>
316 -#include <linux/mfd/mt6397/core.h>
317 -#include <linux/mfd/mt6397/registers.h>
318 +#include <linux/mfd/mt6323/core.h>
319 +#include <linux/mfd/mt6323/registers.h>
320 #include <linux/regulator/driver.h>
321 #include <linux/regulator/machine.h>
322 -#include <linux/regulator/mt6397-regulator.h>
323 +#include <linux/regulator/mt6323-regulator.h>
324 #include <linux/regulator/of_regulator.h>
325
326 /*
327 - * MT6397 regulators' information
328 + * MT6323 regulators' information
329 *
330 * @desc: standard fields of regulator description.
331 * @qi: Mask for query enable signal status of regulators
332 @@ -32,7 +32,7 @@
333 * @vselctrl_reg: Register for controlling the buck control mode.
334 * @vselctrl_mask: Mask for query buck's voltage control mode.
335 */
336 -struct mt6397_regulator_info {
337 +struct mt6323_regulator_info {
338 struct regulator_desc desc;
339 u32 qi;
340 u32 vselon_reg;
341 @@ -40,15 +40,15 @@ struct mt6397_regulator_info {
342 u32 vselctrl_mask;
343 };
344
345 -#define MT6397_BUCK(match, vreg, min, max, step, volt_ranges, enreg, \
346 +#define MT6323_BUCK(match, vreg, min, max, step, volt_ranges, enreg, \
347 vosel, vosel_mask, voselon, vosel_ctrl) \
348 -[MT6397_ID_##vreg] = { \
349 +[MT6323_ID_##vreg] = { \
350 .desc = { \
351 .name = #vreg, \
352 .of_match = of_match_ptr(match), \
353 - .ops = &mt6397_volt_range_ops, \
354 + .ops = &mt6323_volt_range_ops, \
355 .type = REGULATOR_VOLTAGE, \
356 - .id = MT6397_ID_##vreg, \
357 + .id = MT6323_ID_##vreg, \
358 .owner = THIS_MODULE, \
359 .n_voltages = (max - min)/step + 1, \
360 .linear_ranges = volt_ranges, \
361 @@ -64,15 +64,15 @@ struct mt6397_regulator_info {
362 .vselctrl_mask = BIT(1), \
363 }
364
365 -#define MT6397_LDO(match, vreg, ldo_volt_table, enreg, enbit, vosel, \
366 +#define MT6323_LDO(match, vreg, ldo_volt_table, enreg, enbit, vosel, \
367 vosel_mask) \
368 -[MT6397_ID_##vreg] = { \
369 +[MT6323_ID_##vreg] = { \
370 .desc = { \
371 .name = #vreg, \
372 .of_match = of_match_ptr(match), \
373 - .ops = &mt6397_volt_table_ops, \
374 + .ops = &mt6323_volt_table_ops, \
375 .type = REGULATOR_VOLTAGE, \
376 - .id = MT6397_ID_##vreg, \
377 + .id = MT6323_ID_##vreg, \
378 .owner = THIS_MODULE, \
379 .n_voltages = ARRAY_SIZE(ldo_volt_table), \
380 .volt_table = ldo_volt_table, \
381 @@ -84,14 +84,14 @@ struct mt6397_regulator_info {
382 .qi = BIT(15), \
383 }
384
385 -#define MT6397_REG_FIXED(match, vreg, enreg, enbit, volt) \
386 -[MT6397_ID_##vreg] = { \
387 +#define MT6323_REG_FIXED(match, vreg, enreg, enbit, volt) \
388 +[MT6323_ID_##vreg] = { \
389 .desc = { \
390 .name = #vreg, \
391 .of_match = of_match_ptr(match), \
392 - .ops = &mt6397_volt_fixed_ops, \
393 + .ops = &mt6323_volt_fixed_ops, \
394 .type = REGULATOR_VOLTAGE, \
395 - .id = MT6397_ID_##vreg, \
396 + .id = MT6323_ID_##vreg, \
397 .owner = THIS_MODULE, \
398 .n_voltages = 1, \
399 .enable_reg = enreg, \
400 @@ -106,50 +106,34 @@ static const struct regulator_linear_range buck_volt_range1[] = {
401 };
402
403 static const struct regulator_linear_range buck_volt_range2[] = {
404 - REGULATOR_LINEAR_RANGE(800000, 0, 0x7f, 6250),
405 + REGULATOR_LINEAR_RANGE(1400000, 0, 0x7f, 12500),
406 };
407
408 static const struct regulator_linear_range buck_volt_range3[] = {
409 - REGULATOR_LINEAR_RANGE(1500000, 0, 0x1f, 20000),
410 + REGULATOR_LINEAR_RANGE(500000, 0, 0x3f, 50000),
411 };
412
413 static const u32 ldo_volt_table1[] = {
414 - 1500000, 1800000, 2500000, 2800000,
415 + 1800000, 3300000,
416 };
417
418 static const u32 ldo_volt_table2[] = {
419 - 1800000, 3300000,
420 + 3000000, 3300000,
421 };
422
423 static const u32 ldo_volt_table3[] = {
424 - 3000000, 3300000,
425 + 1200000, 1300000, 1500000, 1800000, 2000000, 2800000, 3000000,
426 };
427
428 static const u32 ldo_volt_table4[] = {
429 - 1220000, 1300000, 1500000, 1800000, 2500000, 2800000, 3000000, 3300000,
430 -};
431 -
432 -static const u32 ldo_volt_table5[] = {
433 1200000, 1300000, 1500000, 1800000, 2500000, 2800000, 3000000, 3300000,
434 };
435
436 -static const u32 ldo_volt_table5_v2[] = {
437 - 1200000, 1000000, 1500000, 1800000, 2500000, 2800000, 3000000, 3300000,
438 -};
439 -
440 -static const u32 ldo_volt_table6[] = {
441 - 1200000, 1300000, 1500000, 1800000, 2500000, 2800000, 3000000, 2000000,
442 -};
443 -
444 -static const u32 ldo_volt_table7[] = {
445 - 1300000, 1500000, 1800000, 2000000, 2500000, 2800000, 3000000, 3300000,
446 -};
447 -
448 -static int mt6397_get_status(struct regulator_dev *rdev)
449 +static int mt6323_get_status(struct regulator_dev *rdev)
450 {
451 int ret;
452 u32 regval;
453 - struct mt6397_regulator_info *info = rdev_get_drvdata(rdev);
454 + struct mt6323_regulator_info *info = rdev_get_drvdata(rdev);
455
456 ret = regmap_read(rdev->regmap, info->desc.enable_reg, &regval);
457 if (ret != 0) {
458 @@ -160,7 +144,7 @@ static int mt6397_get_status(struct regulator_dev *rdev)
459 return (regval & info->qi) ? REGULATOR_STATUS_ON : REGULATOR_STATUS_OFF;
460 }
461
462 -static struct regulator_ops mt6397_volt_range_ops = {
463 +static struct regulator_ops mt6323_volt_range_ops = {
464 .list_voltage = regulator_list_voltage_linear_range,
465 .map_voltage = regulator_map_voltage_linear_range,
466 .set_voltage_sel = regulator_set_voltage_sel_regmap,
467 @@ -169,10 +153,10 @@ static struct regulator_ops mt6397_volt_range_ops = {
468 .enable = regulator_enable_regmap,
469 .disable = regulator_disable_regmap,
470 .is_enabled = regulator_is_enabled_regmap,
471 - .get_status = mt6397_get_status,
472 + .get_status = mt6323_get_status,
473 };
474
475 -static struct regulator_ops mt6397_volt_table_ops = {
476 +static struct regulator_ops mt6323_volt_table_ops = {
477 .list_voltage = regulator_list_voltage_table,
478 .map_voltage = regulator_map_voltage_iterate,
479 .set_voltage_sel = regulator_set_voltage_sel_regmap,
480 @@ -181,90 +165,68 @@ static struct regulator_ops mt6397_volt_table_ops = {
481 .enable = regulator_enable_regmap,
482 .disable = regulator_disable_regmap,
483 .is_enabled = regulator_is_enabled_regmap,
484 - .get_status = mt6397_get_status,
485 + .get_status = mt6323_get_status,
486 };
487
488 -static struct regulator_ops mt6397_volt_fixed_ops = {
489 +static struct regulator_ops mt6323_volt_fixed_ops = {
490 .list_voltage = regulator_list_voltage_linear,
491 .enable = regulator_enable_regmap,
492 .disable = regulator_disable_regmap,
493 .is_enabled = regulator_is_enabled_regmap,
494 - .get_status = mt6397_get_status,
495 + .get_status = mt6323_get_status,
496 };
497
498 -/* The array is indexed by id(MT6397_ID_XXX) */
499 -static struct mt6397_regulator_info mt6397_regulators[] = {
500 - MT6397_BUCK("buck_vpca15", VPCA15, 700000, 1493750, 6250,
501 - buck_volt_range1, MT6397_VCA15_CON7, MT6397_VCA15_CON9, 0x7f,
502 - MT6397_VCA15_CON10, MT6397_VCA15_CON5),
503 - MT6397_BUCK("buck_vpca7", VPCA7, 700000, 1493750, 6250,
504 - buck_volt_range1, MT6397_VPCA7_CON7, MT6397_VPCA7_CON9, 0x7f,
505 - MT6397_VPCA7_CON10, MT6397_VPCA7_CON5),
506 - MT6397_BUCK("buck_vsramca15", VSRAMCA15, 700000, 1493750, 6250,
507 - buck_volt_range1, MT6397_VSRMCA15_CON7, MT6397_VSRMCA15_CON9,
508 - 0x7f, MT6397_VSRMCA15_CON10, MT6397_VSRMCA15_CON5),
509 - MT6397_BUCK("buck_vsramca7", VSRAMCA7, 700000, 1493750, 6250,
510 - buck_volt_range1, MT6397_VSRMCA7_CON7, MT6397_VSRMCA7_CON9,
511 - 0x7f, MT6397_VSRMCA7_CON10, MT6397_VSRMCA7_CON5),
512 - MT6397_BUCK("buck_vcore", VCORE, 700000, 1493750, 6250,
513 - buck_volt_range1, MT6397_VCORE_CON7, MT6397_VCORE_CON9, 0x7f,
514 - MT6397_VCORE_CON10, MT6397_VCORE_CON5),
515 - MT6397_BUCK("buck_vgpu", VGPU, 700000, 1493750, 6250, buck_volt_range1,
516 - MT6397_VGPU_CON7, MT6397_VGPU_CON9, 0x7f,
517 - MT6397_VGPU_CON10, MT6397_VGPU_CON5),
518 - MT6397_BUCK("buck_vdrm", VDRM, 800000, 1593750, 6250, buck_volt_range2,
519 - MT6397_VDRM_CON7, MT6397_VDRM_CON9, 0x7f,
520 - MT6397_VDRM_CON10, MT6397_VDRM_CON5),
521 - MT6397_BUCK("buck_vio18", VIO18, 1500000, 2120000, 20000,
522 - buck_volt_range3, MT6397_VIO18_CON7, MT6397_VIO18_CON9, 0x1f,
523 - MT6397_VIO18_CON10, MT6397_VIO18_CON5),
524 - MT6397_REG_FIXED("ldo_vtcxo", VTCXO, MT6397_ANALDO_CON0, 10, 2800000),
525 - MT6397_REG_FIXED("ldo_va28", VA28, MT6397_ANALDO_CON1, 14, 2800000),
526 - MT6397_LDO("ldo_vcama", VCAMA, ldo_volt_table1,
527 - MT6397_ANALDO_CON2, 15, MT6397_ANALDO_CON6, 0xC0),
528 - MT6397_REG_FIXED("ldo_vio28", VIO28, MT6397_DIGLDO_CON0, 14, 2800000),
529 - MT6397_REG_FIXED("ldo_vusb", VUSB, MT6397_DIGLDO_CON1, 14, 3300000),
530 - MT6397_LDO("ldo_vmc", VMC, ldo_volt_table2,
531 - MT6397_DIGLDO_CON2, 12, MT6397_DIGLDO_CON29, 0x10),
532 - MT6397_LDO("ldo_vmch", VMCH, ldo_volt_table3,
533 - MT6397_DIGLDO_CON3, 14, MT6397_DIGLDO_CON17, 0x80),
534 - MT6397_LDO("ldo_vemc3v3", VEMC3V3, ldo_volt_table3,
535 - MT6397_DIGLDO_CON4, 14, MT6397_DIGLDO_CON18, 0x10),
536 - MT6397_LDO("ldo_vgp1", VGP1, ldo_volt_table4,
537 - MT6397_DIGLDO_CON5, 15, MT6397_DIGLDO_CON19, 0xE0),
538 - MT6397_LDO("ldo_vgp2", VGP2, ldo_volt_table5,
539 - MT6397_DIGLDO_CON6, 15, MT6397_DIGLDO_CON20, 0xE0),
540 - MT6397_LDO("ldo_vgp3", VGP3, ldo_volt_table5,
541 - MT6397_DIGLDO_CON7, 15, MT6397_DIGLDO_CON21, 0xE0),
542 - MT6397_LDO("ldo_vgp4", VGP4, ldo_volt_table5,
543 - MT6397_DIGLDO_CON8, 15, MT6397_DIGLDO_CON22, 0xE0),
544 - MT6397_LDO("ldo_vgp5", VGP5, ldo_volt_table6,
545 - MT6397_DIGLDO_CON9, 15, MT6397_DIGLDO_CON23, 0xE0),
546 - MT6397_LDO("ldo_vgp6", VGP6, ldo_volt_table5,
547 - MT6397_DIGLDO_CON10, 15, MT6397_DIGLDO_CON33, 0xE0),
548 - MT6397_LDO("ldo_vibr", VIBR, ldo_volt_table7,
549 - MT6397_DIGLDO_CON24, 15, MT6397_DIGLDO_CON25, 0xE00),
550 +/* The array is indexed by id(MT6323_ID_XXX) */
551 +static struct mt6323_regulator_info mt6323_regulators[] = {
552 + /* buck */
553 + MT6323_BUCK("buck_vproc", VPROC, 700000, 1493750, 6250,
554 + buck_volt_range1, MT6323_VPROC_CON7, MT6323_VPROC_CON9, 0x7f,
555 + MT6323_VPROC_CON10, MT6323_VPROC_CON5),
556 + MT6323_BUCK("buck_vsys", VSYS, 1400000, 3000000, 12500,
557 + buck_volt_range2, MT6323_VSYS_CON7, MT6323_VSYS_CON9,
558 + 0x7f, MT6323_VSYS_CON10, MT6323_VSYS_CON5),
559 + MT6323_BUCK("buck_vpa", VPA, 500000, 3650000, 50000,
560 + buck_volt_range3, MT6323_VPA_CON7, MT6323_VPA_CON9, 0x7f,
561 + MT6323_VPA_CON10, MT6323_VPA_CON5),
562 +
563 + /* analog */
564 + MT6323_REG_FIXED("ldo_vtcxo", VTCXO, MT6323_ANALDO_CON1, 10, 2800000),
565 + MT6323_REG_FIXED("ldo_va", VA, MT6323_ANALDO_CON2, 14, 2800000),
566 + MT6323_REG_FIXED("ldo_vcn28", VCN28, MT6323_ANALDO_CON19, 12, 2800000),
567 + MT6323_REG_FIXED("ldo_vcn33", VCN33, MT6323_ANALDO_CON21, 12, 3300000),
568 +
569 + /* digital */
570 + MT6323_REG_FIXED("ldo_vio28", VIO28, MT6323_DIGLDO_CON0, 15, 2800000),
571 + MT6323_REG_FIXED("ldo_vusb", VUSB, MT6323_DIGLDO_CON2, 15, 3300000),
572 + MT6323_LDO("ldo_vmc", VMC, ldo_volt_table1,
573 + MT6323_DIGLDO_CON3, 12, MT6323_DIGLDO_CON24, 0x10),
574 + MT6323_LDO("ldo_vmch", VMCH, ldo_volt_table2,
575 + MT6323_DIGLDO_CON5, 14, MT6323_DIGLDO_CON26, 0x80),
576 + MT6323_LDO("ldo_vgp1", VGP1, ldo_volt_table3,
577 + MT6323_DIGLDO_CON7, 15, MT6323_DIGLDO_CON28, 0xE0),
578 + MT6323_LDO("ldo_vgp2", VGP2, ldo_volt_table4,
579 + MT6323_DIGLDO_CON8, 15, MT6323_DIGLDO_CON29, 0xE0),
580 };
581
582 -static int mt6397_set_buck_vosel_reg(struct platform_device *pdev)
583 +static int mt6323_set_buck_vosel_reg(struct platform_device *pdev)
584 {
585 - struct mt6397_chip *mt6397 = dev_get_drvdata(pdev->dev.parent);
586 + struct mt6323_chip *mt6323 = dev_get_drvdata(pdev->dev.parent);
587 int i;
588 u32 regval;
589
590 - for (i = 0; i < MT6397_MAX_REGULATOR; i++) {
591 - if (mt6397_regulators[i].vselctrl_reg) {
592 - if (regmap_read(mt6397->regmap,
593 - mt6397_regulators[i].vselctrl_reg,
594 + for (i = 0; i < MT6323_MAX_REGULATOR; i++) {
595 + if (mt6323_regulators[i].vselctrl_reg) {
596 + if (regmap_read(mt6323->regmap,
597 + mt6323_regulators[i].vselctrl_reg,
598 &regval) < 0) {
599 dev_err(&pdev->dev,
600 "Failed to read buck ctrl\n");
601 return -EIO;
602 }
603
604 - if (regval & mt6397_regulators[i].vselctrl_mask) {
605 - mt6397_regulators[i].desc.vsel_reg =
606 - mt6397_regulators[i].vselon_reg;
607 + if (regval & mt6323_regulators[i].vselctrl_mask) {
608 + mt6323_regulators[i].desc.vsel_reg =
609 + mt6323_regulators[i].vselon_reg;
610 }
611 }
612 }
613 @@ -272,44 +234,34 @@ static int mt6397_set_buck_vosel_reg(struct platform_device *pdev)
614 return 0;
615 }
616
617 -static int mt6397_regulator_probe(struct platform_device *pdev)
618 +static int mt6323_regulator_probe(struct platform_device *pdev)
619 {
620 - struct mt6397_chip *mt6397 = dev_get_drvdata(pdev->dev.parent);
621 + struct mt6323_chip *mt6323 = dev_get_drvdata(pdev->dev.parent);
622 struct regulator_config config = {};
623 struct regulator_dev *rdev;
624 int i;
625 - u32 reg_value, version;
626 + u32 reg_value;
627
628 /* Query buck controller to select activated voltage register part */
629 - if (mt6397_set_buck_vosel_reg(pdev))
630 + if (mt6323_set_buck_vosel_reg(pdev))
631 return -EIO;
632
633 /* Read PMIC chip revision to update constraints and voltage table */
634 - if (regmap_read(mt6397->regmap, MT6397_CID, &reg_value) < 0) {
635 + if (regmap_read(mt6323->regmap, MT6323_CID, &reg_value) < 0) {
636 dev_err(&pdev->dev, "Failed to read Chip ID\n");
637 return -EIO;
638 }
639 dev_info(&pdev->dev, "Chip ID = 0x%x\n", reg_value);
640
641 - version = (reg_value & 0xFF);
642 - switch (version) {
643 - case MT6397_REGULATOR_ID91:
644 - mt6397_regulators[MT6397_ID_VGP2].desc.volt_table =
645 - ldo_volt_table5_v2;
646 - break;
647 - default:
648 - break;
649 - }
650 -
651 - for (i = 0; i < MT6397_MAX_REGULATOR; i++) {
652 + for (i = 0; i < MT6323_MAX_REGULATOR; i++) {
653 config.dev = &pdev->dev;
654 - config.driver_data = &mt6397_regulators[i];
655 - config.regmap = mt6397->regmap;
656 + config.driver_data = &mt6323_regulators[i];
657 + config.regmap = mt6323->regmap;
658 rdev = devm_regulator_register(&pdev->dev,
659 - &mt6397_regulators[i].desc, &config);
660 + &mt6323_regulators[i].desc, &config);
661 if (IS_ERR(rdev)) {
662 dev_err(&pdev->dev, "failed to register %s\n",
663 - mt6397_regulators[i].desc.name);
664 + mt6323_regulators[i].desc.name);
665 return PTR_ERR(rdev);
666 }
667 }
668 @@ -317,16 +269,16 @@ static int mt6397_regulator_probe(struct platform_device *pdev)
669 return 0;
670 }
671
672 -static struct platform_driver mt6397_regulator_driver = {
673 +static struct platform_driver mt6323_regulator_driver = {
674 .driver = {
675 - .name = "mt6397-regulator",
676 + .name = "mt6323-regulator",
677 },
678 - .probe = mt6397_regulator_probe,
679 + .probe = mt6323_regulator_probe,
680 };
681
682 -module_platform_driver(mt6397_regulator_driver);
683 +module_platform_driver(mt6323_regulator_driver);
684
685 MODULE_AUTHOR("Flora Fu <flora.fu@mediatek.com>");
686 -MODULE_DESCRIPTION("Regulator Driver for MediaTek MT6397 PMIC");
687 +MODULE_DESCRIPTION("Regulator Driver for MediaTek MT6323 PMIC");
688 MODULE_LICENSE("GPL");
689 -MODULE_ALIAS("platform:mt6397-regulator");
690 +MODULE_ALIAS("platform:mt6323-regulator");
691 diff --git a/include/linux/mfd/mt6323/core.h b/include/linux/mfd/mt6323/core.h
692 index cf5265b..5bb2d32 100644
693 --- a/include/linux/mfd/mt6323/core.h
694 +++ b/include/linux/mfd/mt6323/core.h
695 @@ -12,46 +12,46 @@
696 * GNU General Public License for more details.
697 */
698
699 -#ifndef __MFD_MT6397_CORE_H__
700 -#define __MFD_MT6397_CORE_H__
701 +#ifndef __MFD_MT6323_CORE_H__
702 +#define __MFD_MT6323_CORE_H__
703
704 -enum mt6397_irq_numbers {
705 - MT6397_IRQ_SPKL_AB = 0,
706 - MT6397_IRQ_SPKR_AB,
707 - MT6397_IRQ_SPKL,
708 - MT6397_IRQ_SPKR,
709 - MT6397_IRQ_BAT_L,
710 - MT6397_IRQ_BAT_H,
711 - MT6397_IRQ_FG_BAT_L,
712 - MT6397_IRQ_FG_BAT_H,
713 - MT6397_IRQ_WATCHDOG,
714 - MT6397_IRQ_PWRKEY,
715 - MT6397_IRQ_THR_L,
716 - MT6397_IRQ_THR_H,
717 - MT6397_IRQ_VBATON_UNDET,
718 - MT6397_IRQ_BVALID_DET,
719 - MT6397_IRQ_CHRDET,
720 - MT6397_IRQ_OV,
721 - MT6397_IRQ_LDO,
722 - MT6397_IRQ_HOMEKEY,
723 - MT6397_IRQ_ACCDET,
724 - MT6397_IRQ_AUDIO,
725 - MT6397_IRQ_RTC,
726 - MT6397_IRQ_PWRKEY_RSTB,
727 - MT6397_IRQ_HDMI_SIFM,
728 - MT6397_IRQ_HDMI_CEC,
729 - MT6397_IRQ_VCA15,
730 - MT6397_IRQ_VSRMCA15,
731 - MT6397_IRQ_VCORE,
732 - MT6397_IRQ_VGPU,
733 - MT6397_IRQ_VIO18,
734 - MT6397_IRQ_VPCA7,
735 - MT6397_IRQ_VSRMCA7,
736 - MT6397_IRQ_VDRM,
737 - MT6397_IRQ_NR,
738 +enum mt6323_irq_numbers {
739 + MT6323_IRQ_SPKL_AB = 0,
740 + MT6323_IRQ_SPKR_AB,
741 + MT6323_IRQ_SPKL,
742 + MT6323_IRQ_SPKR,
743 + MT6323_IRQ_BAT_L,
744 + MT6323_IRQ_BAT_H,
745 + MT6323_IRQ_FG_BAT_L,
746 + MT6323_IRQ_FG_BAT_H,
747 + MT6323_IRQ_WATCHDOG,
748 + MT6323_IRQ_PWRKEY,
749 + MT6323_IRQ_THR_L,
750 + MT6323_IRQ_THR_H,
751 + MT6323_IRQ_VBATON_UNDET,
752 + MT6323_IRQ_BVALID_DET,
753 + MT6323_IRQ_CHRDET,
754 + MT6323_IRQ_OV,
755 + MT6323_IRQ_LDO,
756 + MT6323_IRQ_HOMEKEY,
757 + MT6323_IRQ_ACCDET,
758 + MT6323_IRQ_AUDIO,
759 + MT6323_IRQ_RTC,
760 + MT6323_IRQ_PWRKEY_RSTB,
761 + MT6323_IRQ_HDMI_SIFM,
762 + MT6323_IRQ_HDMI_CEC,
763 + MT6323_IRQ_VCA15,
764 + MT6323_IRQ_VSRMCA15,
765 + MT6323_IRQ_VCORE,
766 + MT6323_IRQ_VGPU,
767 + MT6323_IRQ_VIO18,
768 + MT6323_IRQ_VPCA7,
769 + MT6323_IRQ_VSRMCA7,
770 + MT6323_IRQ_VDRM,
771 + MT6323_IRQ_NR,
772 };
773
774 -struct mt6397_chip {
775 +struct mt6323_chip {
776 struct device *dev;
777 struct regmap *regmap;
778 int irq;
779 @@ -61,4 +61,4 @@ struct mt6397_chip {
780 u16 irq_masks_cache[2];
781 };
782
783 -#endif /* __MFD_MT6397_CORE_H__ */
784 +#endif /* __MFD_MT6323_CORE_H__ */
785 diff --git a/include/linux/mfd/mt6323/registers.h b/include/linux/mfd/mt6323/registers.h
786 index f23a0a6..4ee5e1f0 100644
787 --- a/include/linux/mfd/mt6323/registers.h
788 +++ b/include/linux/mfd/mt6323/registers.h
789 @@ -1,6 +1,5 @@
790 /*
791 - * Copyright (c) 2014 MediaTek Inc.
792 - * Author: Flora Fu, MediaTek
793 + * Copyright (c) 2015 - John Crispin <blogic@openwrt.org>
794 *
795 * This program is free software; you can redistribute it and/or modify
796 * it under the terms of the GNU General Public License version 2 as
797 @@ -12,351 +11,403 @@
798 * GNU General Public License for more details.
799 */
800
801 -#ifndef __MFD_MT6397_REGISTERS_H__
802 -#define __MFD_MT6397_REGISTERS_H__
803 +#ifndef __MFD_MT6323_REGISTERS_H__
804 +#define __MFD_MT6323_REGISTERS_H__
805
806 /* PMIC Registers */
807 -#define MT6397_CID 0x0100
808 -#define MT6397_TOP_CKPDN 0x0102
809 -#define MT6397_TOP_CKPDN_SET 0x0104
810 -#define MT6397_TOP_CKPDN_CLR 0x0106
811 -#define MT6397_TOP_CKPDN2 0x0108
812 -#define MT6397_TOP_CKPDN2_SET 0x010A
813 -#define MT6397_TOP_CKPDN2_CLR 0x010C
814 -#define MT6397_TOP_GPIO_CKPDN 0x010E
815 -#define MT6397_TOP_RST_CON 0x0114
816 -#define MT6397_WRP_CKPDN 0x011A
817 -#define MT6397_WRP_RST_CON 0x0120
818 -#define MT6397_TOP_RST_MISC 0x0126
819 -#define MT6397_TOP_CKCON1 0x0128
820 -#define MT6397_TOP_CKCON2 0x012A
821 -#define MT6397_TOP_CKTST1 0x012C
822 -#define MT6397_TOP_CKTST2 0x012E
823 -#define MT6397_OC_DEG_EN 0x0130
824 -#define MT6397_OC_CTL0 0x0132
825 -#define MT6397_OC_CTL1 0x0134
826 -#define MT6397_OC_CTL2 0x0136
827 -#define MT6397_INT_RSV 0x0138
828 -#define MT6397_TEST_CON0 0x013A
829 -#define MT6397_TEST_CON1 0x013C
830 -#define MT6397_STATUS0 0x013E
831 -#define MT6397_STATUS1 0x0140
832 -#define MT6397_PGSTATUS 0x0142
833 -#define MT6397_CHRSTATUS 0x0144
834 -#define MT6397_OCSTATUS0 0x0146
835 -#define MT6397_OCSTATUS1 0x0148
836 -#define MT6397_OCSTATUS2 0x014A
837 -#define MT6397_HDMI_PAD_IE 0x014C
838 -#define MT6397_TEST_OUT_L 0x014E
839 -#define MT6397_TEST_OUT_H 0x0150
840 -#define MT6397_TDSEL_CON 0x0152
841 -#define MT6397_RDSEL_CON 0x0154
842 -#define MT6397_GPIO_SMT_CON0 0x0156
843 -#define MT6397_GPIO_SMT_CON1 0x0158
844 -#define MT6397_GPIO_SMT_CON2 0x015A
845 -#define MT6397_GPIO_SMT_CON3 0x015C
846 -#define MT6397_DRV_CON0 0x015E
847 -#define MT6397_DRV_CON1 0x0160
848 -#define MT6397_DRV_CON2 0x0162
849 -#define MT6397_DRV_CON3 0x0164
850 -#define MT6397_DRV_CON4 0x0166
851 -#define MT6397_DRV_CON5 0x0168
852 -#define MT6397_DRV_CON6 0x016A
853 -#define MT6397_DRV_CON7 0x016C
854 -#define MT6397_DRV_CON8 0x016E
855 -#define MT6397_DRV_CON9 0x0170
856 -#define MT6397_DRV_CON10 0x0172
857 -#define MT6397_DRV_CON11 0x0174
858 -#define MT6397_DRV_CON12 0x0176
859 -#define MT6397_INT_CON0 0x0178
860 -#define MT6397_INT_CON1 0x017E
861 -#define MT6397_INT_STATUS0 0x0184
862 -#define MT6397_INT_STATUS1 0x0186
863 -#define MT6397_FQMTR_CON0 0x0188
864 -#define MT6397_FQMTR_CON1 0x018A
865 -#define MT6397_FQMTR_CON2 0x018C
866 -#define MT6397_EFUSE_DOUT_0_15 0x01C4
867 -#define MT6397_EFUSE_DOUT_16_31 0x01C6
868 -#define MT6397_EFUSE_DOUT_32_47 0x01C8
869 -#define MT6397_EFUSE_DOUT_48_63 0x01CA
870 -#define MT6397_SPI_CON 0x01CC
871 -#define MT6397_TOP_CKPDN3 0x01CE
872 -#define MT6397_TOP_CKCON3 0x01D4
873 -#define MT6397_EFUSE_DOUT_64_79 0x01D6
874 -#define MT6397_EFUSE_DOUT_80_95 0x01D8
875 -#define MT6397_EFUSE_DOUT_96_111 0x01DA
876 -#define MT6397_EFUSE_DOUT_112_127 0x01DC
877 -#define MT6397_EFUSE_DOUT_128_143 0x01DE
878 -#define MT6397_EFUSE_DOUT_144_159 0x01E0
879 -#define MT6397_EFUSE_DOUT_160_175 0x01E2
880 -#define MT6397_EFUSE_DOUT_176_191 0x01E4
881 -#define MT6397_EFUSE_DOUT_192_207 0x01E6
882 -#define MT6397_EFUSE_DOUT_208_223 0x01E8
883 -#define MT6397_EFUSE_DOUT_224_239 0x01EA
884 -#define MT6397_EFUSE_DOUT_240_255 0x01EC
885 -#define MT6397_EFUSE_DOUT_256_271 0x01EE
886 -#define MT6397_EFUSE_DOUT_272_287 0x01F0
887 -#define MT6397_EFUSE_DOUT_288_300 0x01F2
888 -#define MT6397_EFUSE_DOUT_304_319 0x01F4
889 -#define MT6397_BUCK_CON0 0x0200
890 -#define MT6397_BUCK_CON1 0x0202
891 -#define MT6397_BUCK_CON2 0x0204
892 -#define MT6397_BUCK_CON3 0x0206
893 -#define MT6397_BUCK_CON4 0x0208
894 -#define MT6397_BUCK_CON5 0x020A
895 -#define MT6397_BUCK_CON6 0x020C
896 -#define MT6397_BUCK_CON7 0x020E
897 -#define MT6397_BUCK_CON8 0x0210
898 -#define MT6397_BUCK_CON9 0x0212
899 -#define MT6397_VCA15_CON0 0x0214
900 -#define MT6397_VCA15_CON1 0x0216
901 -#define MT6397_VCA15_CON2 0x0218
902 -#define MT6397_VCA15_CON3 0x021A
903 -#define MT6397_VCA15_CON4 0x021C
904 -#define MT6397_VCA15_CON5 0x021E
905 -#define MT6397_VCA15_CON6 0x0220
906 -#define MT6397_VCA15_CON7 0x0222
907 -#define MT6397_VCA15_CON8 0x0224
908 -#define MT6397_VCA15_CON9 0x0226
909 -#define MT6397_VCA15_CON10 0x0228
910 -#define MT6397_VCA15_CON11 0x022A
911 -#define MT6397_VCA15_CON12 0x022C
912 -#define MT6397_VCA15_CON13 0x022E
913 -#define MT6397_VCA15_CON14 0x0230
914 -#define MT6397_VCA15_CON15 0x0232
915 -#define MT6397_VCA15_CON16 0x0234
916 -#define MT6397_VCA15_CON17 0x0236
917 -#define MT6397_VCA15_CON18 0x0238
918 -#define MT6397_VSRMCA15_CON0 0x023A
919 -#define MT6397_VSRMCA15_CON1 0x023C
920 -#define MT6397_VSRMCA15_CON2 0x023E
921 -#define MT6397_VSRMCA15_CON3 0x0240
922 -#define MT6397_VSRMCA15_CON4 0x0242
923 -#define MT6397_VSRMCA15_CON5 0x0244
924 -#define MT6397_VSRMCA15_CON6 0x0246
925 -#define MT6397_VSRMCA15_CON7 0x0248
926 -#define MT6397_VSRMCA15_CON8 0x024A
927 -#define MT6397_VSRMCA15_CON9 0x024C
928 -#define MT6397_VSRMCA15_CON10 0x024E
929 -#define MT6397_VSRMCA15_CON11 0x0250
930 -#define MT6397_VSRMCA15_CON12 0x0252
931 -#define MT6397_VSRMCA15_CON13 0x0254
932 -#define MT6397_VSRMCA15_CON14 0x0256
933 -#define MT6397_VSRMCA15_CON15 0x0258
934 -#define MT6397_VSRMCA15_CON16 0x025A
935 -#define MT6397_VSRMCA15_CON17 0x025C
936 -#define MT6397_VSRMCA15_CON18 0x025E
937 -#define MT6397_VSRMCA15_CON19 0x0260
938 -#define MT6397_VSRMCA15_CON20 0x0262
939 -#define MT6397_VSRMCA15_CON21 0x0264
940 -#define MT6397_VCORE_CON0 0x0266
941 -#define MT6397_VCORE_CON1 0x0268
942 -#define MT6397_VCORE_CON2 0x026A
943 -#define MT6397_VCORE_CON3 0x026C
944 -#define MT6397_VCORE_CON4 0x026E
945 -#define MT6397_VCORE_CON5 0x0270
946 -#define MT6397_VCORE_CON6 0x0272
947 -#define MT6397_VCORE_CON7 0x0274
948 -#define MT6397_VCORE_CON8 0x0276
949 -#define MT6397_VCORE_CON9 0x0278
950 -#define MT6397_VCORE_CON10 0x027A
951 -#define MT6397_VCORE_CON11 0x027C
952 -#define MT6397_VCORE_CON12 0x027E
953 -#define MT6397_VCORE_CON13 0x0280
954 -#define MT6397_VCORE_CON14 0x0282
955 -#define MT6397_VCORE_CON15 0x0284
956 -#define MT6397_VCORE_CON16 0x0286
957 -#define MT6397_VCORE_CON17 0x0288
958 -#define MT6397_VCORE_CON18 0x028A
959 -#define MT6397_VGPU_CON0 0x028C
960 -#define MT6397_VGPU_CON1 0x028E
961 -#define MT6397_VGPU_CON2 0x0290
962 -#define MT6397_VGPU_CON3 0x0292
963 -#define MT6397_VGPU_CON4 0x0294
964 -#define MT6397_VGPU_CON5 0x0296
965 -#define MT6397_VGPU_CON6 0x0298
966 -#define MT6397_VGPU_CON7 0x029A
967 -#define MT6397_VGPU_CON8 0x029C
968 -#define MT6397_VGPU_CON9 0x029E
969 -#define MT6397_VGPU_CON10 0x02A0
970 -#define MT6397_VGPU_CON11 0x02A2
971 -#define MT6397_VGPU_CON12 0x02A4
972 -#define MT6397_VGPU_CON13 0x02A6
973 -#define MT6397_VGPU_CON14 0x02A8
974 -#define MT6397_VGPU_CON15 0x02AA
975 -#define MT6397_VGPU_CON16 0x02AC
976 -#define MT6397_VGPU_CON17 0x02AE
977 -#define MT6397_VGPU_CON18 0x02B0
978 -#define MT6397_VIO18_CON0 0x0300
979 -#define MT6397_VIO18_CON1 0x0302
980 -#define MT6397_VIO18_CON2 0x0304
981 -#define MT6397_VIO18_CON3 0x0306
982 -#define MT6397_VIO18_CON4 0x0308
983 -#define MT6397_VIO18_CON5 0x030A
984 -#define MT6397_VIO18_CON6 0x030C
985 -#define MT6397_VIO18_CON7 0x030E
986 -#define MT6397_VIO18_CON8 0x0310
987 -#define MT6397_VIO18_CON9 0x0312
988 -#define MT6397_VIO18_CON10 0x0314
989 -#define MT6397_VIO18_CON11 0x0316
990 -#define MT6397_VIO18_CON12 0x0318
991 -#define MT6397_VIO18_CON13 0x031A
992 -#define MT6397_VIO18_CON14 0x031C
993 -#define MT6397_VIO18_CON15 0x031E
994 -#define MT6397_VIO18_CON16 0x0320
995 -#define MT6397_VIO18_CON17 0x0322
996 -#define MT6397_VIO18_CON18 0x0324
997 -#define MT6397_VPCA7_CON0 0x0326
998 -#define MT6397_VPCA7_CON1 0x0328
999 -#define MT6397_VPCA7_CON2 0x032A
1000 -#define MT6397_VPCA7_CON3 0x032C
1001 -#define MT6397_VPCA7_CON4 0x032E
1002 -#define MT6397_VPCA7_CON5 0x0330
1003 -#define MT6397_VPCA7_CON6 0x0332
1004 -#define MT6397_VPCA7_CON7 0x0334
1005 -#define MT6397_VPCA7_CON8 0x0336
1006 -#define MT6397_VPCA7_CON9 0x0338
1007 -#define MT6397_VPCA7_CON10 0x033A
1008 -#define MT6397_VPCA7_CON11 0x033C
1009 -#define MT6397_VPCA7_CON12 0x033E
1010 -#define MT6397_VPCA7_CON13 0x0340
1011 -#define MT6397_VPCA7_CON14 0x0342
1012 -#define MT6397_VPCA7_CON15 0x0344
1013 -#define MT6397_VPCA7_CON16 0x0346
1014 -#define MT6397_VPCA7_CON17 0x0348
1015 -#define MT6397_VPCA7_CON18 0x034A
1016 -#define MT6397_VSRMCA7_CON0 0x034C
1017 -#define MT6397_VSRMCA7_CON1 0x034E
1018 -#define MT6397_VSRMCA7_CON2 0x0350
1019 -#define MT6397_VSRMCA7_CON3 0x0352
1020 -#define MT6397_VSRMCA7_CON4 0x0354
1021 -#define MT6397_VSRMCA7_CON5 0x0356
1022 -#define MT6397_VSRMCA7_CON6 0x0358
1023 -#define MT6397_VSRMCA7_CON7 0x035A
1024 -#define MT6397_VSRMCA7_CON8 0x035C
1025 -#define MT6397_VSRMCA7_CON9 0x035E
1026 -#define MT6397_VSRMCA7_CON10 0x0360
1027 -#define MT6397_VSRMCA7_CON11 0x0362
1028 -#define MT6397_VSRMCA7_CON12 0x0364
1029 -#define MT6397_VSRMCA7_CON13 0x0366
1030 -#define MT6397_VSRMCA7_CON14 0x0368
1031 -#define MT6397_VSRMCA7_CON15 0x036A
1032 -#define MT6397_VSRMCA7_CON16 0x036C
1033 -#define MT6397_VSRMCA7_CON17 0x036E
1034 -#define MT6397_VSRMCA7_CON18 0x0370
1035 -#define MT6397_VSRMCA7_CON19 0x0372
1036 -#define MT6397_VSRMCA7_CON20 0x0374
1037 -#define MT6397_VSRMCA7_CON21 0x0376
1038 -#define MT6397_VDRM_CON0 0x0378
1039 -#define MT6397_VDRM_CON1 0x037A
1040 -#define MT6397_VDRM_CON2 0x037C
1041 -#define MT6397_VDRM_CON3 0x037E
1042 -#define MT6397_VDRM_CON4 0x0380
1043 -#define MT6397_VDRM_CON5 0x0382
1044 -#define MT6397_VDRM_CON6 0x0384
1045 -#define MT6397_VDRM_CON7 0x0386
1046 -#define MT6397_VDRM_CON8 0x0388
1047 -#define MT6397_VDRM_CON9 0x038A
1048 -#define MT6397_VDRM_CON10 0x038C
1049 -#define MT6397_VDRM_CON11 0x038E
1050 -#define MT6397_VDRM_CON12 0x0390
1051 -#define MT6397_VDRM_CON13 0x0392
1052 -#define MT6397_VDRM_CON14 0x0394
1053 -#define MT6397_VDRM_CON15 0x0396
1054 -#define MT6397_VDRM_CON16 0x0398
1055 -#define MT6397_VDRM_CON17 0x039A
1056 -#define MT6397_VDRM_CON18 0x039C
1057 -#define MT6397_BUCK_K_CON0 0x039E
1058 -#define MT6397_BUCK_K_CON1 0x03A0
1059 -#define MT6397_ANALDO_CON0 0x0400
1060 -#define MT6397_ANALDO_CON1 0x0402
1061 -#define MT6397_ANALDO_CON2 0x0404
1062 -#define MT6397_ANALDO_CON3 0x0406
1063 -#define MT6397_ANALDO_CON4 0x0408
1064 -#define MT6397_ANALDO_CON5 0x040A
1065 -#define MT6397_ANALDO_CON6 0x040C
1066 -#define MT6397_ANALDO_CON7 0x040E
1067 -#define MT6397_DIGLDO_CON0 0x0410
1068 -#define MT6397_DIGLDO_CON1 0x0412
1069 -#define MT6397_DIGLDO_CON2 0x0414
1070 -#define MT6397_DIGLDO_CON3 0x0416
1071 -#define MT6397_DIGLDO_CON4 0x0418
1072 -#define MT6397_DIGLDO_CON5 0x041A
1073 -#define MT6397_DIGLDO_CON6 0x041C
1074 -#define MT6397_DIGLDO_CON7 0x041E
1075 -#define MT6397_DIGLDO_CON8 0x0420
1076 -#define MT6397_DIGLDO_CON9 0x0422
1077 -#define MT6397_DIGLDO_CON10 0x0424
1078 -#define MT6397_DIGLDO_CON11 0x0426
1079 -#define MT6397_DIGLDO_CON12 0x0428
1080 -#define MT6397_DIGLDO_CON13 0x042A
1081 -#define MT6397_DIGLDO_CON14 0x042C
1082 -#define MT6397_DIGLDO_CON15 0x042E
1083 -#define MT6397_DIGLDO_CON16 0x0430
1084 -#define MT6397_DIGLDO_CON17 0x0432
1085 -#define MT6397_DIGLDO_CON18 0x0434
1086 -#define MT6397_DIGLDO_CON19 0x0436
1087 -#define MT6397_DIGLDO_CON20 0x0438
1088 -#define MT6397_DIGLDO_CON21 0x043A
1089 -#define MT6397_DIGLDO_CON22 0x043C
1090 -#define MT6397_DIGLDO_CON23 0x043E
1091 -#define MT6397_DIGLDO_CON24 0x0440
1092 -#define MT6397_DIGLDO_CON25 0x0442
1093 -#define MT6397_DIGLDO_CON26 0x0444
1094 -#define MT6397_DIGLDO_CON27 0x0446
1095 -#define MT6397_DIGLDO_CON28 0x0448
1096 -#define MT6397_DIGLDO_CON29 0x044A
1097 -#define MT6397_DIGLDO_CON30 0x044C
1098 -#define MT6397_DIGLDO_CON31 0x044E
1099 -#define MT6397_DIGLDO_CON32 0x0450
1100 -#define MT6397_DIGLDO_CON33 0x045A
1101 -#define MT6397_SPK_CON0 0x0600
1102 -#define MT6397_SPK_CON1 0x0602
1103 -#define MT6397_SPK_CON2 0x0604
1104 -#define MT6397_SPK_CON3 0x0606
1105 -#define MT6397_SPK_CON4 0x0608
1106 -#define MT6397_SPK_CON5 0x060A
1107 -#define MT6397_SPK_CON6 0x060C
1108 -#define MT6397_SPK_CON7 0x060E
1109 -#define MT6397_SPK_CON8 0x0610
1110 -#define MT6397_SPK_CON9 0x0612
1111 -#define MT6397_SPK_CON10 0x0614
1112 -#define MT6397_SPK_CON11 0x0616
1113 -#define MT6397_AUDDAC_CON0 0x0700
1114 -#define MT6397_AUDBUF_CFG0 0x0702
1115 -#define MT6397_AUDBUF_CFG1 0x0704
1116 -#define MT6397_AUDBUF_CFG2 0x0706
1117 -#define MT6397_AUDBUF_CFG3 0x0708
1118 -#define MT6397_AUDBUF_CFG4 0x070A
1119 -#define MT6397_IBIASDIST_CFG0 0x070C
1120 -#define MT6397_AUDACCDEPOP_CFG0 0x070E
1121 -#define MT6397_AUD_IV_CFG0 0x0710
1122 -#define MT6397_AUDCLKGEN_CFG0 0x0712
1123 -#define MT6397_AUDLDO_CFG0 0x0714
1124 -#define MT6397_AUDLDO_CFG1 0x0716
1125 -#define MT6397_AUDNVREGGLB_CFG0 0x0718
1126 -#define MT6397_AUD_NCP0 0x071A
1127 -#define MT6397_AUDPREAMP_CON0 0x071C
1128 -#define MT6397_AUDADC_CON0 0x071E
1129 -#define MT6397_AUDADC_CON1 0x0720
1130 -#define MT6397_AUDADC_CON2 0x0722
1131 -#define MT6397_AUDADC_CON3 0x0724
1132 -#define MT6397_AUDADC_CON4 0x0726
1133 -#define MT6397_AUDADC_CON5 0x0728
1134 -#define MT6397_AUDADC_CON6 0x072A
1135 -#define MT6397_AUDDIGMI_CON0 0x072C
1136 -#define MT6397_AUDLSBUF_CON0 0x072E
1137 -#define MT6397_AUDLSBUF_CON1 0x0730
1138 -#define MT6397_AUDENCSPARE_CON0 0x0732
1139 -#define MT6397_AUDENCCLKSQ_CON0 0x0734
1140 -#define MT6397_AUDPREAMPGAIN_CON0 0x0736
1141 -#define MT6397_ZCD_CON0 0x0738
1142 -#define MT6397_ZCD_CON1 0x073A
1143 -#define MT6397_ZCD_CON2 0x073C
1144 -#define MT6397_ZCD_CON3 0x073E
1145 -#define MT6397_ZCD_CON4 0x0740
1146 -#define MT6397_ZCD_CON5 0x0742
1147 -#define MT6397_NCP_CLKDIV_CON0 0x0744
1148 -#define MT6397_NCP_CLKDIV_CON1 0x0746
1149 +#define MT6323_CHR_CON0 0x0000
1150 +#define MT6323_CHR_CON1 0x0002
1151 +#define MT6323_CHR_CON2 0x0004
1152 +#define MT6323_CHR_CON3 0x0006
1153 +#define MT6323_CHR_CON4 0x0008
1154 +#define MT6323_CHR_CON5 0x000A
1155 +#define MT6323_CHR_CON6 0x000C
1156 +#define MT6323_CHR_CON7 0x000E
1157 +#define MT6323_CHR_CON8 0x0010
1158 +#define MT6323_CHR_CON9 0x0012
1159 +#define MT6323_CHR_CON10 0x0014
1160 +#define MT6323_CHR_CON11 0x0016
1161 +#define MT6323_CHR_CON12 0x0018
1162 +#define MT6323_CHR_CON13 0x001A
1163 +#define MT6323_CHR_CON14 0x001C
1164 +#define MT6323_CHR_CON15 0x001E
1165 +#define MT6323_CHR_CON16 0x0020
1166 +#define MT6323_CHR_CON17 0x0022
1167 +#define MT6323_CHR_CON18 0x0024
1168 +#define MT6323_CHR_CON19 0x0026
1169 +#define MT6323_CHR_CON20 0x0028
1170 +#define MT6323_CHR_CON21 0x002A
1171 +#define MT6323_CHR_CON22 0x002C
1172 +#define MT6323_CHR_CON23 0x002E
1173 +#define MT6323_CHR_CON24 0x0030
1174 +#define MT6323_CHR_CON25 0x0032
1175 +#define MT6323_CHR_CON26 0x0034
1176 +#define MT6323_CHR_CON27 0x0036
1177 +#define MT6323_CHR_CON28 0x0038
1178 +#define MT6323_CHR_CON29 0x003A
1179 +#define MT6323_STRUP_CON0 0x003C
1180 +#define MT6323_STRUP_CON2 0x003E
1181 +#define MT6323_STRUP_CON3 0x0040
1182 +#define MT6323_STRUP_CON4 0x0042
1183 +#define MT6323_STRUP_CON5 0x0044
1184 +#define MT6323_STRUP_CON6 0x0046
1185 +#define MT6323_STRUP_CON7 0x0048
1186 +#define MT6323_STRUP_CON8 0x004A
1187 +#define MT6323_STRUP_CON9 0x004C
1188 +#define MT6323_STRUP_CON10 0x004E
1189 +#define MT6323_STRUP_CON11 0x0050
1190 +#define MT6323_SPK_CON0 0x0052
1191 +#define MT6323_SPK_CON1 0x0054
1192 +#define MT6323_SPK_CON2 0x0056
1193 +#define MT6323_SPK_CON6 0x005E
1194 +#define MT6323_SPK_CON7 0x0060
1195 +#define MT6323_SPK_CON8 0x0062
1196 +#define MT6323_SPK_CON9 0x0064
1197 +#define MT6323_SPK_CON10 0x0066
1198 +#define MT6323_SPK_CON11 0x0068
1199 +#define MT6323_SPK_CON12 0x006A
1200 +#define MT6323_CID 0x0100
1201 +#define MT6323_TOP_CKPDN0 0x0102
1202 +#define MT6323_TOP_CKPDN0_SET 0x0104
1203 +#define MT6323_TOP_CKPDN0_CLR 0x0106
1204 +#define MT6323_TOP_CKPDN1 0x0108
1205 +#define MT6323_TOP_CKPDN1_SET 0x010A
1206 +#define MT6323_TOP_CKPDN1_CLR 0x010C
1207 +#define MT6323_TOP_CKPDN2 0x010E
1208 +#define MT6323_TOP_CKPDN2_SET 0x0110
1209 +#define MT6323_TOP_CKPDN2_CLR 0x0112
1210 +#define MT6323_TOP_RST_CON 0x0114
1211 +#define MT6323_TOP_RST_CON_SET 0x0116
1212 +#define MT6323_TOP_RST_CON_CLR 0x0118
1213 +#define MT6323_TOP_RST_MISC 0x011A
1214 +#define MT6323_TOP_RST_MISC_SET 0x011C
1215 +#define MT6323_TOP_RST_MISC_CLR 0x011E
1216 +#define MT6323_TOP_CKCON0 0x0120
1217 +#define MT6323_TOP_CKCON0_SET 0x0122
1218 +#define MT6323_TOP_CKCON0_CLR 0x0124
1219 +#define MT6323_TOP_CKCON1 0x0126
1220 +#define MT6323_TOP_CKCON1_SET 0x0128
1221 +#define MT6323_TOP_CKCON1_CLR 0x012A
1222 +#define MT6323_TOP_CKTST0 0x012C
1223 +#define MT6323_TOP_CKTST1 0x012E
1224 +#define MT6323_TOP_CKTST2 0x0130
1225 +#define MT6323_TEST_OUT 0x0132
1226 +#define MT6323_TEST_CON0 0x0134
1227 +#define MT6323_TEST_CON1 0x0136
1228 +#define MT6323_EN_STATUS0 0x0138
1229 +#define MT6323_EN_STATUS1 0x013A
1230 +#define MT6323_OCSTATUS0 0x013C
1231 +#define MT6323_OCSTATUS1 0x013E
1232 +#define MT6323_PGSTATUS 0x0140
1233 +#define MT6323_CHRSTATUS 0x0142
1234 +#define MT6323_TDSEL_CON 0x0144
1235 +#define MT6323_RDSEL_CON 0x0146
1236 +#define MT6323_SMT_CON0 0x0148
1237 +#define MT6323_SMT_CON1 0x014A
1238 +#define MT6323_SMT_CON2 0x014C
1239 +#define MT6323_SMT_CON3 0x014E
1240 +#define MT6323_SMT_CON4 0x0150
1241 +#define MT6323_DRV_CON0 0x0152
1242 +#define MT6323_DRV_CON1 0x0154
1243 +#define MT6323_DRV_CON2 0x0156
1244 +#define MT6323_DRV_CON3 0x0158
1245 +#define MT6323_DRV_CON4 0x015A
1246 +#define MT6323_SIMLS1_CON 0x015C
1247 +#define MT6323_SIMLS2_CON 0x015E
1248 +#define MT6323_INT_CON0 0x0160
1249 +#define MT6323_INT_CON0_SET 0x0162
1250 +#define MT6323_INT_CON0_CLR 0x0164
1251 +#define MT6323_INT_CON1 0x0166
1252 +#define MT6323_INT_CON1_SET 0x0168
1253 +#define MT6323_INT_CON1_CLR 0x016A
1254 +#define MT6323_INT_MISC_CON 0x016C
1255 +#define MT6323_INT_MISC_CON_SET 0x016E
1256 +#define MT6323_INT_MISC_CON_CLR 0x0170
1257 +#define MT6323_INT_STATUS0 0x0172
1258 +#define MT6323_INT_STATUS1 0x0174
1259 +#define MT6323_OC_GEAR_0 0x0176
1260 +#define MT6323_OC_GEAR_1 0x0178
1261 +#define MT6323_OC_GEAR_2 0x017A
1262 +#define MT6323_OC_CTL_VPROC 0x017C
1263 +#define MT6323_OC_CTL_VSYS 0x017E
1264 +#define MT6323_OC_CTL_VPA 0x0180
1265 +#define MT6323_FQMTR_CON0 0x0182
1266 +#define MT6323_FQMTR_CON1 0x0184
1267 +#define MT6323_FQMTR_CON2 0x0186
1268 +#define MT6323_RG_SPI_CON 0x0188
1269 +#define MT6323_DEW_DIO_EN 0x018A
1270 +#define MT6323_DEW_READ_TEST 0x018C
1271 +#define MT6323_DEW_WRITE_TEST 0x018E
1272 +#define MT6323_DEW_CRC_SWRST 0x0190
1273 +#define MT6323_DEW_CRC_EN 0x0192
1274 +#define MT6323_DEW_CRC_VAL 0x0194
1275 +#define MT6323_DEW_DBG_MON_SEL 0x0196
1276 +#define MT6323_DEW_CIPHER_KEY_SEL 0x0198
1277 +#define MT6323_DEW_CIPHER_IV_SEL 0x019A
1278 +#define MT6323_DEW_CIPHER_EN 0x019C
1279 +#define MT6323_DEW_CIPHER_RDY 0x019E
1280 +#define MT6323_DEW_CIPHER_MODE 0x01A0
1281 +#define MT6323_DEW_CIPHER_SWRST 0x01A2
1282 +#define MT6323_DEW_RDDMY_NO 0x01A4
1283 +#define MT6323_DEW_RDATA_DLY_SEL 0x01A6
1284 +#define MT6323_BUCK_CON0 0x0200
1285 +#define MT6323_BUCK_CON1 0x0202
1286 +#define MT6323_BUCK_CON2 0x0204
1287 +#define MT6323_BUCK_CON3 0x0206
1288 +#define MT6323_BUCK_CON4 0x0208
1289 +#define MT6323_BUCK_CON5 0x020A
1290 +#define MT6323_VPROC_CON0 0x020C
1291 +#define MT6323_VPROC_CON1 0x020E
1292 +#define MT6323_VPROC_CON2 0x0210
1293 +#define MT6323_VPROC_CON3 0x0212
1294 +#define MT6323_VPROC_CON4 0x0214
1295 +#define MT6323_VPROC_CON5 0x0216
1296 +#define MT6323_VPROC_CON7 0x021A
1297 +#define MT6323_VPROC_CON8 0x021C
1298 +#define MT6323_VPROC_CON9 0x021E
1299 +#define MT6323_VPROC_CON10 0x0220
1300 +#define MT6323_VPROC_CON11 0x0222
1301 +#define MT6323_VPROC_CON12 0x0224
1302 +#define MT6323_VPROC_CON13 0x0226
1303 +#define MT6323_VPROC_CON14 0x0228
1304 +#define MT6323_VPROC_CON15 0x022A
1305 +#define MT6323_VPROC_CON18 0x0230
1306 +#define MT6323_VSYS_CON0 0x0232
1307 +#define MT6323_VSYS_CON1 0x0234
1308 +#define MT6323_VSYS_CON2 0x0236
1309 +#define MT6323_VSYS_CON3 0x0238
1310 +#define MT6323_VSYS_CON4 0x023A
1311 +#define MT6323_VSYS_CON5 0x023C
1312 +#define MT6323_VSYS_CON7 0x0240
1313 +#define MT6323_VSYS_CON8 0x0242
1314 +#define MT6323_VSYS_CON9 0x0244
1315 +#define MT6323_VSYS_CON10 0x0246
1316 +#define MT6323_VSYS_CON11 0x0248
1317 +#define MT6323_VSYS_CON12 0x024A
1318 +#define MT6323_VSYS_CON13 0x024C
1319 +#define MT6323_VSYS_CON14 0x024E
1320 +#define MT6323_VSYS_CON15 0x0250
1321 +#define MT6323_VSYS_CON18 0x0256
1322 +#define MT6323_VPA_CON0 0x0300
1323 +#define MT6323_VPA_CON1 0x0302
1324 +#define MT6323_VPA_CON2 0x0304
1325 +#define MT6323_VPA_CON3 0x0306
1326 +#define MT6323_VPA_CON4 0x0308
1327 +#define MT6323_VPA_CON5 0x030A
1328 +#define MT6323_VPA_CON7 0x030E
1329 +#define MT6323_VPA_CON8 0x0310
1330 +#define MT6323_VPA_CON9 0x0312
1331 +#define MT6323_VPA_CON10 0x0314
1332 +#define MT6323_VPA_CON11 0x0316
1333 +#define MT6323_VPA_CON12 0x0318
1334 +#define MT6323_VPA_CON14 0x031C
1335 +#define MT6323_VPA_CON16 0x0320
1336 +#define MT6323_VPA_CON17 0x0322
1337 +#define MT6323_VPA_CON18 0x0324
1338 +#define MT6323_VPA_CON19 0x0326
1339 +#define MT6323_VPA_CON20 0x0328
1340 +#define MT6323_BUCK_K_CON0 0x032A
1341 +#define MT6323_BUCK_K_CON1 0x032C
1342 +#define MT6323_BUCK_K_CON2 0x032E
1343 +#define MT6323_ISINK0_CON0 0x0330
1344 +#define MT6323_ISINK0_CON1 0x0332
1345 +#define MT6323_ISINK0_CON2 0x0334
1346 +#define MT6323_ISINK0_CON3 0x0336
1347 +#define MT6323_ISINK1_CON0 0x0338
1348 +#define MT6323_ISINK1_CON1 0x033A
1349 +#define MT6323_ISINK1_CON2 0x033C
1350 +#define MT6323_ISINK1_CON3 0x033E
1351 +#define MT6323_ISINK2_CON0 0x0340
1352 +#define MT6323_ISINK2_CON1 0x0342
1353 +#define MT6323_ISINK2_CON2 0x0344
1354 +#define MT6323_ISINK2_CON3 0x0346
1355 +#define MT6323_ISINK3_CON0 0x0348
1356 +#define MT6323_ISINK3_CON1 0x034A
1357 +#define MT6323_ISINK3_CON2 0x034C
1358 +#define MT6323_ISINK3_CON3 0x034E
1359 +#define MT6323_ISINK_ANA0 0x0350
1360 +#define MT6323_ISINK_ANA1 0x0352
1361 +#define MT6323_ISINK_PHASE_DLY 0x0354
1362 +#define MT6323_ISINK_EN_CTRL 0x0356
1363 +#define MT6323_ANALDO_CON0 0x0400
1364 +#define MT6323_ANALDO_CON1 0x0402
1365 +#define MT6323_ANALDO_CON2 0x0404
1366 +#define MT6323_ANALDO_CON3 0x0406
1367 +#define MT6323_ANALDO_CON4 0x0408
1368 +#define MT6323_ANALDO_CON5 0x040A
1369 +#define MT6323_ANALDO_CON6 0x040C
1370 +#define MT6323_ANALDO_CON7 0x040E
1371 +#define MT6323_ANALDO_CON8 0x0410
1372 +#define MT6323_ANALDO_CON10 0x0412
1373 +#define MT6323_ANALDO_CON15 0x0414
1374 +#define MT6323_ANALDO_CON16 0x0416
1375 +#define MT6323_ANALDO_CON17 0x0418
1376 +#define MT6323_ANALDO_CON18 0x041A
1377 +#define MT6323_ANALDO_CON19 0x041C
1378 +#define MT6323_ANALDO_CON20 0x041E
1379 +#define MT6323_ANALDO_CON21 0x0420
1380 +#define MT6323_DIGLDO_CON0 0x0500
1381 +#define MT6323_DIGLDO_CON2 0x0502
1382 +#define MT6323_DIGLDO_CON3 0x0504
1383 +#define MT6323_DIGLDO_CON5 0x0506
1384 +#define MT6323_DIGLDO_CON6 0x0508
1385 +#define MT6323_DIGLDO_CON7 0x050A
1386 +#define MT6323_DIGLDO_CON8 0x050C
1387 +#define MT6323_DIGLDO_CON9 0x050E
1388 +#define MT6323_DIGLDO_CON10 0x0510
1389 +#define MT6323_DIGLDO_CON11 0x0512
1390 +#define MT6323_DIGLDO_CON12 0x0514
1391 +#define MT6323_DIGLDO_CON13 0x0516
1392 +#define MT6323_DIGLDO_CON14 0x0518
1393 +#define MT6323_DIGLDO_CON15 0x051A
1394 +#define MT6323_DIGLDO_CON16 0x051C
1395 +#define MT6323_DIGLDO_CON17 0x051E
1396 +#define MT6323_DIGLDO_CON18 0x0520
1397 +#define MT6323_DIGLDO_CON19 0x0522
1398 +#define MT6323_DIGLDO_CON20 0x0524
1399 +#define MT6323_DIGLDO_CON21 0x0526
1400 +#define MT6323_DIGLDO_CON23 0x0528
1401 +#define MT6323_DIGLDO_CON24 0x052A
1402 +#define MT6323_DIGLDO_CON26 0x052C
1403 +#define MT6323_DIGLDO_CON27 0x052E
1404 +#define MT6323_DIGLDO_CON28 0x0530
1405 +#define MT6323_DIGLDO_CON29 0x0532
1406 +#define MT6323_DIGLDO_CON30 0x0534
1407 +#define MT6323_DIGLDO_CON31 0x0536
1408 +#define MT6323_DIGLDO_CON32 0x0538
1409 +#define MT6323_DIGLDO_CON33 0x053A
1410 +#define MT6323_DIGLDO_CON34 0x053C
1411 +#define MT6323_DIGLDO_CON35 0x053E
1412 +#define MT6323_DIGLDO_CON36 0x0540
1413 +#define MT6323_DIGLDO_CON39 0x0542
1414 +#define MT6323_DIGLDO_CON40 0x0544
1415 +#define MT6323_DIGLDO_CON41 0x0546
1416 +#define MT6323_DIGLDO_CON42 0x0548
1417 +#define MT6323_DIGLDO_CON43 0x054A
1418 +#define MT6323_DIGLDO_CON44 0x054C
1419 +#define MT6323_DIGLDO_CON45 0x054E
1420 +#define MT6323_DIGLDO_CON46 0x0550
1421 +#define MT6323_DIGLDO_CON47 0x0552
1422 +#define MT6323_DIGLDO_CON48 0x0554
1423 +#define MT6323_DIGLDO_CON49 0x0556
1424 +#define MT6323_DIGLDO_CON50 0x0558
1425 +#define MT6323_DIGLDO_CON51 0x055A
1426 +#define MT6323_DIGLDO_CON52 0x055C
1427 +#define MT6323_DIGLDO_CON53 0x055E
1428 +#define MT6323_DIGLDO_CON54 0x0560
1429 +#define MT6323_EFUSE_CON0 0x0600
1430 +#define MT6323_EFUSE_CON1 0x0602
1431 +#define MT6323_EFUSE_CON2 0x0604
1432 +#define MT6323_EFUSE_CON3 0x0606
1433 +#define MT6323_EFUSE_CON4 0x0608
1434 +#define MT6323_EFUSE_CON5 0x060A
1435 +#define MT6323_EFUSE_CON6 0x060C
1436 +#define MT6323_EFUSE_VAL_0_15 0x060E
1437 +#define MT6323_EFUSE_VAL_16_31 0x0610
1438 +#define MT6323_EFUSE_VAL_32_47 0x0612
1439 +#define MT6323_EFUSE_VAL_48_63 0x0614
1440 +#define MT6323_EFUSE_VAL_64_79 0x0616
1441 +#define MT6323_EFUSE_VAL_80_95 0x0618
1442 +#define MT6323_EFUSE_VAL_96_111 0x061A
1443 +#define MT6323_EFUSE_VAL_112_127 0x061C
1444 +#define MT6323_EFUSE_VAL_128_143 0x061E
1445 +#define MT6323_EFUSE_VAL_144_159 0x0620
1446 +#define MT6323_EFUSE_VAL_160_175 0x0622
1447 +#define MT6323_EFUSE_VAL_176_191 0x0624
1448 +#define MT6323_EFUSE_DOUT_0_15 0x0626
1449 +#define MT6323_EFUSE_DOUT_16_31 0x0628
1450 +#define MT6323_EFUSE_DOUT_32_47 0x062A
1451 +#define MT6323_EFUSE_DOUT_48_63 0x062C
1452 +#define MT6323_EFUSE_DOUT_64_79 0x062E
1453 +#define MT6323_EFUSE_DOUT_80_95 0x0630
1454 +#define MT6323_EFUSE_DOUT_96_111 0x0632
1455 +#define MT6323_EFUSE_DOUT_112_127 0x0634
1456 +#define MT6323_EFUSE_DOUT_128_143 0x0636
1457 +#define MT6323_EFUSE_DOUT_144_159 0x0638
1458 +#define MT6323_EFUSE_DOUT_160_175 0x063A
1459 +#define MT6323_EFUSE_DOUT_176_191 0x063C
1460 +#define MT6323_EFUSE_CON7 0x063E
1461 +#define MT6323_EFUSE_CON8 0x0640
1462 +#define MT6323_EFUSE_CON9 0x0642
1463 +#define MT6323_RTC_MIX_CON0 0x0644
1464 +#define MT6323_RTC_MIX_CON1 0x0646
1465 +#define MT6323_AUDTOP_CON0 0x0700
1466 +#define MT6323_AUDTOP_CON1 0x0702
1467 +#define MT6323_AUDTOP_CON2 0x0704
1468 +#define MT6323_AUDTOP_CON3 0x0706
1469 +#define MT6323_AUDTOP_CON4 0x0708
1470 +#define MT6323_AUDTOP_CON5 0x070A
1471 +#define MT6323_AUDTOP_CON6 0x070C
1472 +#define MT6323_AUDTOP_CON7 0x070E
1473 +#define MT6323_AUDTOP_CON8 0x0710
1474 +#define MT6323_AUDTOP_CON9 0x0712
1475 +#define MT6323_AUXADC_ADC0 0x0714
1476 +#define MT6323_AUXADC_ADC1 0x0716
1477 +#define MT6323_AUXADC_ADC2 0x0718
1478 +#define MT6323_AUXADC_ADC3 0x071A
1479 +#define MT6323_AUXADC_ADC4 0x071C
1480 +#define MT6323_AUXADC_ADC5 0x071E
1481 +#define MT6323_AUXADC_ADC6 0x0720
1482 +#define MT6323_AUXADC_ADC7 0x0722
1483 +#define MT6323_AUXADC_ADC8 0x0724
1484 +#define MT6323_AUXADC_ADC9 0x0726
1485 +#define MT6323_AUXADC_ADC10 0x0728
1486 +#define MT6323_AUXADC_ADC11 0x072A
1487 +#define MT6323_AUXADC_ADC12 0x072C
1488 +#define MT6323_AUXADC_ADC13 0x072E
1489 +#define MT6323_AUXADC_ADC14 0x0730
1490 +#define MT6323_AUXADC_ADC15 0x0732
1491 +#define MT6323_AUXADC_ADC16 0x0734
1492 +#define MT6323_AUXADC_ADC17 0x0736
1493 +#define MT6323_AUXADC_ADC18 0x0738
1494 +#define MT6323_AUXADC_ADC19 0x073A
1495 +#define MT6323_AUXADC_ADC20 0x073C
1496 +#define MT6323_AUXADC_RSV1 0x073E
1497 +#define MT6323_AUXADC_RSV2 0x0740
1498 +#define MT6323_AUXADC_CON0 0x0742
1499 +#define MT6323_AUXADC_CON1 0x0744
1500 +#define MT6323_AUXADC_CON2 0x0746
1501 +#define MT6323_AUXADC_CON3 0x0748
1502 +#define MT6323_AUXADC_CON4 0x074A
1503 +#define MT6323_AUXADC_CON5 0x074C
1504 +#define MT6323_AUXADC_CON6 0x074E
1505 +#define MT6323_AUXADC_CON7 0x0750
1506 +#define MT6323_AUXADC_CON8 0x0752
1507 +#define MT6323_AUXADC_CON9 0x0754
1508 +#define MT6323_AUXADC_CON10 0x0756
1509 +#define MT6323_AUXADC_CON11 0x0758
1510 +#define MT6323_AUXADC_CON12 0x075A
1511 +#define MT6323_AUXADC_CON13 0x075C
1512 +#define MT6323_AUXADC_CON14 0x075E
1513 +#define MT6323_AUXADC_CON15 0x0760
1514 +#define MT6323_AUXADC_CON16 0x0762
1515 +#define MT6323_AUXADC_CON17 0x0764
1516 +#define MT6323_AUXADC_CON18 0x0766
1517 +#define MT6323_AUXADC_CON19 0x0768
1518 +#define MT6323_AUXADC_CON20 0x076A
1519 +#define MT6323_AUXADC_CON21 0x076C
1520 +#define MT6323_AUXADC_CON22 0x076E
1521 +#define MT6323_AUXADC_CON23 0x0770
1522 +#define MT6323_AUXADC_CON24 0x0772
1523 +#define MT6323_AUXADC_CON25 0x0774
1524 +#define MT6323_AUXADC_CON26 0x0776
1525 +#define MT6323_AUXADC_CON27 0x0778
1526 +#define MT6323_ACCDET_CON0 0x077A
1527 +#define MT6323_ACCDET_CON1 0x077C
1528 +#define MT6323_ACCDET_CON2 0x077E
1529 +#define MT6323_ACCDET_CON3 0x0780
1530 +#define MT6323_ACCDET_CON4 0x0782
1531 +#define MT6323_ACCDET_CON5 0x0784
1532 +#define MT6323_ACCDET_CON6 0x0786
1533 +#define MT6323_ACCDET_CON7 0x0788
1534 +#define MT6323_ACCDET_CON8 0x078A
1535 +#define MT6323_ACCDET_CON9 0x078C
1536 +#define MT6323_ACCDET_CON10 0x078E
1537 +#define MT6323_ACCDET_CON11 0x0790
1538 +#define MT6323_ACCDET_CON12 0x0792
1539 +#define MT6323_ACCDET_CON13 0x0794
1540 +#define MT6323_ACCDET_CON14 0x0796
1541 +#define MT6323_ACCDET_CON15 0x0798
1542 +#define MT6323_ACCDET_CON16 0x079A
1543
1544 -#endif /* __MFD_MT6397_REGISTERS_H__ */
1545 +#endif
1546 diff --git a/include/linux/regulator/mt6323-regulator.h b/include/linux/regulator/mt6323-regulator.h
1547 new file mode 100644
1548 index 0000000..620b0e3
1549 --- /dev/null
1550 +++ b/include/linux/regulator/mt6323-regulator.h
1551 @@ -0,0 +1,37 @@
1552 +/*
1553 + * Copyright (c) 2015 MediaTek Inc.
1554 + * Author: John Crispin <blogic@openwrt.org>
1555 + *
1556 + * This program is free software; you can redistribute it and/or modify
1557 + * it under the terms of the GNU General Public License version 2 as
1558 + * published by the Free Software Foundation.
1559 + *
1560 + * This program is distributed in the hope that it will be useful,
1561 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
1562 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1563 + * GNU General Public License for more details.
1564 + */
1565 +
1566 +#ifndef __LINUX_REGULATOR_MT6323_H
1567 +#define __LINUX_REGULATOR_MT6323_H
1568 +
1569 +enum {
1570 + MT6323_ID_VPROC = 0,
1571 + MT6323_ID_VSYS,
1572 + MT6323_ID_VPA,
1573 + MT6323_ID_VTCXO,
1574 + MT6323_ID_VA,
1575 + MT6323_ID_VCN28,
1576 + MT6323_ID_VCN33,
1577 + MT6323_ID_VIO28,
1578 + MT6323_ID_VUSB,
1579 + MT6323_ID_VMC,
1580 + MT6323_ID_VMCH,
1581 + MT6323_ID_VGP1,
1582 + MT6323_ID_VGP2,
1583 + MT6323_ID_RG_MAX,
1584 +};
1585 +
1586 +#define MT6323_MAX_REGULATOR MT6323_ID_RG_MAX
1587 +
1588 +#endif /* __LINUX_REGULATOR_MT6323_H */
1589 --
1590 1.7.10.4
1591
lynxis staging tree for omap