1 --- a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts
2 +++ b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts
4 stdout-path = "serial2:115200n8";
8 + reg = <0 0x80000000 0 0x20000000>;
13 proc-supply = <&mt6323_vproc_reg>;
16 reg = <0 0x80000000 0 0x40000000>;
20 + compatible = "mediatek,mt7530";
30 + compatible = "mediatek,eth-mac";
49 compatible = "mediatek,mt7530";
53 core-supply = <&mt6323_vpa_reg>;
54 io-supply = <&mt6323_vemc3v3_reg>;
56 + dsa,mii-bus = <&mdio>;
96 + ethernet = <&gmac1>;
105 + cpu_port0: port@6 {
117 pinctrl-names = "default";
118 --- a/arch/arm/boot/dts/Makefile
119 +++ b/arch/arm/boot/dts/Makefile
120 @@ -1061,6 +1061,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
122 mt6589-aquaris5.dtb \
124 + mt7623a-rfb-emmc.dtb \
125 mt7623n-rfb-nand.dtb \
126 mt7623n-bananapi-bpi-r2.dtb \
129 +++ b/arch/arm/boot/dts/mt7623a-rfb-emmc.dts
132 + * Copyright 2017 Sean Wang <sean.wang@mediatek.com>
134 + * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
138 +#include <dt-bindings/input/input.h>
139 +#include "mt7623.dtsi"
140 +#include "mt6323.dtsi"
143 + model = "MediaTek MT7623N NAND reference board";
144 + compatible = "mediatek,mt7623a-rfb-emmc", "mediatek,mt7623";
151 + bootargs = "earlyprintk block2mtd.block2mtd=/dev/mmcblk0,65536,eMMC,5 mtdparts=eMMC:256k(mbr)ro,512k(uboot)ro,256k(config)ro,256k(factory)ro,32M(kernel),32M(recovery),1024M(rootfs),2048M(usrdata),-(bmtpool) rootfstype=squashfs,jffs2";
153 + stdout-path = "serial2:115200n8";
157 + reg = <0 0x80000000 0 0x20000000>;
162 + proc-supply = <&mt6323_vproc_reg>;
166 + proc-supply = <&mt6323_vproc_reg>;
170 + proc-supply = <&mt6323_vproc_reg>;
174 + proc-supply = <&mt6323_vproc_reg>;
179 + reg = <0 0x80000000 0 0x40000000>;
183 + compatible = "mediatek,mt7530";
184 + #address-cells = <1>;
197 + compatible = "mediatek,eth-mac";
199 + phy-mode = "trgmii";
209 + compatible = "mediatek,eth-mac";
211 + phy-mode = "rgmiii-rxid";
212 + phy-handle = <&phy5>;
216 + #address-cells = <1>;
218 + phy5: ethernet-phy@5 {
220 + phy-mode = "rgmii-rxid";
226 + compatible = "mediatek,mt7530";
227 + #address-cells = <1>;
230 + pinctrl-names = "default";
232 + resets = <ðsys 2>;
233 + reset-names = "mcm";
234 + core-supply = <&mt6323_vpa_reg>;
235 + io-supply = <&mt6323_vemc3v3_reg>;
237 + dsa,mii-bus = <&mdio>;
240 + #address-cells = <1>;
247 + cpu = <&cpu_port0>;
253 + cpu = <&cpu_port0>;
259 + cpu = <&cpu_port0>;
265 + cpu = <&cpu_port0>;
268 + cpu_port0: port@6 {
271 + ethernet = <&gmac0>;
272 + phy-mode = "trgmii";
283 + pinctrl-names = "default";
284 + pinctrl-0 = <&i2c0_pins_a>;
289 + pinctrl-names = "default";
290 + pinctrl-0 = <&i2c1_pins_a>;
295 + pinctrl-names = "default", "state_uhs";
296 + pinctrl-0 = <&mmc0_pins_default>;
297 + pinctrl-1 = <&mmc0_pins_uhs>;
300 + max-frequency = <50000000>;
302 + vmmc-supply = <&mt6323_vemc3v3_reg>;
303 + vqmmc-supply = <&mt6323_vio18_reg>;
308 + pinctrl-names = "default", "state_uhs";
309 + pinctrl-0 = <&mmc1_pins_default>;
310 + pinctrl-1 = <&mmc1_pins_uhs>;
313 + max-frequency = <50000000>;
315 + cd-gpios = <&pio 261 0>;
316 + vmmc-supply = <&mt6323_vmch_reg>;
317 + vqmmc-supply = <&mt6323_vio18_reg>;
323 + pinmux = <MT7623_PIN_46_IR_FUNC_IR>;
328 + i2c0_pins_a: i2c@0 {
330 + pinmux = <MT7623_PIN_75_SDA0_FUNC_SDA0>,
331 + <MT7623_PIN_76_SCL0_FUNC_SCL0>;
336 + i2c1_pins_a: i2c@1 {
338 + pinmux = <MT7623_PIN_57_SDA1_FUNC_SDA1>,
339 + <MT7623_PIN_58_SCL1_FUNC_SCL1>;
344 + i2s0_pins_a: i2s@0 {
346 + pinmux = <MT7623_PIN_49_I2S0_DATA_FUNC_I2S0_DATA>,
347 + <MT7623_PIN_72_I2S0_DATA_IN_FUNC_I2S0_DATA_IN>,
348 + <MT7623_PIN_73_I2S0_LRCK_FUNC_I2S0_LRCK>,
349 + <MT7623_PIN_74_I2S0_BCK_FUNC_I2S0_BCK>,
350 + <MT7623_PIN_126_I2S0_MCLK_FUNC_I2S0_MCLK>;
351 + drive-strength = <MTK_DRIVE_12mA>;
356 + i2s1_pins_a: i2s@1 {
358 + pinmux = <MT7623_PIN_33_I2S1_DATA_FUNC_I2S1_DATA>,
359 + <MT7623_PIN_34_I2S1_DATA_IN_FUNC_I2S1_DATA_IN>,
360 + <MT7623_PIN_35_I2S1_BCK_FUNC_I2S1_BCK>,
361 + <MT7623_PIN_36_I2S1_LRCK_FUNC_I2S1_LRCK>,
362 + <MT7623_PIN_37_I2S1_MCLK_FUNC_I2S1_MCLK>;
363 + drive-strength = <MTK_DRIVE_12mA>;
368 + mmc0_pins_default: mmc0default {
370 + pinmux = <MT7623_PIN_111_MSDC0_DAT7_FUNC_MSDC0_DAT7>,
371 + <MT7623_PIN_112_MSDC0_DAT6_FUNC_MSDC0_DAT6>,
372 + <MT7623_PIN_113_MSDC0_DAT5_FUNC_MSDC0_DAT5>,
373 + <MT7623_PIN_114_MSDC0_DAT4_FUNC_MSDC0_DAT4>,
374 + <MT7623_PIN_118_MSDC0_DAT3_FUNC_MSDC0_DAT3>,
375 + <MT7623_PIN_119_MSDC0_DAT2_FUNC_MSDC0_DAT2>,
376 + <MT7623_PIN_120_MSDC0_DAT1_FUNC_MSDC0_DAT1>,
377 + <MT7623_PIN_121_MSDC0_DAT0_FUNC_MSDC0_DAT0>,
378 + <MT7623_PIN_116_MSDC0_CMD_FUNC_MSDC0_CMD>;
384 + pinmux = <MT7623_PIN_117_MSDC0_CLK_FUNC_MSDC0_CLK>;
389 + pinmux = <MT7623_PIN_115_MSDC0_RSTB_FUNC_MSDC0_RSTB>;
394 + mmc0_pins_uhs: mmc0 {
396 + pinmux = <MT7623_PIN_111_MSDC0_DAT7_FUNC_MSDC0_DAT7>,
397 + <MT7623_PIN_112_MSDC0_DAT6_FUNC_MSDC0_DAT6>,
398 + <MT7623_PIN_113_MSDC0_DAT5_FUNC_MSDC0_DAT5>,
399 + <MT7623_PIN_114_MSDC0_DAT4_FUNC_MSDC0_DAT4>,
400 + <MT7623_PIN_118_MSDC0_DAT3_FUNC_MSDC0_DAT3>,
401 + <MT7623_PIN_119_MSDC0_DAT2_FUNC_MSDC0_DAT2>,
402 + <MT7623_PIN_120_MSDC0_DAT1_FUNC_MSDC0_DAT1>,
403 + <MT7623_PIN_121_MSDC0_DAT0_FUNC_MSDC0_DAT0>,
404 + <MT7623_PIN_116_MSDC0_CMD_FUNC_MSDC0_CMD>;
406 + drive-strength = <MTK_DRIVE_2mA>;
407 + bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
411 + pinmux = <MT7623_PIN_117_MSDC0_CLK_FUNC_MSDC0_CLK>;
412 + drive-strength = <MTK_DRIVE_2mA>;
413 + bias-pull-down = <MTK_PUPD_SET_R1R0_01>;
417 + pinmux = <MT7623_PIN_115_MSDC0_RSTB_FUNC_MSDC0_RSTB>;
422 + mmc1_pins_default: mmc1default {
424 + pinmux = <MT7623_PIN_107_MSDC1_DAT0_FUNC_MSDC1_DAT0>,
425 + <MT7623_PIN_108_MSDC1_DAT1_FUNC_MSDC1_DAT1>,
426 + <MT7623_PIN_109_MSDC1_DAT2_FUNC_MSDC1_DAT2>,
427 + <MT7623_PIN_110_MSDC1_DAT3_FUNC_MSDC1_DAT3>,
428 + <MT7623_PIN_105_MSDC1_CMD_FUNC_MSDC1_CMD>;
430 + drive-strength = <MTK_DRIVE_4mA>;
431 + bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
435 + pinmux = <MT7623_PIN_106_MSDC1_CLK_FUNC_MSDC1_CLK>;
437 + drive-strength = <MTK_DRIVE_4mA>;
441 + pinmux = <MT7623_PIN_29_EINT7_FUNC_MSDC1_WP>;
447 + pinmux = <MT7623_PIN_261_MSDC1_INS_FUNC_GPIO261>;
452 + mmc1_pins_uhs: mmc1 {
454 + pinmux = <MT7623_PIN_107_MSDC1_DAT0_FUNC_MSDC1_DAT0>,
455 + <MT7623_PIN_108_MSDC1_DAT1_FUNC_MSDC1_DAT1>,
456 + <MT7623_PIN_109_MSDC1_DAT2_FUNC_MSDC1_DAT2>,
457 + <MT7623_PIN_110_MSDC1_DAT3_FUNC_MSDC1_DAT3>,
458 + <MT7623_PIN_105_MSDC1_CMD_FUNC_MSDC1_CMD>;
460 + drive-strength = <MTK_DRIVE_4mA>;
461 + bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
465 + pinmux = <MT7623_PIN_106_MSDC1_CLK_FUNC_MSDC1_CLK>;
466 + drive-strength = <MTK_DRIVE_4mA>;
467 + bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
471 + pwm_pins_a: pwm@0 {
473 + pinmux = <MT7623_PIN_203_PWM0_FUNC_PWM0>,
474 + <MT7623_PIN_204_PWM1_FUNC_PWM1>,
475 + <MT7623_PIN_205_PWM2_FUNC_PWM2>,
476 + <MT7623_PIN_206_PWM3_FUNC_PWM3>,
477 + <MT7623_PIN_207_PWM4_FUNC_PWM4>;
481 + spi0_pins_a: spi@0 {
483 + pinmux = <MT7623_PIN_53_SPI0_CSN_FUNC_SPI0_CS>,
484 + <MT7623_PIN_54_SPI0_CK_FUNC_SPI0_CK>,
485 + <MT7623_PIN_55_SPI0_MI_FUNC_SPI0_MI>,
486 + <MT7623_PIN_56_SPI0_MO_FUNC_SPI0_MO>;
491 + uart0_pins_a: uart@0 {
493 + pinmux = <MT7623_PIN_79_URXD0_FUNC_URXD0>,
494 + <MT7623_PIN_80_UTXD0_FUNC_UTXD0>;
498 + uart1_pins_a: uart@1 {
500 + pinmux = <MT7623_PIN_81_URXD1_FUNC_URXD1>,
501 + <MT7623_PIN_82_UTXD1_FUNC_UTXD1>;
507 + pinctrl-names = "default";
508 + pinctrl-0 = <&pwm_pins_a>;
515 + compatible = "mediatek,mt6323-led";
516 + #address-cells = <1>;
521 + label = "bpi-r2:isink:green";
522 + default-state = "off";
527 + label = "bpi-r2:isink:red";
528 + default-state = "off";
533 + label = "bpi-r2:isink:blue";
534 + default-state = "off";
541 + pinctrl-names = "default";
542 + pinctrl-0 = <&spi0_pins_a>;
547 + pinctrl-names = "default";
548 + pinctrl-0 = <&uart0_pins_a>;
549 + status = "disabled";
553 + pinctrl-names = "default";
554 + pinctrl-0 = <&uart1_pins_a>;
555 + status = "disabled";
563 + vusb33-supply = <&mt6323_vusb_reg>;
568 + vusb33-supply = <&mt6323_vusb_reg>;
580 --- a/arch/arm/boot/dts/mt7623.dtsi
581 +++ b/arch/arm/boot/dts/mt7623.dtsi
584 reg = <0 0x10209000 0 0x1000>;
586 + #reset-cells = <1>;