target/linux/mediatek/patches-4.14/0064-dts.patch

   1 Index: linux-4.14.18/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts
   2 ===================================================================
   3 --- linux-4.14.18.orig/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts
   4 +++ linux-4.14.18/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts
   5 @@ -21,6 +21,10 @@
   6                 stdout-path = "serial2:115200n8";
   7         };
   8
   9 +       memory {
  10 +               reg = <0 0x80000000 0 0x20000000>;
  11 +       };
  12 +
  13         cpus {
  14                 cpu@0 {
  15                         proc-supply = <&mt6323_vproc_reg>;
  16 @@ -84,6 +88,10 @@
  17         memory@80000000 {
  18                 reg = <0 0x80000000 0 0x40000000>;
  19         };
  20 +
  21 +       mt7530: switch@0 {
  22 +               compatible = "mediatek,mt7530";
  23 +       };
  24  };
  25
  26  &cir {
  27 @@ -111,11 +119,24 @@
  28                 };
  29         };
  30
  31 +       gmac1: mac@1 {
  32 +               compatible = "mediatek,eth-mac";
  33 +               reg = <1>;
  34 +               phy-mode = "rgmii";
  35 +
  36 +               fixed-link {
  37 +                       speed = <1000>;
  38 +                       full-duplex;
  39 +                       pause;
  40 +               };
  41 +       };
  42 +
  43         mdio: mdio-bus {
  44                 #address-cells = <1>;
  45                 #size-cells = <0>;
  46 -
  47 -               switch@0 {
  48 +       };
  49 +};
  50 +               &mt7530 {
  51                         compatible = "mediatek,mt7530";
  52                         #address-cells = <1>;
  53                         #size-cells = <0>;
  54 @@ -125,6 +146,8 @@
  55                         core-supply = <&mt6323_vpa_reg>;
  56                         io-supply = <&mt6323_vemc3v3_reg>;
  57
  58 +                       dsa,mii-bus = <&mdio>;
  59 +
  60                         ports {
  61                                 #address-cells = <1>;
  62                                 #size-cells = <0>;
  63 @@ -133,29 +156,46 @@
  64                                 port@0 {
  65                                         reg = <0>;
  66                                         label = "wan";
  67 +                                       cpu = <&cpu_port1>;
  68                                 };
  69
  70                                 port@1 {
  71                                         reg = <1>;
  72                                         label = "lan0";
  73 +                                       cpu = <&cpu_port0>;
  74                                 };
  75
  76                                 port@2 {
  77                                         reg = <2>;
  78                                         label = "lan1";
  79 +                                       cpu = <&cpu_port0>;
  80                                 };
  81
  82                                 port@3 {
  83                                         reg = <3>;
  84                                         label = "lan2";
  85 +                                       cpu = <&cpu_port0>;
  86                                 };
  87
  88                                 port@4 {
  89                                         reg = <4>;
  90                                         label = "lan3";
  91 +                                       cpu = <&cpu_port0>;
  92                                 };
  93
  94 -                               port@6 {
  95 +                               cpu_port1: port@5 {
  96 +                                       reg = <5>;
  97 +                                       label = "cpu";
  98 +                                       ethernet = <&gmac1>;
  99 +                                       phy-mode = "rgmii";
 100 +
 101 +                                       fixed-link {
 102 +                                               speed = <1000>;
 103 +                                               full-duplex;
 104 +                                       };
 105 +                               };
 106 +
 107 +                               cpu_port0: port@6 {
 108                                         reg = <6>;
 109                                         label = "cpu";
 110                                         ethernet = <&gmac0>;
 111 @@ -168,8 +208,6 @@
 112                                 };
 113                         };
 114                 };
 115 -       };
 116 -};
 117
 118  &i2c0 {
 119         pinctrl-names = "default";
 120 Index: linux-4.14.18/arch/arm/boot/dts/Makefile
 121 ===================================================================
 122 --- linux-4.14.18.orig/arch/arm/boot/dts/Makefile
 123 +++ linux-4.14.18/arch/arm/boot/dts/Makefile
 124 @@ -1061,6 +1061,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
 125         mt6580-evbp1.dtb \
 126         mt6589-aquaris5.dtb \
 127         mt6592-evb.dtb \
 128 +       mt7623a-rfb-emmc.dtb \
 129         mt7623n-rfb-nand.dtb \
 130         mt7623n-bananapi-bpi-r2.dtb \
 131         mt8127-moose.dtb \
 132 Index: linux-4.14.18/arch/arm/boot/dts/mt7623a-rfb-emmc.dts
 133 ===================================================================
 134 --- /dev/null
 135 +++ linux-4.14.18/arch/arm/boot/dts/mt7623a-rfb-emmc.dts
 136 @@ -0,0 +1,449 @@
 137 +/*
 138 + * Copyright 2017 Sean Wang <sean.wang@mediatek.com>
 139 + *
 140 + * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 141 + */
 142 +
 143 +/dts-v1/;
 144 +#include <dt-bindings/input/input.h>
 145 +#include "mt7623.dtsi"
 146 +#include "mt6323.dtsi"
 147 +
 148 +/ {
 149 +       model = "MediaTek MT7623N NAND reference board";
 150 +       compatible = "mediatek,mt7623a-rfb-emmc", "mediatek,mt7623";
 151 +
 152 +       aliases {
 153 +               serial2 = &uart2;
 154 +       };
 155 +
 156 +       chosen {
 157 +               bootargs = "earlyprintk block2mtd.block2mtd=/dev/mmcblk0,65536,eMMC,5 mtdparts=eMMC:256k(mbr)ro,512k(uboot)ro,256k(config)ro,256k(factory)ro,32M(kernel),32M(recovery),1024M(rootfs),2048M(usrdata),-(bmtpool) rootfstype=squashfs,jffs2";
 158 +
 159 +               stdout-path = "serial2:115200n8";
 160 +       };
 161 +
 162 +       memory {
 163 +               reg = <0 0x80000000 0 0x20000000>;
 164 +       };
 165 +
 166 +       cpus {
 167 +               cpu@0 {
 168 +                       proc-supply = <&mt6323_vproc_reg>;
 169 +               };
 170 +
 171 +               cpu@1 {
 172 +                       proc-supply = <&mt6323_vproc_reg>;
 173 +               };
 174 +
 175 +               cpu@2 {
 176 +                       proc-supply = <&mt6323_vproc_reg>;
 177 +               };
 178 +
 179 +               cpu@3 {
 180 +                       proc-supply = <&mt6323_vproc_reg>;
 181 +               };
 182 +       };
 183 +
 184 +       memory@80000000 {
 185 +               reg = <0 0x80000000 0 0x40000000>;
 186 +       };
 187 +
 188 +       mt7530: switch@0 {
 189 +               compatible = "mediatek,mt7530";
 190 +               #address-cells = <1>;
 191 +               #size-cells = <0>;
 192 +       };
 193 +};
 194 +
 195 +&crypto {
 196 +       status = "okay";
 197 +};
 198 +
 199 +&eth {
 200 +       status = "okay";
 201 +
 202 +       gmac0: mac@0 {
 203 +               compatible = "mediatek,eth-mac";
 204 +               reg = <0>;
 205 +               phy-mode = "trgmii";
 206 +
 207 +               fixed-link {
 208 +                       speed = <1000>;
 209 +                       full-duplex;
 210 +                       pause;
 211 +               };
 212 +       };
 213 +
 214 +       gmac1: mac@1 {
 215 +               compatible = "mediatek,eth-mac";
 216 +               reg = <1>;
 217 +               phy-mode = "rgmiii-rxid";
 218 +               phy-handle = <&phy5>;
 219 +       };
 220 +
 221 +       mdio: mdio-bus {
 222 +               #address-cells = <1>;
 223 +               #size-cells = <0>;
 224 +               phy5: ethernet-phy@5 {
 225 +                       reg = <5>;
 226 +                       phy-mode = "rgmii-rxid";
 227 +               };
 228 +       };
 229 +};
 230 +
 231 +&mt7530 {
 232 +       compatible = "mediatek,mt7530";
 233 +       #address-cells = <1>;
 234 +       #size-cells = <0>;
 235 +       reg = <0>;
 236 +       pinctrl-names = "default";
 237 +       mediatek,mcm;
 238 +       resets = <&ethsys 2>;
 239 +       reset-names = "mcm";
 240 +       core-supply = <&mt6323_vpa_reg>;
 241 +       io-supply = <&mt6323_vemc3v3_reg>;
 242 +
 243 +       dsa,mii-bus = <&mdio>;
 244 +
 245 +       ports {
 246 +               #address-cells = <1>;
 247 +               #size-cells = <0>;
 248 +               reg = <0>;
 249 +
 250 +               port@0 {
 251 +                       reg = <0>;
 252 +                       label = "lan0";
 253 +                       cpu = <&cpu_port0>;
 254 +               };
 255 +
 256 +               port@1 {
 257 +                       reg = <1>;
 258 +                       label = "lan1";
 259 +                       cpu = <&cpu_port0>;
 260 +               };
 261 +
 262 +               port@2 {
 263 +                       reg = <2>;
 264 +                       label = "lan2";
 265 +                       cpu = <&cpu_port0>;
 266 +               };
 267 +
 268 +               port@3 {
 269 +                       reg = <3>;
 270 +                       label = "lan3";
 271 +                       cpu = <&cpu_port0>;
 272 +               };
 273 +
 274 +               cpu_port0: port@6 {
 275 +                       reg = <6>;
 276 +                       label = "cpu";
 277 +                       ethernet = <&gmac0>;
 278 +                       phy-mode = "trgmii";
 279 +
 280 +                       fixed-link {
 281 +                               speed = <1000>;
 282 +                               full-duplex;
 283 +                       };
 284 +               };
 285 +       };
 286 +};
 287 +
 288 +&i2c0 {
 289 +       pinctrl-names = "default";
 290 +       pinctrl-0 = <&i2c0_pins_a>;
 291 +       status = "okay";
 292 +};
 293 +
 294 +&i2c1 {
 295 +       pinctrl-names = "default";
 296 +       pinctrl-0 = <&i2c1_pins_a>;
 297 +       status = "okay";
 298 +};
 299 +
 300 +&mmc0 {
 301 +       pinctrl-names = "default", "state_uhs";
 302 +       pinctrl-0 = <&mmc0_pins_default>;
 303 +       pinctrl-1 = <&mmc0_pins_uhs>;
 304 +       status = "okay";
 305 +       bus-width = <8>;
 306 +       max-frequency = <50000000>;
 307 +       cap-mmc-highspeed;
 308 +       vmmc-supply = <&mt6323_vemc3v3_reg>;
 309 +       vqmmc-supply = <&mt6323_vio18_reg>;
 310 +       non-removable;
 311 +};
 312 +
 313 +&mmc1 {
 314 +       pinctrl-names = "default", "state_uhs";
 315 +       pinctrl-0 = <&mmc1_pins_default>;
 316 +       pinctrl-1 = <&mmc1_pins_uhs>;
 317 +       status = "okay";
 318 +       bus-width = <4>;
 319 +       max-frequency = <50000000>;
 320 +       cap-sd-highspeed;
 321 +       cd-gpios = <&pio 261 0>;
 322 +       vmmc-supply = <&mt6323_vmch_reg>;
 323 +       vqmmc-supply = <&mt6323_vio18_reg>;
 324 +};
 325 +
 326 +&pio {
 327 +       cir_pins_a:cir@0 {
 328 +               pins_cir {
 329 +                       pinmux = <MT7623_PIN_46_IR_FUNC_IR>;
 330 +                       bias-disable;
 331 +               };
 332 +       };
 333 +
 334 +       i2c0_pins_a: i2c@0 {
 335 +               pins_i2c0 {
 336 +                       pinmux = <MT7623_PIN_75_SDA0_FUNC_SDA0>,
 337 +                                <MT7623_PIN_76_SCL0_FUNC_SCL0>;
 338 +                       bias-disable;
 339 +               };
 340 +       };
 341 +
 342 +       i2c1_pins_a: i2c@1 {
 343 +               pin_i2c1 {
 344 +                       pinmux = <MT7623_PIN_57_SDA1_FUNC_SDA1>,
 345 +                                <MT7623_PIN_58_SCL1_FUNC_SCL1>;
 346 +                       bias-disable;
 347 +               };
 348 +       };
 349 +
 350 +       i2s0_pins_a: i2s@0 {
 351 +               pin_i2s0 {
 352 +                       pinmux = <MT7623_PIN_49_I2S0_DATA_FUNC_I2S0_DATA>,
 353 +                                <MT7623_PIN_72_I2S0_DATA_IN_FUNC_I2S0_DATA_IN>,
 354 +                                <MT7623_PIN_73_I2S0_LRCK_FUNC_I2S0_LRCK>,
 355 +                                <MT7623_PIN_74_I2S0_BCK_FUNC_I2S0_BCK>,
 356 +                                <MT7623_PIN_126_I2S0_MCLK_FUNC_I2S0_MCLK>;
 357 +                       drive-strength = <MTK_DRIVE_12mA>;
 358 +                       bias-pull-down;
 359 +               };
 360 +       };
 361 +
 362 +       i2s1_pins_a: i2s@1 {
 363 +               pin_i2s1 {
 364 +                       pinmux = <MT7623_PIN_33_I2S1_DATA_FUNC_I2S1_DATA>,
 365 +                                <MT7623_PIN_34_I2S1_DATA_IN_FUNC_I2S1_DATA_IN>,
 366 +                                <MT7623_PIN_35_I2S1_BCK_FUNC_I2S1_BCK>,
 367 +                                <MT7623_PIN_36_I2S1_LRCK_FUNC_I2S1_LRCK>,
 368 +                                <MT7623_PIN_37_I2S1_MCLK_FUNC_I2S1_MCLK>;
 369 +                       drive-strength = <MTK_DRIVE_12mA>;
 370 +                       bias-pull-down;
 371 +               };
 372 +       };
 373 +
 374 +       mmc0_pins_default: mmc0default {
 375 +               pins_cmd_dat {
 376 +                       pinmux = <MT7623_PIN_111_MSDC0_DAT7_FUNC_MSDC0_DAT7>,
 377 +                                <MT7623_PIN_112_MSDC0_DAT6_FUNC_MSDC0_DAT6>,
 378 +                                <MT7623_PIN_113_MSDC0_DAT5_FUNC_MSDC0_DAT5>,
 379 +                                <MT7623_PIN_114_MSDC0_DAT4_FUNC_MSDC0_DAT4>,
 380 +                                <MT7623_PIN_118_MSDC0_DAT3_FUNC_MSDC0_DAT3>,
 381 +                                <MT7623_PIN_119_MSDC0_DAT2_FUNC_MSDC0_DAT2>,
 382 +                                <MT7623_PIN_120_MSDC0_DAT1_FUNC_MSDC0_DAT1>,
 383 +                                <MT7623_PIN_121_MSDC0_DAT0_FUNC_MSDC0_DAT0>,
 384 +                                <MT7623_PIN_116_MSDC0_CMD_FUNC_MSDC0_CMD>;
 385 +                       input-enable;
 386 +                       bias-pull-up;
 387 +               };
 388 +
 389 +               pins_clk {
 390 +                       pinmux = <MT7623_PIN_117_MSDC0_CLK_FUNC_MSDC0_CLK>;
 391 +                       bias-pull-down;
 392 +               };
 393 +
 394 +               pins_rst {
 395 +                       pinmux = <MT7623_PIN_115_MSDC0_RSTB_FUNC_MSDC0_RSTB>;
 396 +                       bias-pull-up;
 397 +               };
 398 +       };
 399 +
 400 +       mmc0_pins_uhs: mmc0 {
 401 +               pins_cmd_dat {
 402 +                       pinmux = <MT7623_PIN_111_MSDC0_DAT7_FUNC_MSDC0_DAT7>,
 403 +                                <MT7623_PIN_112_MSDC0_DAT6_FUNC_MSDC0_DAT6>,
 404 +                                <MT7623_PIN_113_MSDC0_DAT5_FUNC_MSDC0_DAT5>,
 405 +                                <MT7623_PIN_114_MSDC0_DAT4_FUNC_MSDC0_DAT4>,
 406 +                                <MT7623_PIN_118_MSDC0_DAT3_FUNC_MSDC0_DAT3>,
 407 +                                <MT7623_PIN_119_MSDC0_DAT2_FUNC_MSDC0_DAT2>,
 408 +                                <MT7623_PIN_120_MSDC0_DAT1_FUNC_MSDC0_DAT1>,
 409 +                                <MT7623_PIN_121_MSDC0_DAT0_FUNC_MSDC0_DAT0>,
 410 +                                <MT7623_PIN_116_MSDC0_CMD_FUNC_MSDC0_CMD>;
 411 +                       input-enable;
 412 +                       drive-strength = <MTK_DRIVE_2mA>;
 413 +                       bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
 414 +               };
 415 +
 416 +               pins_clk {
 417 +                       pinmux = <MT7623_PIN_117_MSDC0_CLK_FUNC_MSDC0_CLK>;
 418 +                       drive-strength = <MTK_DRIVE_2mA>;
 419 +                       bias-pull-down = <MTK_PUPD_SET_R1R0_01>;
 420 +               };
 421 +
 422 +               pins_rst {
 423 +                       pinmux = <MT7623_PIN_115_MSDC0_RSTB_FUNC_MSDC0_RSTB>;
 424 +                       bias-pull-up;
 425 +               };
 426 +       };
 427 +
 428 +       mmc1_pins_default: mmc1default {
 429 +               pins_cmd_dat {
 430 +                       pinmux = <MT7623_PIN_107_MSDC1_DAT0_FUNC_MSDC1_DAT0>,
 431 +                                <MT7623_PIN_108_MSDC1_DAT1_FUNC_MSDC1_DAT1>,
 432 +                                <MT7623_PIN_109_MSDC1_DAT2_FUNC_MSDC1_DAT2>,
 433 +                                <MT7623_PIN_110_MSDC1_DAT3_FUNC_MSDC1_DAT3>,
 434 +                                <MT7623_PIN_105_MSDC1_CMD_FUNC_MSDC1_CMD>;
 435 +                       input-enable;
 436 +                       drive-strength = <MTK_DRIVE_4mA>;
 437 +                       bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
 438 +               };
 439 +
 440 +               pins_clk {
 441 +                       pinmux = <MT7623_PIN_106_MSDC1_CLK_FUNC_MSDC1_CLK>;
 442 +                       bias-pull-down;
 443 +                       drive-strength = <MTK_DRIVE_4mA>;
 444 +               };
 445 +
 446 +               pins_wp {
 447 +                       pinmux = <MT7623_PIN_29_EINT7_FUNC_MSDC1_WP>;
 448 +                       input-enable;
 449 +                       bias-pull-up;
 450 +               };
 451 +
 452 +               pins_insert {
 453 +                       pinmux = <MT7623_PIN_261_MSDC1_INS_FUNC_GPIO261>;
 454 +                       bias-pull-up;
 455 +               };
 456 +       };
 457 +
 458 +       mmc1_pins_uhs: mmc1 {
 459 +               pins_cmd_dat {
 460 +                       pinmux = <MT7623_PIN_107_MSDC1_DAT0_FUNC_MSDC1_DAT0>,
 461 +                                <MT7623_PIN_108_MSDC1_DAT1_FUNC_MSDC1_DAT1>,
 462 +                                <MT7623_PIN_109_MSDC1_DAT2_FUNC_MSDC1_DAT2>,
 463 +                                <MT7623_PIN_110_MSDC1_DAT3_FUNC_MSDC1_DAT3>,
 464 +                                <MT7623_PIN_105_MSDC1_CMD_FUNC_MSDC1_CMD>;
 465 +                       input-enable;
 466 +                       drive-strength = <MTK_DRIVE_4mA>;
 467 +                       bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
 468 +               };
 469 +
 470 +               pins_clk {
 471 +                       pinmux = <MT7623_PIN_106_MSDC1_CLK_FUNC_MSDC1_CLK>;
 472 +                       drive-strength = <MTK_DRIVE_4mA>;
 473 +                       bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
 474 +               };
 475 +       };
 476 +
 477 +       pwm_pins_a: pwm@0 {
 478 +               pins_pwm {
 479 +                       pinmux = <MT7623_PIN_203_PWM0_FUNC_PWM0>,
 480 +                                <MT7623_PIN_204_PWM1_FUNC_PWM1>,
 481 +                                <MT7623_PIN_205_PWM2_FUNC_PWM2>,
 482 +                                <MT7623_PIN_206_PWM3_FUNC_PWM3>,
 483 +                                <MT7623_PIN_207_PWM4_FUNC_PWM4>;
 484 +               };
 485 +       };
 486 +
 487 +       spi0_pins_a: spi@0 {
 488 +               pins_spi {
 489 +                       pinmux = <MT7623_PIN_53_SPI0_CSN_FUNC_SPI0_CS>,
 490 +                               <MT7623_PIN_54_SPI0_CK_FUNC_SPI0_CK>,
 491 +                               <MT7623_PIN_55_SPI0_MI_FUNC_SPI0_MI>,
 492 +                               <MT7623_PIN_56_SPI0_MO_FUNC_SPI0_MO>;
 493 +                       bias-disable;
 494 +               };
 495 +       };
 496 +
 497 +       uart0_pins_a: uart@0 {
 498 +               pins_dat {
 499 +                       pinmux = <MT7623_PIN_79_URXD0_FUNC_URXD0>,
 500 +                                <MT7623_PIN_80_UTXD0_FUNC_UTXD0>;
 501 +               };
 502 +       };
 503 +
 504 +       uart1_pins_a: uart@1 {
 505 +               pins_dat {
 506 +                       pinmux = <MT7623_PIN_81_URXD1_FUNC_URXD1>,
 507 +                                <MT7623_PIN_82_UTXD1_FUNC_UTXD1>;
 508 +               };
 509 +       };
 510 +};
 511 +
 512 +&pwm {
 513 +       pinctrl-names = "default";
 514 +       pinctrl-0 = <&pwm_pins_a>;
 515 +       status = "okay";
 516 +};
 517 +
 518 +&pwrap {
 519 +       mt6323 {
 520 +               mt6323led: led {
 521 +                       compatible = "mediatek,mt6323-led";
 522 +                       #address-cells = <1>;
 523 +                       #size-cells = <0>;
 524 +
 525 +                       led@0 {
 526 +                               reg = <0>;
 527 +                               label = "bpi-r2:isink:green";
 528 +                               default-state = "off";
 529 +                       };
 530 +
 531 +                       led@1 {
 532 +                               reg = <1>;
 533 +                               label = "bpi-r2:isink:red";
 534 +                               default-state = "off";
 535 +                       };
 536 +
 537 +                       led@2 {
 538 +                               reg = <2>;
 539 +                               label = "bpi-r2:isink:blue";
 540 +                               default-state = "off";
 541 +                       };
 542 +               };
 543 +       };
 544 +};
 545 +
 546 +&spi0 {
 547 +       pinctrl-names = "default";
 548 +       pinctrl-0 = <&spi0_pins_a>;
 549 +       status = "okay";
 550 +};
 551 +
 552 +&uart0 {
 553 +       pinctrl-names = "default";
 554 +       pinctrl-0 = <&uart0_pins_a>;
 555 +       status = "disabled";
 556 +};
 557 +
 558 +&uart1 {
 559 +       pinctrl-names = "default";
 560 +       pinctrl-0 = <&uart1_pins_a>;
 561 +       status = "disabled";
 562 +};
 563 +
 564 +&uart2 {
 565 +       status = "okay";
 566 +};
 567 +
 568 +&usb1 {
 569 +       vusb33-supply = <&mt6323_vusb_reg>;
 570 +       status = "okay";
 571 +};
 572 +
 573 +&usb2 {
 574 +       vusb33-supply = <&mt6323_vusb_reg>;
 575 +       status = "okay";
 576 +};
 577 +
 578 +&u3phy1 {
 579 +       status = "okay";
 580 +};
 581 +
 582 +&u3phy2 {
 583 +       status = "okay";
 584 +};
 585 +
 586 Index: linux-4.14.18/arch/arm/boot/dts/mt7623.dtsi
 587 ===================================================================
 588 --- linux-4.14.18.orig/arch/arm/boot/dts/mt7623.dtsi
 589 +++ linux-4.14.18/arch/arm/boot/dts/mt7623.dtsi
 590 @@ -753,6 +753,7 @@
 591                              "syscon";
 592                 reg = <0 0x1b000000 0 0x1000>;
 593                 #clock-cells = <1>;
 594 +               #reset-cells = <1>;
 595         };
 596
 597         eth: ethernet@1b100000 {