1 From 442c890727e0f585154662b0908fbe3a7986052a Mon Sep 17 00:00:00 2001
2 From: Sean Wang <sean.wang@mediatek.com>
3 Date: Wed, 18 Oct 2017 16:28:47 +0800
4 Subject: [PATCH 121/224] soc: mediatek: pwrap: add common way for setup CS
7 Multiple platforms would always use their own way handling CS timing
8 extension on the bus which leads to a little bit code duplication.
9 Therefore, the patch groups the similar logic to handle CS timing
10 extension into the common function which allows the following SoCs
11 have more reusability for configing CS timing.
13 Signed-off-by: Chenglin Xu <chenglin.xu@mediatek.com>
14 Signed-off-by: Sean Wang <sean.wang@mediatek.com>
15 Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
17 drivers/soc/mediatek/mtk-pmic-wrap.c | 59 ++++++++++++++++++++++--------------
18 1 file changed, 37 insertions(+), 22 deletions(-)
20 --- a/drivers/soc/mediatek/mtk-pmic-wrap.c
21 +++ b/drivers/soc/mediatek/mtk-pmic-wrap.c
22 @@ -827,23 +827,44 @@ static int pwrap_init_dual_io(struct pmi
26 -static int pwrap_mt8135_init_reg_clock(struct pmic_wrapper *wrp)
28 - pwrap_writel(wrp, 0x4, PWRAP_CSHEXT);
29 - pwrap_writel(wrp, 0x0, PWRAP_CSHEXT_WRITE);
30 - pwrap_writel(wrp, 0x4, PWRAP_CSHEXT_READ);
31 - pwrap_writel(wrp, 0x0, PWRAP_CSLEXT_START);
32 - pwrap_writel(wrp, 0x0, PWRAP_CSLEXT_END);
36 + * pwrap_init_chip_select_ext is used to configure CS extension time for each
37 + * phase during data transactions on the pwrap bus.
39 +static void pwrap_init_chip_select_ext(struct pmic_wrapper *wrp, u8 hext_write,
40 + u8 hext_read, u8 lext_start,
44 + * After finishing a write and read transaction, extends CS high time
45 + * to be at least xT of BUS CLK as hext_write and hext_read specifies
48 + pwrap_writel(wrp, hext_write, PWRAP_CSHEXT_WRITE);
49 + pwrap_writel(wrp, hext_read, PWRAP_CSHEXT_READ);
52 + * Extends CS low time after CSL and before CSH command to be at
53 + * least xT of BUS CLK as lext_start and lext_end specifies
56 + pwrap_writel(wrp, lext_start, PWRAP_CSLEXT_START);
57 + pwrap_writel(wrp, lext_end, PWRAP_CSLEXT_END);
60 -static int pwrap_mt8173_init_reg_clock(struct pmic_wrapper *wrp)
61 +static int pwrap_common_init_reg_clock(struct pmic_wrapper *wrp)
63 - pwrap_writel(wrp, 0x0, PWRAP_CSHEXT_WRITE);
64 - pwrap_writel(wrp, 0x4, PWRAP_CSHEXT_READ);
65 - pwrap_writel(wrp, 0x2, PWRAP_CSLEXT_START);
66 - pwrap_writel(wrp, 0x2, PWRAP_CSLEXT_END);
67 + switch (wrp->master->type) {
69 + pwrap_init_chip_select_ext(wrp, 0, 4, 2, 2);
72 + pwrap_writel(wrp, 0x4, PWRAP_CSHEXT);
73 + pwrap_init_chip_select_ext(wrp, 0, 4, 0, 0);
81 @@ -853,20 +874,14 @@ static int pwrap_mt2701_init_reg_clock(s
82 switch (wrp->slave->type) {
84 pwrap_writel(wrp, 0xc, PWRAP_RDDMY);
85 - pwrap_writel(wrp, 0x4, PWRAP_CSHEXT_WRITE);
86 - pwrap_writel(wrp, 0x0, PWRAP_CSHEXT_READ);
87 - pwrap_writel(wrp, 0x2, PWRAP_CSLEXT_START);
88 - pwrap_writel(wrp, 0x2, PWRAP_CSLEXT_END);
89 + pwrap_init_chip_select_ext(wrp, 4, 0, 2, 2);
93 pwrap_writel(wrp, 0x8, PWRAP_RDDMY);
94 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_RDDMY_NO],
96 - pwrap_writel(wrp, 0x5, PWRAP_CSHEXT_WRITE);
97 - pwrap_writel(wrp, 0x0, PWRAP_CSHEXT_READ);
98 - pwrap_writel(wrp, 0x2, PWRAP_CSLEXT_START);
99 - pwrap_writel(wrp, 0x2, PWRAP_CSLEXT_END);
100 + pwrap_init_chip_select_ext(wrp, 5, 0, 2, 2);
104 @@ -1235,7 +1250,7 @@ static const struct pmic_wrapper_type pw
105 .spi_w = PWRAP_MAN_CMD_SPI_WRITE,
106 .wdt_src = PWRAP_WDT_SRC_MASK_ALL,
108 - .init_reg_clock = pwrap_mt8135_init_reg_clock,
109 + .init_reg_clock = pwrap_common_init_reg_clock,
110 .init_soc_specific = pwrap_mt8135_init_soc_specific,
113 @@ -1247,7 +1262,7 @@ static const struct pmic_wrapper_type pw
114 .spi_w = PWRAP_MAN_CMD_SPI_WRITE,
115 .wdt_src = PWRAP_WDT_SRC_MASK_NO_STAUPD,
117 - .init_reg_clock = pwrap_mt8173_init_reg_clock,
118 + .init_reg_clock = pwrap_common_init_reg_clock,
119 .init_soc_specific = pwrap_mt8173_init_soc_specific,