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mediatek: backport upstream mediatek patches
[openwrt/staging/hauke.git] / target / linux / mediatek / patches-4.14 / 0122-soc-mediatek-pwrap-add-support-for-MT7622-SoC.patch
1 From 87996dabef0d83bbd2ed5264b83b01224bc42968 Mon Sep 17 00:00:00 2001
2 From: Chenglin Xu <chenglin.xu@mediatek.com>
3 Date: Wed, 18 Oct 2017 16:28:48 +0800
4 Subject: [PATCH 122/224] soc: mediatek: pwrap: add support for MT7622 SoC
5
6 Add the registers, callbacks and data structures required to make the
7 PMIC wrapper work on MT7622.
8
9 Signed-off-by: Chenglin Xu <chenglin.xu@mediatek.com>
10 Signed-off-by: Chen Zhong <chen.zhong@mediatek.com>
11 Signed-off-by: Sean Wang <sean.wang@mediatek.com>
12 Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
13 ---
14 drivers/soc/mediatek/mtk-pmic-wrap.c | 170 +++++++++++++++++++++++++++++++++++
15 1 file changed, 170 insertions(+)
16
17 diff --git a/drivers/soc/mediatek/mtk-pmic-wrap.c b/drivers/soc/mediatek/mtk-pmic-wrap.c
18 index cbc3f0e82337..5d61d127e1d7 100644
19 --- a/drivers/soc/mediatek/mtk-pmic-wrap.c
20 +++ b/drivers/soc/mediatek/mtk-pmic-wrap.c
21 @@ -214,6 +214,36 @@ enum pwrap_regs {
22 PWRAP_ADC_RDATA_ADDR1,
23 PWRAP_ADC_RDATA_ADDR2,
24
25 + /* MT7622 only regs */
26 + PWRAP_EINT_STA0_ADR,
27 + PWRAP_EINT_STA1_ADR,
28 + PWRAP_STA,
29 + PWRAP_CLR,
30 + PWRAP_DVFS_ADR8,
31 + PWRAP_DVFS_WDATA8,
32 + PWRAP_DVFS_ADR9,
33 + PWRAP_DVFS_WDATA9,
34 + PWRAP_DVFS_ADR10,
35 + PWRAP_DVFS_WDATA10,
36 + PWRAP_DVFS_ADR11,
37 + PWRAP_DVFS_WDATA11,
38 + PWRAP_DVFS_ADR12,
39 + PWRAP_DVFS_WDATA12,
40 + PWRAP_DVFS_ADR13,
41 + PWRAP_DVFS_WDATA13,
42 + PWRAP_DVFS_ADR14,
43 + PWRAP_DVFS_WDATA14,
44 + PWRAP_DVFS_ADR15,
45 + PWRAP_DVFS_WDATA15,
46 + PWRAP_EXT_CK,
47 + PWRAP_ADC_RDATA_ADDR,
48 + PWRAP_GPS_STA,
49 + PWRAP_SW_RST,
50 + PWRAP_DVFS_STEP_CTRL0,
51 + PWRAP_DVFS_STEP_CTRL1,
52 + PWRAP_DVFS_STEP_CTRL2,
53 + PWRAP_SPI2_CTRL,
54 +
55 /* MT8135 only regs */
56 PWRAP_CSHEXT,
57 PWRAP_EVENT_IN_EN,
58 @@ -336,6 +366,118 @@ static int mt2701_regs[] = {
59 [PWRAP_ADC_RDATA_ADDR2] = 0x154,
60 };
61
62 +static int mt7622_regs[] = {
63 + [PWRAP_MUX_SEL] = 0x0,
64 + [PWRAP_WRAP_EN] = 0x4,
65 + [PWRAP_DIO_EN] = 0x8,
66 + [PWRAP_SIDLY] = 0xC,
67 + [PWRAP_RDDMY] = 0x10,
68 + [PWRAP_SI_CK_CON] = 0x14,
69 + [PWRAP_CSHEXT_WRITE] = 0x18,
70 + [PWRAP_CSHEXT_READ] = 0x1C,
71 + [PWRAP_CSLEXT_START] = 0x20,
72 + [PWRAP_CSLEXT_END] = 0x24,
73 + [PWRAP_STAUPD_PRD] = 0x28,
74 + [PWRAP_STAUPD_GRPEN] = 0x2C,
75 + [PWRAP_EINT_STA0_ADR] = 0x30,
76 + [PWRAP_EINT_STA1_ADR] = 0x34,
77 + [PWRAP_STA] = 0x38,
78 + [PWRAP_CLR] = 0x3C,
79 + [PWRAP_STAUPD_MAN_TRIG] = 0x40,
80 + [PWRAP_STAUPD_STA] = 0x44,
81 + [PWRAP_WRAP_STA] = 0x48,
82 + [PWRAP_HARB_INIT] = 0x4C,
83 + [PWRAP_HARB_HPRIO] = 0x50,
84 + [PWRAP_HIPRIO_ARB_EN] = 0x54,
85 + [PWRAP_HARB_STA0] = 0x58,
86 + [PWRAP_HARB_STA1] = 0x5C,
87 + [PWRAP_MAN_EN] = 0x60,
88 + [PWRAP_MAN_CMD] = 0x64,
89 + [PWRAP_MAN_RDATA] = 0x68,
90 + [PWRAP_MAN_VLDCLR] = 0x6C,
91 + [PWRAP_WACS0_EN] = 0x70,
92 + [PWRAP_INIT_DONE0] = 0x74,
93 + [PWRAP_WACS0_CMD] = 0x78,
94 + [PWRAP_WACS0_RDATA] = 0x7C,
95 + [PWRAP_WACS0_VLDCLR] = 0x80,
96 + [PWRAP_WACS1_EN] = 0x84,
97 + [PWRAP_INIT_DONE1] = 0x88,
98 + [PWRAP_WACS1_CMD] = 0x8C,
99 + [PWRAP_WACS1_RDATA] = 0x90,
100 + [PWRAP_WACS1_VLDCLR] = 0x94,
101 + [PWRAP_WACS2_EN] = 0x98,
102 + [PWRAP_INIT_DONE2] = 0x9C,
103 + [PWRAP_WACS2_CMD] = 0xA0,
104 + [PWRAP_WACS2_RDATA] = 0xA4,
105 + [PWRAP_WACS2_VLDCLR] = 0xA8,
106 + [PWRAP_INT_EN] = 0xAC,
107 + [PWRAP_INT_FLG_RAW] = 0xB0,
108 + [PWRAP_INT_FLG] = 0xB4,
109 + [PWRAP_INT_CLR] = 0xB8,
110 + [PWRAP_SIG_ADR] = 0xBC,
111 + [PWRAP_SIG_MODE] = 0xC0,
112 + [PWRAP_SIG_VALUE] = 0xC4,
113 + [PWRAP_SIG_ERRVAL] = 0xC8,
114 + [PWRAP_CRC_EN] = 0xCC,
115 + [PWRAP_TIMER_EN] = 0xD0,
116 + [PWRAP_TIMER_STA] = 0xD4,
117 + [PWRAP_WDT_UNIT] = 0xD8,
118 + [PWRAP_WDT_SRC_EN] = 0xDC,
119 + [PWRAP_WDT_FLG] = 0xE0,
120 + [PWRAP_DEBUG_INT_SEL] = 0xE4,
121 + [PWRAP_DVFS_ADR0] = 0xE8,
122 + [PWRAP_DVFS_WDATA0] = 0xEC,
123 + [PWRAP_DVFS_ADR1] = 0xF0,
124 + [PWRAP_DVFS_WDATA1] = 0xF4,
125 + [PWRAP_DVFS_ADR2] = 0xF8,
126 + [PWRAP_DVFS_WDATA2] = 0xFC,
127 + [PWRAP_DVFS_ADR3] = 0x100,
128 + [PWRAP_DVFS_WDATA3] = 0x104,
129 + [PWRAP_DVFS_ADR4] = 0x108,
130 + [PWRAP_DVFS_WDATA4] = 0x10C,
131 + [PWRAP_DVFS_ADR5] = 0x110,
132 + [PWRAP_DVFS_WDATA5] = 0x114,
133 + [PWRAP_DVFS_ADR6] = 0x118,
134 + [PWRAP_DVFS_WDATA6] = 0x11C,
135 + [PWRAP_DVFS_ADR7] = 0x120,
136 + [PWRAP_DVFS_WDATA7] = 0x124,
137 + [PWRAP_DVFS_ADR8] = 0x128,
138 + [PWRAP_DVFS_WDATA8] = 0x12C,
139 + [PWRAP_DVFS_ADR9] = 0x130,
140 + [PWRAP_DVFS_WDATA9] = 0x134,
141 + [PWRAP_DVFS_ADR10] = 0x138,
142 + [PWRAP_DVFS_WDATA10] = 0x13C,
143 + [PWRAP_DVFS_ADR11] = 0x140,
144 + [PWRAP_DVFS_WDATA11] = 0x144,
145 + [PWRAP_DVFS_ADR12] = 0x148,
146 + [PWRAP_DVFS_WDATA12] = 0x14C,
147 + [PWRAP_DVFS_ADR13] = 0x150,
148 + [PWRAP_DVFS_WDATA13] = 0x154,
149 + [PWRAP_DVFS_ADR14] = 0x158,
150 + [PWRAP_DVFS_WDATA14] = 0x15C,
151 + [PWRAP_DVFS_ADR15] = 0x160,
152 + [PWRAP_DVFS_WDATA15] = 0x164,
153 + [PWRAP_SPMINF_STA] = 0x168,
154 + [PWRAP_CIPHER_KEY_SEL] = 0x16C,
155 + [PWRAP_CIPHER_IV_SEL] = 0x170,
156 + [PWRAP_CIPHER_EN] = 0x174,
157 + [PWRAP_CIPHER_RDY] = 0x178,
158 + [PWRAP_CIPHER_MODE] = 0x17C,
159 + [PWRAP_CIPHER_SWRST] = 0x180,
160 + [PWRAP_DCM_EN] = 0x184,
161 + [PWRAP_DCM_DBC_PRD] = 0x188,
162 + [PWRAP_EXT_CK] = 0x18C,
163 + [PWRAP_ADC_CMD_ADDR] = 0x190,
164 + [PWRAP_PWRAP_ADC_CMD] = 0x194,
165 + [PWRAP_ADC_RDATA_ADDR] = 0x198,
166 + [PWRAP_GPS_STA] = 0x19C,
167 + [PWRAP_SW_RST] = 0x1A0,
168 + [PWRAP_DVFS_STEP_CTRL0] = 0x238,
169 + [PWRAP_DVFS_STEP_CTRL1] = 0x23C,
170 + [PWRAP_DVFS_STEP_CTRL2] = 0x240,
171 + [PWRAP_SPI2_CTRL] = 0x244,
172 +};
173 +
174 static int mt8173_regs[] = {
175 [PWRAP_MUX_SEL] = 0x0,
176 [PWRAP_WRAP_EN] = 0x4,
177 @@ -499,6 +641,7 @@ enum pmic_type {
178
179 enum pwrap_type {
180 PWRAP_MT2701,
181 + PWRAP_MT7622,
182 PWRAP_MT8135,
183 PWRAP_MT8173,
184 };
185 @@ -927,6 +1070,9 @@ static int pwrap_init_cipher(struct pmic_wrapper *wrp)
186 case PWRAP_MT8173:
187 pwrap_writel(wrp, 1, PWRAP_CIPHER_EN);
188 break;
189 + case PWRAP_MT7622:
190 + pwrap_writel(wrp, 0, PWRAP_CIPHER_EN);
191 + break;
192 }
193
194 /* Config cipher mode @PMIC */
195 @@ -1071,6 +1217,15 @@ static int pwrap_mt2701_init_soc_specific(struct pmic_wrapper *wrp)
196 return 0;
197 }
198
199 +static int pwrap_mt7622_init_soc_specific(struct pmic_wrapper *wrp)
200 +{
201 + pwrap_writel(wrp, 0, PWRAP_STAUPD_PRD);
202 + /* enable 2wire SPI master */
203 + pwrap_writel(wrp, 0x8000000, PWRAP_SPI2_CTRL);
204 +
205 + return 0;
206 +}
207 +
208 static int pwrap_init(struct pmic_wrapper *wrp)
209 {
210 int ret;
211 @@ -1242,6 +1397,18 @@ static const struct pmic_wrapper_type pwrap_mt2701 = {
212 .init_soc_specific = pwrap_mt2701_init_soc_specific,
213 };
214
215 +static const struct pmic_wrapper_type pwrap_mt7622 = {
216 + .regs = mt7622_regs,
217 + .type = PWRAP_MT7622,
218 + .arb_en_all = 0xff,
219 + .int_en_all = ~(u32)BIT(31),
220 + .spi_w = PWRAP_MAN_CMD_SPI_WRITE,
221 + .wdt_src = PWRAP_WDT_SRC_MASK_ALL,
222 + .has_bridge = 0,
223 + .init_reg_clock = pwrap_common_init_reg_clock,
224 + .init_soc_specific = pwrap_mt7622_init_soc_specific,
225 +};
226 +
227 static const struct pmic_wrapper_type pwrap_mt8135 = {
228 .regs = mt8135_regs,
229 .type = PWRAP_MT8135,
230 @@ -1271,6 +1438,9 @@ static const struct of_device_id of_pwrap_match_tbl[] = {
231 .compatible = "mediatek,mt2701-pwrap",
232 .data = &pwrap_mt2701,
233 }, {
234 + .compatible = "mediatek,mt7622-pwrap",
235 + .data = &pwrap_mt7622,
236 + }, {
237 .compatible = "mediatek,mt8135-pwrap",
238 .data = &pwrap_mt8135,
239 }, {
240 --
241 2.11.0
242
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