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[openwrt/staging/dedeckeh.git] / target / linux / mediatek / patches-4.14 / 0154-mmc-mediatek-add-async-fifo-and-data-tune-support.patch
1 From 830574225e621809600902b69bbdd563e67ef4eb Mon Sep 17 00:00:00 2001
2 From: Chaotian Jing <chaotian.jing@mediatek.com>
3 Date: Mon, 16 Oct 2017 09:46:33 +0800
4 Subject: [PATCH 154/224] mmc: mediatek: add async fifo and data tune support
5
6 mt2701/mt2712 supports async fifo & data tune, which can improve
7 host stability.
8
9 Signed-off-by: Chaotian Jing <chaotian.jing@mediatek.com>
10 Tested-by: Sean Wang <sean.wang@mediatek.com>
11 Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
12 ---
13 drivers/mmc/host/mtk-sd.c | 52 +++++++++++++++++++++++++++++++++++++++++++++--
14 1 file changed, 50 insertions(+), 2 deletions(-)
15
16 diff --git a/drivers/mmc/host/mtk-sd.c b/drivers/mmc/host/mtk-sd.c
17 index bcd83d6f2b86..8113bacc1540 100644
18 --- a/drivers/mmc/host/mtk-sd.c
19 +++ b/drivers/mmc/host/mtk-sd.c
20 @@ -74,6 +74,7 @@
21 #define MSDC_DMA_CFG 0x9c
22 #define MSDC_PATCH_BIT 0xb0
23 #define MSDC_PATCH_BIT1 0xb4
24 +#define MSDC_PATCH_BIT2 0xb8
25 #define MSDC_PAD_TUNE 0xec
26 #define MSDC_PAD_TUNE0 0xf0
27 #define PAD_DS_TUNE 0x188
28 @@ -216,11 +217,20 @@
29 #define MSDC_PATCH_BIT_SPCPUSH (0x1 << 29) /* RW */
30 #define MSDC_PATCH_BIT_DECRCTMO (0x1 << 30) /* RW */
31
32 +#define MSDC_PATCH_BIT2_CFGRESP (0x1 << 15) /* RW */
33 +#define MSDC_PATCH_BIT2_CFGCRCSTS (0x1 << 28) /* RW */
34 +#define MSDC_PB2_RESPWAIT (0x3 << 2) /* RW */
35 +#define MSDC_PB2_RESPSTSENSEL (0x7 << 16) /* RW */
36 +#define MSDC_PB2_CRCSTSENSEL (0x7 << 29) /* RW */
37 +
38 #define MSDC_PAD_TUNE_DATWRDLY (0x1f << 0) /* RW */
39 #define MSDC_PAD_TUNE_DATRRDLY (0x1f << 8) /* RW */
40 #define MSDC_PAD_TUNE_CMDRDLY (0x1f << 16) /* RW */
41 #define MSDC_PAD_TUNE_CMDRRDLY (0x1f << 22) /* RW */
42 #define MSDC_PAD_TUNE_CLKTDLY (0x1f << 27) /* RW */
43 +#define MSDC_PAD_TUNE_RXDLYSEL (0x1 << 15) /* RW */
44 +#define MSDC_PAD_TUNE_RD_SEL (0x1 << 13) /* RW */
45 +#define MSDC_PAD_TUNE_CMD_SEL (0x1 << 21) /* RW */
46
47 #define PAD_DS_TUNE_DLY1 (0x1f << 2) /* RW */
48 #define PAD_DS_TUNE_DLY2 (0x1f << 7) /* RW */
49 @@ -294,6 +304,7 @@ struct msdc_save_para {
50 u32 pad_tune;
51 u32 patch_bit0;
52 u32 patch_bit1;
53 + u32 patch_bit2;
54 u32 pad_ds_tune;
55 u32 pad_cmd_tune;
56 u32 emmc50_cfg0;
57 @@ -303,6 +314,8 @@ struct mtk_mmc_compatible {
58 u8 clk_div_bits;
59 bool hs400_tune; /* only used for MT8173 */
60 u32 pad_tune_reg;
61 + bool async_fifo;
62 + bool data_tune;
63 };
64
65 struct msdc_tune_para {
66 @@ -365,24 +378,32 @@ static const struct mtk_mmc_compatible mt8135_compat = {
67 .clk_div_bits = 8,
68 .hs400_tune = false,
69 .pad_tune_reg = MSDC_PAD_TUNE,
70 + .async_fifo = false,
71 + .data_tune = false,
72 };
73
74 static const struct mtk_mmc_compatible mt8173_compat = {
75 .clk_div_bits = 8,
76 .hs400_tune = true,
77 .pad_tune_reg = MSDC_PAD_TUNE,
78 + .async_fifo = false,
79 + .data_tune = false,
80 };
81
82 static const struct mtk_mmc_compatible mt2701_compat = {
83 .clk_div_bits = 12,
84 .hs400_tune = false,
85 .pad_tune_reg = MSDC_PAD_TUNE0,
86 + .async_fifo = true,
87 + .data_tune = true,
88 };
89
90 static const struct mtk_mmc_compatible mt2712_compat = {
91 .clk_div_bits = 12,
92 .hs400_tune = false,
93 .pad_tune_reg = MSDC_PAD_TUNE0,
94 + .async_fifo = true,
95 + .data_tune = true,
96 };
97
98 static const struct of_device_id msdc_of_ids[] = {
99 @@ -1252,8 +1273,29 @@ static void msdc_init_hw(struct msdc_host *host)
100 sdr_set_field(host->base + MSDC_IOCON, MSDC_IOCON_DDLSEL, 0);
101 writel(0x403c0046, host->base + MSDC_PATCH_BIT);
102 sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_CKGEN_MSDC_DLY_SEL, 1);
103 - writel(0xffff0089, host->base + MSDC_PATCH_BIT1);
104 + writel(0xffff4089, host->base + MSDC_PATCH_BIT1);
105 sdr_set_bits(host->base + EMMC50_CFG0, EMMC50_CFG_CFCSTS_SEL);
106 + if (host->dev_comp->async_fifo) {
107 + sdr_set_field(host->base + MSDC_PATCH_BIT2,
108 + MSDC_PB2_RESPWAIT, 3);
109 + sdr_set_field(host->base + MSDC_PATCH_BIT2,
110 + MSDC_PB2_RESPSTSENSEL, 2);
111 + sdr_set_field(host->base + MSDC_PATCH_BIT2,
112 + MSDC_PB2_CRCSTSENSEL, 2);
113 + /* use async fifo, then no need tune internal delay */
114 + sdr_clr_bits(host->base + MSDC_PATCH_BIT2,
115 + MSDC_PATCH_BIT2_CFGRESP);
116 + sdr_set_bits(host->base + MSDC_PATCH_BIT2,
117 + MSDC_PATCH_BIT2_CFGCRCSTS);
118 + }
119 +
120 + if (host->dev_comp->data_tune) {
121 + sdr_set_bits(host->base + tune_reg,
122 + MSDC_PAD_TUNE_RD_SEL | MSDC_PAD_TUNE_CMD_SEL);
123 + } else {
124 + /* choose clock tune */
125 + sdr_set_bits(host->base + tune_reg, MSDC_PAD_TUNE_RXDLYSEL);
126 + }
127
128 /* Configure to enable SDIO mode.
129 * it's must otherwise sdio cmd5 failed
130 @@ -1268,6 +1310,8 @@ static void msdc_init_hw(struct msdc_host *host)
131
132 host->def_tune_para.iocon = readl(host->base + MSDC_IOCON);
133 host->def_tune_para.pad_tune = readl(host->base + tune_reg);
134 + host->saved_tune_para.iocon = readl(host->base + MSDC_IOCON);
135 + host->saved_tune_para.pad_tune = readl(host->base + tune_reg);
136 dev_dbg(host->dev, "init hardware done!");
137 }
138
139 @@ -1480,7 +1524,7 @@ static int msdc_tune_response(struct mmc_host *mmc, u32 opcode)
140 final_fall_delay.final_phase);
141 final_delay = final_fall_delay.final_phase;
142 }
143 - if (host->hs200_cmd_int_delay)
144 + if (host->dev_comp->async_fifo || host->hs200_cmd_int_delay)
145 goto skip_internal;
146
147 for (i = 0; i < PAD_DELAY_MAX; i++) {
148 @@ -1638,6 +1682,8 @@ static int msdc_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios)
149 host->hs400_mode = true;
150
151 writel(host->hs400_ds_delay, host->base + PAD_DS_TUNE);
152 + /* hs400 mode must set it to 0 */
153 + sdr_clr_bits(host->base + MSDC_PATCH_BIT2, MSDC_PATCH_BIT2_CFGCRCSTS);
154 return 0;
155 }
156
157 @@ -1876,6 +1922,7 @@ static void msdc_save_reg(struct msdc_host *host)
158 host->save_para.pad_tune = readl(host->base + tune_reg);
159 host->save_para.patch_bit0 = readl(host->base + MSDC_PATCH_BIT);
160 host->save_para.patch_bit1 = readl(host->base + MSDC_PATCH_BIT1);
161 + host->save_para.patch_bit2 = readl(host->base + MSDC_PATCH_BIT2);
162 host->save_para.pad_ds_tune = readl(host->base + PAD_DS_TUNE);
163 host->save_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE);
164 host->save_para.emmc50_cfg0 = readl(host->base + EMMC50_CFG0);
165 @@ -1891,6 +1938,7 @@ static void msdc_restore_reg(struct msdc_host *host)
166 writel(host->save_para.pad_tune, host->base + tune_reg);
167 writel(host->save_para.patch_bit0, host->base + MSDC_PATCH_BIT);
168 writel(host->save_para.patch_bit1, host->base + MSDC_PATCH_BIT1);
169 + writel(host->save_para.patch_bit2, host->base + MSDC_PATCH_BIT2);
170 writel(host->save_para.pad_ds_tune, host->base + PAD_DS_TUNE);
171 writel(host->save_para.pad_cmd_tune, host->base + PAD_CMD_TUNE);
172 writel(host->save_para.emmc50_cfg0, host->base + EMMC50_CFG0);
173 --
174 2.11.0
175
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