1 From fd1a1eabf2473e769b5cafc704e0336d11f61961 Mon Sep 17 00:00:00 2001
2 From: RogerCC Lin <rogercc.lin@mediatek.com>
3 Date: Thu, 30 Nov 2017 22:10:44 +0800
4 Subject: [PATCH 166/224] mtd: nand: mtk: Support different MTK NAND flash
7 MT7622 uses an MTK's earlier NAND flash controller IP which support
8 different sector size, max spare size per sector and paraity bits...,
9 some register's offset and definition also been changed in the NAND
10 flash controller, this patch is the preparation to support MT7622
11 NAND flash controller.
13 MT7622 NFC and ECC engine are similar to MT2701's, except below
15 (1)MT7622 NFC's max sector size(ECC data size) is 512 bytes, and
16 MT2701's is 1024, and MT7622's max sector number is 8.
17 (2)The parity bit of MT7622 is 13, MT2701 is 14.
18 (3)MT7622 ECC supports less ECC strength, max to 16 bit ecc strength.
19 (4)MT7622 supports less spare size per sector, max spare size per
21 (5)Some register's offset are different, include ECC_ENCIRQ_EN,
22 ECC_ENCIRQ_STA, ECC_DECDONE, ECC_DECIRQ_EN and ECC_DECIRQ_STA.
23 (6)ENC_MODE of ECC_ENCCNFG register is moved from bit 5-6 to bit 4-5.
25 Signed-off-by: RogerCC Lin <rogercc.lin@mediatek.com>
26 Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
28 drivers/mtd/nand/mtk_ecc.c | 100 ++++++++++++++++++++++++++++++--------------
29 drivers/mtd/nand/mtk_ecc.h | 3 +-
30 drivers/mtd/nand/mtk_nand.c | 27 ++++++++----
31 3 files changed, 89 insertions(+), 41 deletions(-)
33 --- a/drivers/mtd/nand/mtk_ecc.c
34 +++ b/drivers/mtd/nand/mtk_ecc.c
37 #define ECC_ENCCON (0x00)
38 #define ECC_ENCCNFG (0x04)
39 -#define ECC_MODE_SHIFT (5)
40 #define ECC_MS_SHIFT (16)
41 #define ECC_ENCDIADDR (0x08)
42 #define ECC_ENCIDLE (0x0C)
43 -#define ECC_ENCIRQ_EN (0x80)
44 -#define ECC_ENCIRQ_STA (0x84)
45 #define ECC_DECCON (0x100)
46 #define ECC_DECCNFG (0x104)
47 #define DEC_EMPTY_EN BIT(31)
48 #define DEC_CNFG_CORRECT (0x3 << 12)
49 #define ECC_DECIDLE (0x10C)
50 #define ECC_DECENUM0 (0x114)
51 -#define ECC_DECDONE (0x124)
52 -#define ECC_DECIRQ_EN (0x200)
53 -#define ECC_DECIRQ_STA (0x204)
55 #define ECC_TIMEOUT (500000)
57 #define ECC_IDLE_REG(op) ((op) == ECC_ENCODE ? ECC_ENCIDLE : ECC_DECIDLE)
58 #define ECC_CTL_REG(op) ((op) == ECC_ENCODE ? ECC_ENCCON : ECC_DECCON)
59 -#define ECC_IRQ_REG(op) ((op) == ECC_ENCODE ? \
60 - ECC_ENCIRQ_EN : ECC_DECIRQ_EN)
64 const u8 *ecc_strength;
65 + const u32 *ecc_regs;
67 - u32 encode_parity_reg0;
73 @@ -89,6 +83,33 @@ static const u8 ecc_strength_mt2712[] =
74 40, 44, 48, 52, 56, 60, 68, 72, 80
86 +static int mt2701_ecc_regs[] = {
87 + [ECC_ENCPAR00] = 0x10,
88 + [ECC_ENCIRQ_EN] = 0x80,
89 + [ECC_ENCIRQ_STA] = 0x84,
90 + [ECC_DECDONE] = 0x124,
91 + [ECC_DECIRQ_EN] = 0x200,
92 + [ECC_DECIRQ_STA] = 0x204,
95 +static int mt2712_ecc_regs[] = {
96 + [ECC_ENCPAR00] = 0x300,
97 + [ECC_ENCIRQ_EN] = 0x80,
98 + [ECC_ENCIRQ_STA] = 0x84,
99 + [ECC_DECDONE] = 0x124,
100 + [ECC_DECIRQ_EN] = 0x200,
101 + [ECC_DECIRQ_STA] = 0x204,
104 static inline void mtk_ecc_wait_idle(struct mtk_ecc *ecc,
105 enum mtk_ecc_operation op)
107 @@ -107,32 +128,30 @@ static inline void mtk_ecc_wait_idle(str
108 static irqreturn_t mtk_ecc_irq(int irq, void *id)
110 struct mtk_ecc *ecc = id;
111 - enum mtk_ecc_operation op;
114 - dec = readw(ecc->regs + ECC_DECIRQ_STA) & ECC_IRQ_EN;
115 + dec = readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECIRQ_STA])
119 - dec = readw(ecc->regs + ECC_DECDONE);
120 + dec = readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECDONE]);
121 if (dec & ecc->sectors) {
123 * Clear decode IRQ status once again to ensure that
124 * there will be no extra IRQ.
126 - readw(ecc->regs + ECC_DECIRQ_STA);
127 + readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECIRQ_STA]);
129 complete(&ecc->done);
134 - enc = readl(ecc->regs + ECC_ENCIRQ_STA) & ECC_IRQ_EN;
137 + enc = readl(ecc->regs + ecc->caps->ecc_regs[ECC_ENCIRQ_STA])
140 complete(&ecc->done);
148 @@ -160,7 +179,7 @@ static int mtk_ecc_config(struct mtk_ecc
149 /* configure ECC encoder (in bits) */
150 enc_sz = config->len << 3;
152 - reg = ecc_bit | (config->mode << ECC_MODE_SHIFT);
153 + reg = ecc_bit | (config->mode << ecc->caps->ecc_mode_shift);
154 reg |= (enc_sz << ECC_MS_SHIFT);
155 writel(reg, ecc->regs + ECC_ENCCNFG);
157 @@ -171,9 +190,9 @@ static int mtk_ecc_config(struct mtk_ecc
159 /* configure ECC decoder (in bits) */
160 dec_sz = (config->len << 3) +
161 - config->strength * ECC_PARITY_BITS;
162 + config->strength * ecc->caps->parity_bits;
164 - reg = ecc_bit | (config->mode << ECC_MODE_SHIFT);
165 + reg = ecc_bit | (config->mode << ecc->caps->ecc_mode_shift);
166 reg |= (dec_sz << ECC_MS_SHIFT) | DEC_CNFG_CORRECT;
168 writel(reg, ecc->regs + ECC_DECCNFG);
169 @@ -291,7 +310,12 @@ int mtk_ecc_enable(struct mtk_ecc *ecc,
171 if (ecc->caps->pg_irq_sel && config->mode == ECC_NFI_MODE)
172 reg_val |= ECC_PG_IRQ_SEL;
173 - writew(reg_val, ecc->regs + ECC_IRQ_REG(op));
174 + if (op == ECC_ENCODE)
175 + writew(reg_val, ecc->regs +
176 + ecc->caps->ecc_regs[ECC_ENCIRQ_EN]);
178 + writew(reg_val, ecc->regs +
179 + ecc->caps->ecc_regs[ECC_DECIRQ_EN]);
182 writew(ECC_OP_ENABLE, ecc->regs + ECC_CTL_REG(op));
183 @@ -310,13 +334,17 @@ void mtk_ecc_disable(struct mtk_ecc *ecc
186 mtk_ecc_wait_idle(ecc, op);
187 - if (op == ECC_DECODE)
188 + if (op == ECC_DECODE) {
190 * Clear decode IRQ status in case there is a timeout to wait
193 - readw(ecc->regs + ECC_DECIRQ_STA);
194 - writew(0, ecc->regs + ECC_IRQ_REG(op));
195 + readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECDONE]);
196 + writew(0, ecc->regs + ecc->caps->ecc_regs[ECC_DECIRQ_EN]);
198 + writew(0, ecc->regs + ecc->caps->ecc_regs[ECC_ENCIRQ_EN]);
201 writew(ECC_OP_DISABLE, ecc->regs + ECC_CTL_REG(op));
203 mutex_unlock(&ecc->lock);
204 @@ -367,11 +395,11 @@ int mtk_ecc_encode(struct mtk_ecc *ecc,
205 mtk_ecc_wait_idle(ecc, ECC_ENCODE);
207 /* Program ECC bytes to OOB: per sector oob = FDM + ECC + SPARE */
208 - len = (config->strength * ECC_PARITY_BITS + 7) >> 3;
209 + len = (config->strength * ecc->caps->parity_bits + 7) >> 3;
211 /* write the parity bytes generated by the ECC back to temp buffer */
212 __ioread32_copy(ecc->eccdata,
213 - ecc->regs + ecc->caps->encode_parity_reg0,
214 + ecc->regs + ecc->caps->ecc_regs[ECC_ENCPAR00],
217 /* copy into possibly unaligned OOB region with actual length */
218 @@ -404,19 +432,29 @@ void mtk_ecc_adjust_strength(struct mtk_
220 EXPORT_SYMBOL(mtk_ecc_adjust_strength);
222 +unsigned int mtk_ecc_get_parity_bits(struct mtk_ecc *ecc)
224 + return ecc->caps->parity_bits;
226 +EXPORT_SYMBOL(mtk_ecc_get_parity_bits);
228 static const struct mtk_ecc_caps mtk_ecc_caps_mt2701 = {
230 .ecc_strength = ecc_strength_mt2701,
231 + .ecc_regs = mt2701_ecc_regs,
232 .num_ecc_strength = 20,
233 - .encode_parity_reg0 = 0x10,
234 + .ecc_mode_shift = 5,
239 static const struct mtk_ecc_caps mtk_ecc_caps_mt2712 = {
241 .ecc_strength = ecc_strength_mt2712,
242 + .ecc_regs = mt2712_ecc_regs,
243 .num_ecc_strength = 23,
244 - .encode_parity_reg0 = 0x300,
245 + .ecc_mode_shift = 5,
250 @@ -452,7 +490,7 @@ static int mtk_ecc_probe(struct platform
252 max_eccdata_size = ecc->caps->num_ecc_strength - 1;
253 max_eccdata_size = ecc->caps->ecc_strength[max_eccdata_size];
254 - max_eccdata_size = (max_eccdata_size * ECC_PARITY_BITS + 7) >> 3;
255 + max_eccdata_size = (max_eccdata_size * ecc->caps->parity_bits + 7) >> 3;
256 max_eccdata_size = round_up(max_eccdata_size, 4);
257 ecc->eccdata = devm_kzalloc(dev, max_eccdata_size, GFP_KERNEL);
259 --- a/drivers/mtd/nand/mtk_ecc.h
260 +++ b/drivers/mtd/nand/mtk_ecc.h
263 #include <linux/types.h>
265 -#define ECC_PARITY_BITS (14)
267 enum mtk_ecc_mode {ECC_DMA_MODE = 0, ECC_NFI_MODE = 1};
268 enum mtk_ecc_operation {ECC_ENCODE, ECC_DECODE};
270 @@ -43,6 +41,7 @@ int mtk_ecc_wait_done(struct mtk_ecc *,
271 int mtk_ecc_enable(struct mtk_ecc *, struct mtk_ecc_config *);
272 void mtk_ecc_disable(struct mtk_ecc *);
273 void mtk_ecc_adjust_strength(struct mtk_ecc *ecc, u32 *p);
274 +unsigned int mtk_ecc_get_parity_bits(struct mtk_ecc *ecc);
276 struct mtk_ecc *of_mtk_ecc_get(struct device_node *);
277 void mtk_ecc_release(struct mtk_ecc *);
278 --- a/drivers/mtd/nand/mtk_nand.c
279 +++ b/drivers/mtd/nand/mtk_nand.c
282 #define MTK_TIMEOUT (500000)
283 #define MTK_RESET_TIMEOUT (1000000)
284 -#define MTK_MAX_SECTOR (16)
285 #define MTK_NAND_MAX_NSELS (2)
286 #define MTK_NFC_MIN_SPARE (16)
287 #define ACCTIMING(tpoecs, tprecs, tc2r, tw2r, twh, twst, trlt) \
288 @@ -109,6 +108,8 @@ struct mtk_nfc_caps {
290 u8 pageformat_spare_shift;
293 + u32 max_sector_size;
296 struct mtk_nfc_bad_mark_ctl {
297 @@ -450,7 +451,7 @@ static inline u8 mtk_nfc_read_byte(struc
298 * set to max sector to allow the HW to continue reading over
301 - reg = (MTK_MAX_SECTOR << CON_SEC_SHIFT) | CON_BRD;
302 + reg = (nfc->caps->max_sector << CON_SEC_SHIFT) | CON_BRD;
303 nfi_writel(nfc, reg, NFI_CON);
305 /* trigger to fetch data */
306 @@ -481,7 +482,7 @@ static void mtk_nfc_write_byte(struct mt
307 reg = nfi_readw(nfc, NFI_CNFG) | CNFG_BYTE_RW;
308 nfi_writew(nfc, reg, NFI_CNFG);
310 - reg = MTK_MAX_SECTOR << CON_SEC_SHIFT | CON_BWR;
311 + reg = nfc->caps->max_sector << CON_SEC_SHIFT | CON_BWR;
312 nfi_writel(nfc, reg, NFI_CON);
314 nfi_writew(nfc, STAR_EN, NFI_STRDATA);
315 @@ -1125,9 +1126,11 @@ static void mtk_nfc_set_fdm(struct mtk_n
317 struct nand_chip *nand = mtd_to_nand(mtd);
318 struct mtk_nfc_nand_chip *chip = to_mtk_nand(nand);
319 + struct mtk_nfc *nfc = nand_get_controller_data(nand);
322 - ecc_bytes = DIV_ROUND_UP(nand->ecc.strength * ECC_PARITY_BITS, 8);
323 + ecc_bytes = DIV_ROUND_UP(nand->ecc.strength *
324 + mtk_ecc_get_parity_bits(nfc->ecc), 8);
326 fdm->reg_size = chip->spare_per_sector - ecc_bytes;
327 if (fdm->reg_size > NFI_FDM_MAX_SIZE)
328 @@ -1207,7 +1210,8 @@ static int mtk_nfc_ecc_init(struct devic
329 * this controller only supports 512 and 1024 sizes
331 if (nand->ecc.size < 1024) {
332 - if (mtd->writesize > 512) {
333 + if (mtd->writesize > 512 &&
334 + nfc->caps->max_sector_size > 512) {
335 nand->ecc.size = 1024;
336 nand->ecc.strength <<= 1;
338 @@ -1222,7 +1226,8 @@ static int mtk_nfc_ecc_init(struct devic
341 /* calculate oob bytes except ecc parity data */
342 - free = ((nand->ecc.strength * ECC_PARITY_BITS) + 7) >> 3;
343 + free = (nand->ecc.strength * mtk_ecc_get_parity_bits(nfc->ecc)
348 @@ -1232,10 +1237,12 @@ static int mtk_nfc_ecc_init(struct devic
350 if (free > NFI_FDM_MAX_SIZE) {
351 spare -= NFI_FDM_MAX_SIZE;
352 - nand->ecc.strength = (spare << 3) / ECC_PARITY_BITS;
353 + nand->ecc.strength = (spare << 3) /
354 + mtk_ecc_get_parity_bits(nfc->ecc);
355 } else if (free < 0) {
356 spare -= NFI_FDM_MIN_SIZE;
357 - nand->ecc.strength = (spare << 3) / ECC_PARITY_BITS;
358 + nand->ecc.strength = (spare << 3) /
359 + mtk_ecc_get_parity_bits(nfc->ecc);
363 @@ -1388,6 +1395,8 @@ static const struct mtk_nfc_caps mtk_nfc
364 .num_spare_size = 16,
365 .pageformat_spare_shift = 4,
368 + .max_sector_size = 1024,
371 static const struct mtk_nfc_caps mtk_nfc_caps_mt2712 = {
372 @@ -1395,6 +1404,8 @@ static const struct mtk_nfc_caps mtk_nfc
373 .num_spare_size = 19,
374 .pageformat_spare_shift = 16,
377 + .max_sector_size = 1024,
380 static const struct of_device_id mtk_nfc_id_table[] = {