1 From d5b391bb7208c8a7b6b874c1357d3cd110537167 Mon Sep 17 00:00:00 2001
2 From: Ryder Lee <ryder.lee@mediatek.com>
3 Date: Tue, 2 Jan 2018 19:47:21 +0800
4 Subject: [PATCH 183/224] ASoC: mediatek: update clock related properties of
7 Add 'assigned-clocks*' properties which are used to initialize default
8 domain sources of audio system. we could configure different sets of
9 input clocks through DTS now. Hence driver no longer cares about that.
11 Also we change some 'clock-names' to make them more generic so that
12 other chips can reuse gracefully.
14 Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
15 Signed-off-by: Mark Brown <broonie@kernel.org>
17 .../devicetree/bindings/sound/mt2701-afe-pcm.txt | 207 +++++++++------------
18 1 file changed, 91 insertions(+), 116 deletions(-)
20 --- a/Documentation/devicetree/bindings/sound/mt2701-afe-pcm.txt
21 +++ b/Documentation/devicetree/bindings/sound/mt2701-afe-pcm.txt
22 @@ -6,51 +6,44 @@ Required properties:
23 - interrupts: should contain AFE and ASYS interrupts
24 - interrupt-names: should be "afe" and "asys"
25 - power-domains: should define the power domain
26 +- clocks: Must contain an entry for each entry in clock-names
27 + See ../clocks/clock-bindings.txt for details
28 - clock-names: should have these clock names:
29 - "infra_sys_audio_clk",
32 - "top_audio_mux1_div",
33 - "top_audio_mux2_div",
34 - "top_audio_48k_timing",
35 - "top_audio_44k_timing",
36 - "top_audpll_mux_sel",
40 - "top_hadds2_pll_98M",
41 - "top_hadds2_pll_294M",
47 - "top_audintbus_sel",
50 - "top_aud_k1_src_sel",
51 - "top_aud_k2_src_sel",
52 - "top_aud_k3_src_sel",
53 - "top_aud_k4_src_sel",
54 - "top_aud_k5_src_sel",
55 - "top_aud_k6_src_sel",
56 - "top_aud_k1_src_div",
57 - "top_aud_k2_src_div",
58 - "top_aud_k3_src_div",
59 - "top_aud_k4_src_div",
60 - "top_aud_k5_src_div",
61 - "top_aud_k6_src_div",
62 - "top_aud_i2s1_mclk",
63 - "top_aud_i2s2_mclk",
64 - "top_aud_i2s3_mclk",
65 - "top_aud_i2s4_mclk",
66 - "top_aud_i2s5_mclk",
67 - "top_aud_i2s6_mclk",
98 + "audio_afe_conn_pd",
102 +- assigned-clocks: list of input clocks and dividers for the audio system.
103 + See ../clocks/clock-bindings.txt for details.
104 +- assigned-clocks-parents: parent of input clocks of assigned clocks.
105 +- assigned-clock-rates: list of clock frequencies of assigned clocks.
109 @@ -62,93 +55,75 @@ Example:
110 <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>;
111 interrupt-names = "afe", "asys";
112 power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
113 - clocks = <&infracfg CLK_INFRA_AUDIO>,
114 - <&topckgen CLK_TOP_AUD_MUX1_SEL>,
115 + clocks = <&topckgen CLK_TOP_AUD_MUX1_SEL>,
116 <&topckgen CLK_TOP_AUD_MUX2_SEL>,
117 - <&topckgen CLK_TOP_AUD_MUX1_DIV>,
118 - <&topckgen CLK_TOP_AUD_MUX2_DIV>,
119 - <&topckgen CLK_TOP_AUD_48K_TIMING>,
120 - <&topckgen CLK_TOP_AUD_44K_TIMING>,
121 - <&topckgen CLK_TOP_AUDPLL_MUX_SEL>,
122 - <&topckgen CLK_TOP_APLL_SEL>,
123 - <&topckgen CLK_TOP_AUD1PLL_98M>,
124 - <&topckgen CLK_TOP_AUD2PLL_90M>,
125 - <&topckgen CLK_TOP_HADDS2PLL_98M>,
126 - <&topckgen CLK_TOP_HADDS2PLL_294M>,
127 - <&topckgen CLK_TOP_AUDPLL>,
128 - <&topckgen CLK_TOP_AUDPLL_D4>,
129 - <&topckgen CLK_TOP_AUDPLL_D8>,
130 - <&topckgen CLK_TOP_AUDPLL_D16>,
131 - <&topckgen CLK_TOP_AUDPLL_D24>,
132 - <&topckgen CLK_TOP_AUDINTBUS_SEL>,
134 - <&topckgen CLK_TOP_SYSPLL1_D4>,
135 <&topckgen CLK_TOP_AUD_K1_SRC_SEL>,
136 <&topckgen CLK_TOP_AUD_K2_SRC_SEL>,
137 <&topckgen CLK_TOP_AUD_K3_SRC_SEL>,
138 <&topckgen CLK_TOP_AUD_K4_SRC_SEL>,
139 - <&topckgen CLK_TOP_AUD_K5_SRC_SEL>,
140 - <&topckgen CLK_TOP_AUD_K6_SRC_SEL>,
141 <&topckgen CLK_TOP_AUD_K1_SRC_DIV>,
142 <&topckgen CLK_TOP_AUD_K2_SRC_DIV>,
143 <&topckgen CLK_TOP_AUD_K3_SRC_DIV>,
144 <&topckgen CLK_TOP_AUD_K4_SRC_DIV>,
145 - <&topckgen CLK_TOP_AUD_K5_SRC_DIV>,
146 - <&topckgen CLK_TOP_AUD_K6_SRC_DIV>,
147 <&topckgen CLK_TOP_AUD_I2S1_MCLK>,
148 <&topckgen CLK_TOP_AUD_I2S2_MCLK>,
149 <&topckgen CLK_TOP_AUD_I2S3_MCLK>,
150 <&topckgen CLK_TOP_AUD_I2S4_MCLK>,
151 - <&topckgen CLK_TOP_AUD_I2S5_MCLK>,
152 - <&topckgen CLK_TOP_AUD_I2S6_MCLK>,
153 - <&topckgen CLK_TOP_ASM_M_SEL>,
154 - <&topckgen CLK_TOP_ASM_H_SEL>,
155 - <&topckgen CLK_TOP_UNIVPLL2_D4>,
156 - <&topckgen CLK_TOP_UNIVPLL2_D2>,
157 - <&topckgen CLK_TOP_SYSPLL_D5>;
158 + <&audiosys CLK_AUD_I2SO1>,
159 + <&audiosys CLK_AUD_I2SO2>,
160 + <&audiosys CLK_AUD_I2SO3>,
161 + <&audiosys CLK_AUD_I2SO4>,
162 + <&audiosys CLK_AUD_I2SIN1>,
163 + <&audiosys CLK_AUD_I2SIN2>,
164 + <&audiosys CLK_AUD_I2SIN3>,
165 + <&audiosys CLK_AUD_I2SIN4>,
166 + <&audiosys CLK_AUD_ASRCO1>,
167 + <&audiosys CLK_AUD_ASRCO2>,
168 + <&audiosys CLK_AUD_ASRCO3>,
169 + <&audiosys CLK_AUD_ASRCO4>,
170 + <&audiosys CLK_AUD_AFE>,
171 + <&audiosys CLK_AUD_AFE_CONN>,
172 + <&audiosys CLK_AUD_A1SYS>,
173 + <&audiosys CLK_AUD_A2SYS>,
174 + <&audiosys CLK_AUD_AFE_MRGIF>;
176 - clock-names = "infra_sys_audio_clk",
177 - "top_audio_mux1_sel",
178 + clock-names = "top_audio_mux1_sel",
179 "top_audio_mux2_sel",
180 - "top_audio_mux1_div",
181 - "top_audio_mux2_div",
182 - "top_audio_48k_timing",
183 - "top_audio_44k_timing",
184 - "top_audpll_mux_sel",
186 - "top_aud1_pll_98M",
187 - "top_aud2_pll_90M",
188 - "top_hadds2_pll_98M",
189 - "top_hadds2_pll_294M",
195 - "top_audintbus_sel",
198 - "top_aud_k1_src_sel",
199 - "top_aud_k2_src_sel",
200 - "top_aud_k3_src_sel",
201 - "top_aud_k4_src_sel",
202 - "top_aud_k5_src_sel",
203 - "top_aud_k6_src_sel",
204 - "top_aud_k1_src_div",
205 - "top_aud_k2_src_div",
206 - "top_aud_k3_src_div",
207 - "top_aud_k4_src_div",
208 - "top_aud_k5_src_div",
209 - "top_aud_k6_src_div",
210 - "top_aud_i2s1_mclk",
211 - "top_aud_i2s2_mclk",
212 - "top_aud_i2s3_mclk",
213 - "top_aud_i2s4_mclk",
214 - "top_aud_i2s5_mclk",
215 - "top_aud_i2s6_mclk",
246 + "audio_afe_conn_pd",
251 + assigned-clocks = <&topckgen CLK_TOP_AUD_MUX1_SEL>,
252 + <&topckgen CLK_TOP_AUD_MUX2_SEL>,
253 + <&topckgen CLK_TOP_AUD_MUX1_DIV>,
254 + <&topckgen CLK_TOP_AUD_MUX2_DIV>;
255 + assigned-clock-parents = <&topckgen CLK_TOP_AUD1PLL_98M>,
256 + <&topckgen CLK_TOP_AUD2PLL_90M>;
257 + assigned-clock-rates = <0>, <0>, <49152000>, <45158400>;