1 From 018219d340c0f7a10098683b8a4733618ea76ba3 Mon Sep 17 00:00:00 2001
2 From: Ryder Lee <ryder.lee@mediatek.com>
3 Date: Thu, 4 Jan 2018 15:44:09 +0800
4 Subject: [PATCH 186/224] ASoC: mediatek: update MT2701 AFE documentation to
7 As the new MFD parent is in place, modify MT2701 AFE documentation to
8 adapt it. Also add three core clocks in example.
10 Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
11 Signed-off-by: Mark Brown <broonie@kernel.org>
13 .../devicetree/bindings/sound/mt2701-afe-pcm.txt | 171 +++++++++++----------
14 1 file changed, 93 insertions(+), 78 deletions(-)
16 --- a/Documentation/devicetree/bindings/sound/mt2701-afe-pcm.txt
17 +++ b/Documentation/devicetree/bindings/sound/mt2701-afe-pcm.txt
18 @@ -2,15 +2,17 @@ Mediatek AFE PCM controller for mt2701
21 - compatible = "mediatek,mt2701-audio";
22 -- reg: register location and size
23 - interrupts: should contain AFE and ASYS interrupts
24 - interrupt-names: should be "afe" and "asys"
25 - power-domains: should define the power domain
26 - clocks: Must contain an entry for each entry in clock-names
27 See ../clocks/clock-bindings.txt for details
28 - clock-names: should have these clock names:
29 + "infra_sys_audio_clk",
32 + "top_audio_a1sys_hp",
33 + "top_audio_a2sys_hp",
37 @@ -45,85 +47,98 @@ Required properties:
38 - assigned-clocks-parents: parent of input clocks of assigned clocks.
39 - assigned-clock-rates: list of clock frequencies of assigned clocks.
41 +Must be a subnode of MediaTek audsys device tree node.
42 +See ../arm/mediatek/mediatek,audsys.txt for details about the parent node.
46 - afe: mt2701-afe-pcm@11220000 {
47 - compatible = "mediatek,mt2701-audio";
48 - reg = <0 0x11220000 0 0x2000>,
49 - <0 0x112A0000 0 0x20000>;
50 - interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>,
51 - <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>;
52 - interrupt-names = "afe", "asys";
53 - power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
54 - clocks = <&topckgen CLK_TOP_AUD_MUX1_SEL>,
55 - <&topckgen CLK_TOP_AUD_MUX2_SEL>,
56 - <&topckgen CLK_TOP_AUD_K1_SRC_SEL>,
57 - <&topckgen CLK_TOP_AUD_K2_SRC_SEL>,
58 - <&topckgen CLK_TOP_AUD_K3_SRC_SEL>,
59 - <&topckgen CLK_TOP_AUD_K4_SRC_SEL>,
60 - <&topckgen CLK_TOP_AUD_K1_SRC_DIV>,
61 - <&topckgen CLK_TOP_AUD_K2_SRC_DIV>,
62 - <&topckgen CLK_TOP_AUD_K3_SRC_DIV>,
63 - <&topckgen CLK_TOP_AUD_K4_SRC_DIV>,
64 - <&topckgen CLK_TOP_AUD_I2S1_MCLK>,
65 - <&topckgen CLK_TOP_AUD_I2S2_MCLK>,
66 - <&topckgen CLK_TOP_AUD_I2S3_MCLK>,
67 - <&topckgen CLK_TOP_AUD_I2S4_MCLK>,
68 - <&audiosys CLK_AUD_I2SO1>,
69 - <&audiosys CLK_AUD_I2SO2>,
70 - <&audiosys CLK_AUD_I2SO3>,
71 - <&audiosys CLK_AUD_I2SO4>,
72 - <&audiosys CLK_AUD_I2SIN1>,
73 - <&audiosys CLK_AUD_I2SIN2>,
74 - <&audiosys CLK_AUD_I2SIN3>,
75 - <&audiosys CLK_AUD_I2SIN4>,
76 - <&audiosys CLK_AUD_ASRCO1>,
77 - <&audiosys CLK_AUD_ASRCO2>,
78 - <&audiosys CLK_AUD_ASRCO3>,
79 - <&audiosys CLK_AUD_ASRCO4>,
80 - <&audiosys CLK_AUD_AFE>,
81 - <&audiosys CLK_AUD_AFE_CONN>,
82 - <&audiosys CLK_AUD_A1SYS>,
83 - <&audiosys CLK_AUD_A2SYS>,
84 - <&audiosys CLK_AUD_AFE_MRGIF>;
86 - clock-names = "top_audio_mux1_sel",
87 - "top_audio_mux2_sel",
113 - "audio_afe_conn_pd",
118 - assigned-clocks = <&topckgen CLK_TOP_AUD_MUX1_SEL>,
119 - <&topckgen CLK_TOP_AUD_MUX2_SEL>,
120 - <&topckgen CLK_TOP_AUD_MUX1_DIV>,
121 - <&topckgen CLK_TOP_AUD_MUX2_DIV>;
122 - assigned-clock-parents = <&topckgen CLK_TOP_AUD1PLL_98M>,
123 - <&topckgen CLK_TOP_AUD2PLL_90M>;
124 - assigned-clock-rates = <0>, <0>, <49152000>, <45158400>;
125 + audsys: audio-subsystem@11220000 {
126 + compatible = "mediatek,mt2701-audsys", "syscon", "simple-mfd";
129 + afe: audio-controller {
130 + compatible = "mediatek,mt2701-audio";
131 + interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>,
132 + <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>;
133 + interrupt-names = "afe", "asys";
134 + power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
136 + clocks = <&infracfg CLK_INFRA_AUDIO>,
137 + <&topckgen CLK_TOP_AUD_MUX1_SEL>,
138 + <&topckgen CLK_TOP_AUD_MUX2_SEL>,
139 + <&topckgen CLK_TOP_AUD_48K_TIMING>,
140 + <&topckgen CLK_TOP_AUD_44K_TIMING>,
141 + <&topckgen CLK_TOP_AUD_K1_SRC_SEL>,
142 + <&topckgen CLK_TOP_AUD_K2_SRC_SEL>,
143 + <&topckgen CLK_TOP_AUD_K3_SRC_SEL>,
144 + <&topckgen CLK_TOP_AUD_K4_SRC_SEL>,
145 + <&topckgen CLK_TOP_AUD_K1_SRC_DIV>,
146 + <&topckgen CLK_TOP_AUD_K2_SRC_DIV>,
147 + <&topckgen CLK_TOP_AUD_K3_SRC_DIV>,
148 + <&topckgen CLK_TOP_AUD_K4_SRC_DIV>,
149 + <&topckgen CLK_TOP_AUD_I2S1_MCLK>,
150 + <&topckgen CLK_TOP_AUD_I2S2_MCLK>,
151 + <&topckgen CLK_TOP_AUD_I2S3_MCLK>,
152 + <&topckgen CLK_TOP_AUD_I2S4_MCLK>,
153 + <&audsys CLK_AUD_I2SO1>,
154 + <&audsys CLK_AUD_I2SO2>,
155 + <&audsys CLK_AUD_I2SO3>,
156 + <&audsys CLK_AUD_I2SO4>,
157 + <&audsys CLK_AUD_I2SIN1>,
158 + <&audsys CLK_AUD_I2SIN2>,
159 + <&audsys CLK_AUD_I2SIN3>,
160 + <&audsys CLK_AUD_I2SIN4>,
161 + <&audsys CLK_AUD_ASRCO1>,
162 + <&audsys CLK_AUD_ASRCO2>,
163 + <&audsys CLK_AUD_ASRCO3>,
164 + <&audsys CLK_AUD_ASRCO4>,
165 + <&audsys CLK_AUD_AFE>,
166 + <&audsys CLK_AUD_AFE_CONN>,
167 + <&audsys CLK_AUD_A1SYS>,
168 + <&audsys CLK_AUD_A2SYS>,
169 + <&audsys CLK_AUD_AFE_MRGIF>;
171 + clock-names = "infra_sys_audio_clk",
172 + "top_audio_mux1_sel",
173 + "top_audio_mux2_sel",
174 + "top_audio_a1sys_hp",
175 + "top_audio_a2sys_hp",
201 + "audio_afe_conn_pd",
206 + assigned-clocks = <&topckgen CLK_TOP_AUD_MUX1_SEL>,
207 + <&topckgen CLK_TOP_AUD_MUX2_SEL>,
208 + <&topckgen CLK_TOP_AUD_MUX1_DIV>,
209 + <&topckgen CLK_TOP_AUD_MUX2_DIV>;
210 + assigned-clock-parents = <&topckgen CLK_TOP_AUD1PLL_98M>,
211 + <&topckgen CLK_TOP_AUD2PLL_90M>;
212 + assigned-clock-rates = <0>, <0>, <49152000>, <45158400>;