1 From 4dab73d46eb58c142b5d2e7039f12e4e5df357ad Mon Sep 17 00:00:00 2001
2 From: Guochun Mao <guochun.mao@mediatek.com>
3 Date: Mon, 18 Dec 2017 09:47:35 +0800
4 Subject: [PATCH 196/224] mtd: mtk-nor: modify functions' name more generally
6 Since more and more Mediatek's SoC can use this driver to
7 control spi-nor flash, functions' name with "mt8173_" is
8 no longer properly. Replacing "mt8173_" with "mtk_" will
9 be more accurate to describe these functions' usable scope.
11 Signed-off-by: Guochun Mao <guochun.mao@mediatek.com>
12 Signed-off-by: Cyrille Pitchen <cyrille.pitchen@wedev4u.fr>
14 drivers/mtd/spi-nor/mtk-quadspi.c | 240 +++++++++++++++++++-------------------
15 1 file changed, 120 insertions(+), 120 deletions(-)
17 --- a/drivers/mtd/spi-nor/mtk-quadspi.c
18 +++ b/drivers/mtd/spi-nor/mtk-quadspi.c
20 #define MTK_NOR_PRG_REG(n) (MTK_NOR_PRGDATA0_REG + 4 * (n))
21 #define MTK_NOR_SHREG(n) (MTK_NOR_SHREG0_REG + 4 * (n))
27 void __iomem *base; /* nor flash base address */
28 @@ -118,48 +118,48 @@ struct mt8173_nor {
32 -static void mt8173_nor_set_read_mode(struct mt8173_nor *mt8173_nor)
33 +static void mtk_nor_set_read_mode(struct mtk_nor *mtk_nor)
35 - struct spi_nor *nor = &mt8173_nor->nor;
36 + struct spi_nor *nor = &mtk_nor->nor;
38 switch (nor->read_proto) {
39 case SNOR_PROTO_1_1_1:
40 - writeb(nor->read_opcode, mt8173_nor->base +
41 + writeb(nor->read_opcode, mtk_nor->base +
42 MTK_NOR_PRGDATA3_REG);
43 - writeb(MTK_NOR_FAST_READ, mt8173_nor->base +
44 + writeb(MTK_NOR_FAST_READ, mtk_nor->base +
47 case SNOR_PROTO_1_1_2:
48 - writeb(nor->read_opcode, mt8173_nor->base +
49 + writeb(nor->read_opcode, mtk_nor->base +
50 MTK_NOR_PRGDATA3_REG);
51 - writeb(MTK_NOR_DUAL_READ_EN, mt8173_nor->base +
52 + writeb(MTK_NOR_DUAL_READ_EN, mtk_nor->base +
55 case SNOR_PROTO_1_1_4:
56 - writeb(nor->read_opcode, mt8173_nor->base +
57 + writeb(nor->read_opcode, mtk_nor->base +
58 MTK_NOR_PRGDATA4_REG);
59 - writeb(MTK_NOR_QUAD_READ_EN, mt8173_nor->base +
60 + writeb(MTK_NOR_QUAD_READ_EN, mtk_nor->base +
64 - writeb(MTK_NOR_DUAL_DISABLE, mt8173_nor->base +
65 + writeb(MTK_NOR_DUAL_DISABLE, mtk_nor->base +
71 -static int mt8173_nor_execute_cmd(struct mt8173_nor *mt8173_nor, u8 cmdval)
72 +static int mtk_nor_execute_cmd(struct mtk_nor *mtk_nor, u8 cmdval)
75 u8 val = cmdval & 0x1f;
77 - writeb(cmdval, mt8173_nor->base + MTK_NOR_CMD_REG);
78 - return readl_poll_timeout(mt8173_nor->base + MTK_NOR_CMD_REG, reg,
79 + writeb(cmdval, mtk_nor->base + MTK_NOR_CMD_REG);
80 + return readl_poll_timeout(mtk_nor->base + MTK_NOR_CMD_REG, reg,
81 !(reg & val), 100, 10000);
84 -static int mt8173_nor_do_tx_rx(struct mt8173_nor *mt8173_nor, u8 op,
85 - u8 *tx, int txlen, u8 *rx, int rxlen)
86 +static int mtk_nor_do_tx_rx(struct mtk_nor *mtk_nor, u8 op,
87 + u8 *tx, int txlen, u8 *rx, int rxlen)
89 int len = 1 + txlen + rxlen;
91 @@ -167,26 +167,26 @@ static int mt8173_nor_do_tx_rx(struct mt
92 if (len > MTK_NOR_MAX_SHIFT)
95 - writeb(len * 8, mt8173_nor->base + MTK_NOR_CNT_REG);
96 + writeb(len * 8, mtk_nor->base + MTK_NOR_CNT_REG);
98 /* start at PRGDATA5, go down to PRGDATA0 */
99 idx = MTK_NOR_MAX_RX_TX_SHIFT - 1;
102 - writeb(op, mt8173_nor->base + MTK_NOR_PRG_REG(idx));
103 + writeb(op, mtk_nor->base + MTK_NOR_PRG_REG(idx));
106 /* program TX data */
107 for (i = 0; i < txlen; i++, idx--)
108 - writeb(tx[i], mt8173_nor->base + MTK_NOR_PRG_REG(idx));
109 + writeb(tx[i], mtk_nor->base + MTK_NOR_PRG_REG(idx));
111 /* clear out rest of TX registers */
113 - writeb(0, mt8173_nor->base + MTK_NOR_PRG_REG(idx));
114 + writeb(0, mtk_nor->base + MTK_NOR_PRG_REG(idx));
118 - ret = mt8173_nor_execute_cmd(mt8173_nor, MTK_NOR_PRG_CMD);
119 + ret = mtk_nor_execute_cmd(mtk_nor, MTK_NOR_PRG_CMD);
123 @@ -195,20 +195,20 @@ static int mt8173_nor_do_tx_rx(struct mt
125 /* read out RX data */
126 for (i = 0; i < rxlen; i++, idx--)
127 - rx[i] = readb(mt8173_nor->base + MTK_NOR_SHREG(idx));
128 + rx[i] = readb(mtk_nor->base + MTK_NOR_SHREG(idx));
133 /* Do a WRSR (Write Status Register) command */
134 -static int mt8173_nor_wr_sr(struct mt8173_nor *mt8173_nor, u8 sr)
135 +static int mtk_nor_wr_sr(struct mtk_nor *mtk_nor, u8 sr)
137 - writeb(sr, mt8173_nor->base + MTK_NOR_PRGDATA5_REG);
138 - writeb(8, mt8173_nor->base + MTK_NOR_CNT_REG);
139 - return mt8173_nor_execute_cmd(mt8173_nor, MTK_NOR_WRSR_CMD);
140 + writeb(sr, mtk_nor->base + MTK_NOR_PRGDATA5_REG);
141 + writeb(8, mtk_nor->base + MTK_NOR_CNT_REG);
142 + return mtk_nor_execute_cmd(mtk_nor, MTK_NOR_WRSR_CMD);
145 -static int mt8173_nor_write_buffer_enable(struct mt8173_nor *mt8173_nor)
146 +static int mtk_nor_write_buffer_enable(struct mtk_nor *mtk_nor)
150 @@ -216,27 +216,27 @@ static int mt8173_nor_write_buffer_enabl
151 * 0: pre-fetch buffer use for read
152 * 1: pre-fetch buffer use for page program
154 - writel(MTK_NOR_WR_BUF_ENABLE, mt8173_nor->base + MTK_NOR_CFG2_REG);
155 - return readb_poll_timeout(mt8173_nor->base + MTK_NOR_CFG2_REG, reg,
156 + writel(MTK_NOR_WR_BUF_ENABLE, mtk_nor->base + MTK_NOR_CFG2_REG);
157 + return readb_poll_timeout(mtk_nor->base + MTK_NOR_CFG2_REG, reg,
158 0x01 == (reg & 0x01), 100, 10000);
161 -static int mt8173_nor_write_buffer_disable(struct mt8173_nor *mt8173_nor)
162 +static int mtk_nor_write_buffer_disable(struct mtk_nor *mtk_nor)
166 - writel(MTK_NOR_WR_BUF_DISABLE, mt8173_nor->base + MTK_NOR_CFG2_REG);
167 - return readb_poll_timeout(mt8173_nor->base + MTK_NOR_CFG2_REG, reg,
168 + writel(MTK_NOR_WR_BUF_DISABLE, mtk_nor->base + MTK_NOR_CFG2_REG);
169 + return readb_poll_timeout(mtk_nor->base + MTK_NOR_CFG2_REG, reg,
170 MTK_NOR_WR_BUF_DISABLE == (reg & 0x1), 100,
174 -static void mt8173_nor_set_addr_width(struct mt8173_nor *mt8173_nor)
175 +static void mtk_nor_set_addr_width(struct mtk_nor *mtk_nor)
178 - struct spi_nor *nor = &mt8173_nor->nor;
179 + struct spi_nor *nor = &mtk_nor->nor;
181 - val = readb(mt8173_nor->base + MTK_NOR_DUAL_REG);
182 + val = readb(mtk_nor->base + MTK_NOR_DUAL_REG);
184 switch (nor->addr_width) {
186 @@ -246,115 +246,115 @@ static void mt8173_nor_set_addr_width(st
187 val |= MTK_NOR_4B_ADDR_EN;
190 - dev_warn(mt8173_nor->dev, "Unexpected address width %u.\n",
191 + dev_warn(mtk_nor->dev, "Unexpected address width %u.\n",
196 - writeb(val, mt8173_nor->base + MTK_NOR_DUAL_REG);
197 + writeb(val, mtk_nor->base + MTK_NOR_DUAL_REG);
200 -static void mt8173_nor_set_addr(struct mt8173_nor *mt8173_nor, u32 addr)
201 +static void mtk_nor_set_addr(struct mtk_nor *mtk_nor, u32 addr)
205 - mt8173_nor_set_addr_width(mt8173_nor);
206 + mtk_nor_set_addr_width(mtk_nor);
208 for (i = 0; i < 3; i++) {
209 - writeb(addr & 0xff, mt8173_nor->base + MTK_NOR_RADR0_REG + i * 4);
210 + writeb(addr & 0xff, mtk_nor->base + MTK_NOR_RADR0_REG + i * 4);
213 /* Last register is non-contiguous */
214 - writeb(addr & 0xff, mt8173_nor->base + MTK_NOR_RADR3_REG);
215 + writeb(addr & 0xff, mtk_nor->base + MTK_NOR_RADR3_REG);
218 -static ssize_t mt8173_nor_read(struct spi_nor *nor, loff_t from, size_t length,
220 +static ssize_t mtk_nor_read(struct spi_nor *nor, loff_t from, size_t length,
224 int addr = (int)from;
225 u8 *buf = (u8 *)buffer;
226 - struct mt8173_nor *mt8173_nor = nor->priv;
227 + struct mtk_nor *mtk_nor = nor->priv;
229 /* set mode for fast read mode ,dual mode or quad mode */
230 - mt8173_nor_set_read_mode(mt8173_nor);
231 - mt8173_nor_set_addr(mt8173_nor, addr);
232 + mtk_nor_set_read_mode(mtk_nor);
233 + mtk_nor_set_addr(mtk_nor, addr);
235 for (i = 0; i < length; i++) {
236 - ret = mt8173_nor_execute_cmd(mt8173_nor, MTK_NOR_PIO_READ_CMD);
237 + ret = mtk_nor_execute_cmd(mtk_nor, MTK_NOR_PIO_READ_CMD);
240 - buf[i] = readb(mt8173_nor->base + MTK_NOR_RDATA_REG);
241 + buf[i] = readb(mtk_nor->base + MTK_NOR_RDATA_REG);
246 -static int mt8173_nor_write_single_byte(struct mt8173_nor *mt8173_nor,
247 - int addr, int length, u8 *data)
248 +static int mtk_nor_write_single_byte(struct mtk_nor *mtk_nor,
249 + int addr, int length, u8 *data)
253 - mt8173_nor_set_addr(mt8173_nor, addr);
254 + mtk_nor_set_addr(mtk_nor, addr);
256 for (i = 0; i < length; i++) {
257 - writeb(*data++, mt8173_nor->base + MTK_NOR_WDATA_REG);
258 - ret = mt8173_nor_execute_cmd(mt8173_nor, MTK_NOR_PIO_WR_CMD);
259 + writeb(*data++, mtk_nor->base + MTK_NOR_WDATA_REG);
260 + ret = mtk_nor_execute_cmd(mtk_nor, MTK_NOR_PIO_WR_CMD);
267 -static int mt8173_nor_write_buffer(struct mt8173_nor *mt8173_nor, int addr,
269 +static int mtk_nor_write_buffer(struct mtk_nor *mtk_nor, int addr,
274 - mt8173_nor_set_addr(mt8173_nor, addr);
275 + mtk_nor_set_addr(mtk_nor, addr);
278 for (i = 0; i < SFLASH_WRBUF_SIZE; i += 4) {
279 data = buf[bufidx + 3]<<24 | buf[bufidx + 2]<<16 |
280 buf[bufidx + 1]<<8 | buf[bufidx];
282 - writel(data, mt8173_nor->base + MTK_NOR_PP_DATA_REG);
283 + writel(data, mtk_nor->base + MTK_NOR_PP_DATA_REG);
285 - return mt8173_nor_execute_cmd(mt8173_nor, MTK_NOR_WR_CMD);
286 + return mtk_nor_execute_cmd(mtk_nor, MTK_NOR_WR_CMD);
289 -static ssize_t mt8173_nor_write(struct spi_nor *nor, loff_t to, size_t len,
291 +static ssize_t mtk_nor_write(struct spi_nor *nor, loff_t to, size_t len,
295 - struct mt8173_nor *mt8173_nor = nor->priv;
296 + struct mtk_nor *mtk_nor = nor->priv;
299 - ret = mt8173_nor_write_buffer_enable(mt8173_nor);
300 + ret = mtk_nor_write_buffer_enable(mtk_nor);
302 - dev_warn(mt8173_nor->dev, "write buffer enable failed!\n");
303 + dev_warn(mtk_nor->dev, "write buffer enable failed!\n");
307 for (i = 0; i + SFLASH_WRBUF_SIZE <= len; i += SFLASH_WRBUF_SIZE) {
308 - ret = mt8173_nor_write_buffer(mt8173_nor, to, buf);
309 + ret = mtk_nor_write_buffer(mtk_nor, to, buf);
311 - dev_err(mt8173_nor->dev, "write buffer failed!\n");
312 + dev_err(mtk_nor->dev, "write buffer failed!\n");
315 to += SFLASH_WRBUF_SIZE;
316 buf += SFLASH_WRBUF_SIZE;
318 - ret = mt8173_nor_write_buffer_disable(mt8173_nor);
319 + ret = mtk_nor_write_buffer_disable(mtk_nor);
321 - dev_warn(mt8173_nor->dev, "write buffer disable failed!\n");
322 + dev_warn(mtk_nor->dev, "write buffer disable failed!\n");
327 - ret = mt8173_nor_write_single_byte(mt8173_nor, to,
328 - (int)(len - i), (u8 *)buf);
329 + ret = mtk_nor_write_single_byte(mtk_nor, to,
330 + (int)(len - i), (u8 *)buf);
332 - dev_err(mt8173_nor->dev, "write single byte failed!\n");
333 + dev_err(mtk_nor->dev, "write single byte failed!\n");
337 @@ -362,72 +362,72 @@ static ssize_t mt8173_nor_write(struct s
341 -static int mt8173_nor_read_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
342 +static int mtk_nor_read_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
345 - struct mt8173_nor *mt8173_nor = nor->priv;
346 + struct mtk_nor *mtk_nor = nor->priv;
350 - ret = mt8173_nor_execute_cmd(mt8173_nor, MTK_NOR_RDSR_CMD);
351 + ret = mtk_nor_execute_cmd(mtk_nor, MTK_NOR_RDSR_CMD);
355 - *buf = readb(mt8173_nor->base + MTK_NOR_RDSR_REG);
356 + *buf = readb(mtk_nor->base + MTK_NOR_RDSR_REG);
358 - dev_err(mt8173_nor->dev, "len should be 1 for read status!\n");
359 + dev_err(mtk_nor->dev, "len should be 1 for read status!\n");
362 - ret = mt8173_nor_do_tx_rx(mt8173_nor, opcode, NULL, 0, buf, len);
363 + ret = mtk_nor_do_tx_rx(mtk_nor, opcode, NULL, 0, buf, len);
369 -static int mt8173_nor_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf,
371 +static int mtk_nor_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf,
375 - struct mt8173_nor *mt8173_nor = nor->priv;
376 + struct mtk_nor *mtk_nor = nor->priv;
380 /* We only handle 1 byte */
381 - ret = mt8173_nor_wr_sr(mt8173_nor, *buf);
382 + ret = mtk_nor_wr_sr(mtk_nor, *buf);
385 - ret = mt8173_nor_do_tx_rx(mt8173_nor, opcode, buf, len, NULL, 0);
386 + ret = mtk_nor_do_tx_rx(mtk_nor, opcode, buf, len, NULL, 0);
388 - dev_warn(mt8173_nor->dev, "write reg failure!\n");
389 + dev_warn(mtk_nor->dev, "write reg failure!\n");
395 -static void mt8173_nor_disable_clk(struct mt8173_nor *mt8173_nor)
396 +static void mtk_nor_disable_clk(struct mtk_nor *mtk_nor)
398 - clk_disable_unprepare(mt8173_nor->spi_clk);
399 - clk_disable_unprepare(mt8173_nor->nor_clk);
400 + clk_disable_unprepare(mtk_nor->spi_clk);
401 + clk_disable_unprepare(mtk_nor->nor_clk);
404 -static int mt8173_nor_enable_clk(struct mt8173_nor *mt8173_nor)
405 +static int mtk_nor_enable_clk(struct mtk_nor *mtk_nor)
409 - ret = clk_prepare_enable(mt8173_nor->spi_clk);
410 + ret = clk_prepare_enable(mtk_nor->spi_clk);
414 - ret = clk_prepare_enable(mt8173_nor->nor_clk);
415 + ret = clk_prepare_enable(mtk_nor->nor_clk);
417 - clk_disable_unprepare(mt8173_nor->spi_clk);
418 + clk_disable_unprepare(mtk_nor->spi_clk);
425 -static int mtk_nor_init(struct mt8173_nor *mt8173_nor,
426 +static int mtk_nor_init(struct mtk_nor *mtk_nor,
427 struct device_node *flash_node)
429 const struct spi_nor_hwcaps hwcaps = {
430 @@ -439,18 +439,18 @@ static int mtk_nor_init(struct mt8173_no
433 /* initialize controller to accept commands */
434 - writel(MTK_NOR_ENABLE_SF_CMD, mt8173_nor->base + MTK_NOR_WRPROT_REG);
435 + writel(MTK_NOR_ENABLE_SF_CMD, mtk_nor->base + MTK_NOR_WRPROT_REG);
437 - nor = &mt8173_nor->nor;
438 - nor->dev = mt8173_nor->dev;
439 - nor->priv = mt8173_nor;
440 + nor = &mtk_nor->nor;
441 + nor->dev = mtk_nor->dev;
442 + nor->priv = mtk_nor;
443 spi_nor_set_flash_node(nor, flash_node);
445 /* fill the hooks to spi nor */
446 - nor->read = mt8173_nor_read;
447 - nor->read_reg = mt8173_nor_read_reg;
448 - nor->write = mt8173_nor_write;
449 - nor->write_reg = mt8173_nor_write_reg;
450 + nor->read = mtk_nor_read;
451 + nor->read_reg = mtk_nor_read_reg;
452 + nor->write = mtk_nor_write;
453 + nor->write_reg = mtk_nor_write_reg;
454 nor->mtd.name = "mtk_nor";
455 /* initialized with NULL */
456 ret = spi_nor_scan(nor, NULL, &hwcaps);
457 @@ -465,34 +465,34 @@ static int mtk_nor_drv_probe(struct plat
458 struct device_node *flash_np;
459 struct resource *res;
461 - struct mt8173_nor *mt8173_nor;
462 + struct mtk_nor *mtk_nor;
464 if (!pdev->dev.of_node) {
465 dev_err(&pdev->dev, "No DT found\n");
469 - mt8173_nor = devm_kzalloc(&pdev->dev, sizeof(*mt8173_nor), GFP_KERNEL);
471 + mtk_nor = devm_kzalloc(&pdev->dev, sizeof(*mtk_nor), GFP_KERNEL);
474 - platform_set_drvdata(pdev, mt8173_nor);
475 + platform_set_drvdata(pdev, mtk_nor);
477 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
478 - mt8173_nor->base = devm_ioremap_resource(&pdev->dev, res);
479 - if (IS_ERR(mt8173_nor->base))
480 - return PTR_ERR(mt8173_nor->base);
481 + mtk_nor->base = devm_ioremap_resource(&pdev->dev, res);
482 + if (IS_ERR(mtk_nor->base))
483 + return PTR_ERR(mtk_nor->base);
485 - mt8173_nor->spi_clk = devm_clk_get(&pdev->dev, "spi");
486 - if (IS_ERR(mt8173_nor->spi_clk))
487 - return PTR_ERR(mt8173_nor->spi_clk);
488 + mtk_nor->spi_clk = devm_clk_get(&pdev->dev, "spi");
489 + if (IS_ERR(mtk_nor->spi_clk))
490 + return PTR_ERR(mtk_nor->spi_clk);
492 - mt8173_nor->nor_clk = devm_clk_get(&pdev->dev, "sf");
493 - if (IS_ERR(mt8173_nor->nor_clk))
494 - return PTR_ERR(mt8173_nor->nor_clk);
495 + mtk_nor->nor_clk = devm_clk_get(&pdev->dev, "sf");
496 + if (IS_ERR(mtk_nor->nor_clk))
497 + return PTR_ERR(mtk_nor->nor_clk);
499 - mt8173_nor->dev = &pdev->dev;
500 + mtk_nor->dev = &pdev->dev;
502 - ret = mt8173_nor_enable_clk(mt8173_nor);
503 + ret = mtk_nor_enable_clk(mtk_nor);
507 @@ -503,20 +503,20 @@ static int mtk_nor_drv_probe(struct plat
511 - ret = mtk_nor_init(mt8173_nor, flash_np);
512 + ret = mtk_nor_init(mtk_nor, flash_np);
516 - mt8173_nor_disable_clk(mt8173_nor);
517 + mtk_nor_disable_clk(mtk_nor);
522 static int mtk_nor_drv_remove(struct platform_device *pdev)
524 - struct mt8173_nor *mt8173_nor = platform_get_drvdata(pdev);
525 + struct mtk_nor *mtk_nor = platform_get_drvdata(pdev);
527 - mt8173_nor_disable_clk(mt8173_nor);
528 + mtk_nor_disable_clk(mtk_nor);
532 @@ -524,18 +524,18 @@ static int mtk_nor_drv_remove(struct pla
533 #ifdef CONFIG_PM_SLEEP
534 static int mtk_nor_suspend(struct device *dev)
536 - struct mt8173_nor *mt8173_nor = dev_get_drvdata(dev);
537 + struct mtk_nor *mtk_nor = dev_get_drvdata(dev);
539 - mt8173_nor_disable_clk(mt8173_nor);
540 + mtk_nor_disable_clk(mtk_nor);
545 static int mtk_nor_resume(struct device *dev)
547 - struct mt8173_nor *mt8173_nor = dev_get_drvdata(dev);
548 + struct mtk_nor *mtk_nor = dev_get_drvdata(dev);
550 - return mt8173_nor_enable_clk(mt8173_nor);
551 + return mtk_nor_enable_clk(mtk_nor);
554 static const struct dev_pm_ops mtk_nor_dev_pm_ops = {