target/linux/mediatek/patches-4.14/0212-arm64-dts-mt7622-add-pinctrl-related-device-nodes.patch

   1 From 927c736a1a169713cd59140db5e82f8ed11dad60 Mon Sep 17 00:00:00 2001
   2 From: Sean Wang <sean.wang@mediatek.com>
   3 Date: Fri, 29 Dec 2017 11:06:52 +0800
   4 Subject: [PATCH 212/224] arm64: dts: mt7622: add pinctrl related device nodes
   5
   6 add pinctrl device nodes and rfb1 board, additionally include all pin
   7 groups possible being used on rfb1 board and available gpio keys.
   8
   9 Signed-off-by: Sean Wang <sean.wang@mediatek.com>
  10 Cc: Matthias Brugger <matthias.bgg@gmail.com>
  11 ---
  12  arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts | 200 +++++++++++++++++++++++++++
  13  arch/arm64/boot/dts/mediatek/mt7622.dtsi     |   7 +
  14  2 files changed, 207 insertions(+)
  15
  16 diff --git a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
  17 index c08309df2cc7..fc8ef78a0a34 100644
  18 --- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
  19 +++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
  20 @@ -7,6 +7,8 @@
  21   */
  22
  23  /dts-v1/;
  24 +#include <dt-bindings/input/input.h>
  25 +
  26  #include "mt7622.dtsi"
  27
  28  / {
  29 @@ -17,11 +19,209 @@
  30                 bootargs = "console=ttyS0,115200n1";
  31         };
  32
  33 +       gpio-keys {
  34 +               compatible = "gpio-keys-polled";
  35 +               poll-interval = <100>;
  36 +
  37 +               factory {
  38 +                       label = "factory";
  39 +                       linux,code = <BTN_0>;
  40 +                       gpios = <&pio 0 0>;
  41 +               };
  42 +
  43 +               wps {
  44 +                       label = "wps";
  45 +                       linux,code = <KEY_WPS_BUTTON>;
  46 +                       gpios = <&pio 102 0>;
  47 +               };
  48 +       };
  49 +
  50         memory {
  51                 reg = <0 0x40000000 0 0x3F000000>;
  52         };
  53  };
  54
  55 +&pio {
  56 +       /* eMMC is shared pin with parallel NAND */
  57 +       emmc_pins_default: emmc-pins-default {
  58 +               mux {
  59 +                       function = "emmc", "emmc_rst";
  60 +                       groups = "emmc";
  61 +               };
  62 +       };
  63 +
  64 +       emmc_pins_uhs: emmc-pins-uhs {
  65 +               mux {
  66 +                       function = "emmc";
  67 +                       groups = "emmc";
  68 +               };
  69 +       };
  70 +
  71 +       eth_pins: eth-pins {
  72 +               mux {
  73 +                       function = "eth";
  74 +                       groups = "mdc_mdio", "rgmii_via_gmac2";
  75 +               };
  76 +       };
  77 +
  78 +       i2c1_pins: i2c1-pins {
  79 +               mux {
  80 +                       function = "i2c";
  81 +                       groups =  "i2c1_0";
  82 +               };
  83 +       };
  84 +
  85 +       i2c2_pins: i2c2-pins {
  86 +               mux {
  87 +                       function = "i2c";
  88 +                       groups =  "i2c2_0";
  89 +               };
  90 +       };
  91 +
  92 +       i2s1_pins: i2s1-pins {
  93 +               mux {
  94 +                       function = "i2s";
  95 +                       groups =  "i2s_out_bclk_ws_mclk",
  96 +                                 "i2s1_in_data",
  97 +                                 "i2s1_out_data";
  98 +               };
  99 +       };
 100 +
 101 +       irrx_pins: irrx-pins {
 102 +               mux {
 103 +                       function = "ir";
 104 +                       groups =  "ir_1_rx";
 105 +               };
 106 +       };
 107 +
 108 +       irtx_pins: irtx-pins {
 109 +               mux {
 110 +                       function = "ir";
 111 +                       groups =  "ir_1_tx";
 112 +               };
 113 +       };
 114 +
 115 +       /* Parallel nand is shared pin with eMMC */
 116 +       parallel_nand_pins: parallel-nand-pins {
 117 +               mux {
 118 +                       function = "flash";
 119 +                       groups = "par_nand";
 120 +               };
 121 +       };
 122 +
 123 +       pcie0_pins: pcie0-pins {
 124 +               mux {
 125 +                       function = "pcie";
 126 +                       groups = "pcie0_pad_perst",
 127 +                                "pcie0_1_waken",
 128 +                                "pcie0_1_clkreq";
 129 +               };
 130 +       };
 131 +
 132 +       pcie1_pins: pcie1-pins {
 133 +               mux {
 134 +                       function = "pcie";
 135 +                       groups = "pcie1_pad_perst",
 136 +                                "pcie1_0_waken",
 137 +                                "pcie1_0_clkreq";
 138 +               };
 139 +       };
 140 +
 141 +       pmic_bus_pins: pmic-bus-pins {
 142 +               mux {
 143 +                       function = "pmic";
 144 +                       groups = "pmic_bus";
 145 +               };
 146 +       };
 147 +
 148 +       pwm7_pins: pwm1-2-pins {
 149 +               mux {
 150 +                       function = "pwm";
 151 +                       groups = "pwm_ch7_2";
 152 +               };
 153 +       };
 154 +
 155 +       wled_pins: wled-pins {
 156 +               mux {
 157 +                       function = "led";
 158 +                       groups = "wled";
 159 +               };
 160 +       };
 161 +
 162 +       sd0_pins_default: sd0-pins-default {
 163 +               mux {
 164 +                       function = "sd";
 165 +                       groups = "sd_0";
 166 +               };
 167 +       };
 168 +
 169 +       sd0_pins_uhs: sd0-pins-uhs {
 170 +               mux {
 171 +                       function = "sd";
 172 +                       groups = "sd_0";
 173 +               };
 174 +       };
 175 +
 176 +       /* Serial NAND is shared pin with SPI-NOR */
 177 +       serial_nand_pins: serial-nand-pins {
 178 +               mux {
 179 +                       function = "flash";
 180 +                       groups = "snfi";
 181 +               };
 182 +       };
 183 +
 184 +       spic0_pins: spic0-pins {
 185 +               mux {
 186 +                       function = "spi";
 187 +                       groups = "spic0_0";
 188 +               };
 189 +       };
 190 +
 191 +       spic1_pins: spic1-pins {
 192 +               mux {
 193 +                       function = "spi";
 194 +                       groups = "spic1_0";
 195 +               };
 196 +       };
 197 +
 198 +       /* SPI-NOR is shared pin with serial NAND */
 199 +       spi_nor_pins: spi-nor-pins {
 200 +               mux {
 201 +                       function = "flash";
 202 +                       groups = "spi_nor";
 203 +               };
 204 +       };
 205 +
 206 +       /* serial NAND is shared pin with SPI-NOR */
 207 +       serial_nand_pins: serial-nand-pins {
 208 +               mux {
 209 +                       function = "flash";
 210 +                       groups = "snfi";
 211 +               };
 212 +       };
 213 +
 214 +       uart0_pins: uart0-pins {
 215 +               mux {
 216 +                       function = "uart";
 217 +                       groups = "uart0_0_tx_rx" ;
 218 +               };
 219 +       };
 220 +
 221 +       uart2_pins: uart2-pins {
 222 +               mux {
 223 +                       function = "uart";
 224 +                       groups = "uart2_1_tx_rx" ;
 225 +               };
 226 +       };
 227 +
 228 +       watchdog_pins: watchdog-pins {
 229 +               mux {
 230 +                       function = "watchdog";
 231 +                       groups = "watchdog";
 232 +               };
 233 +       };
 234 +};
 235 +
 236  &uart0 {
 237         status = "okay";
 238  };
 239 diff --git a/arch/arm64/boot/dts/mediatek/mt7622.dtsi b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
 240 index 81207e652d59..8211bf72ccaa 100644
 241 --- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
 242 +++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
 243 @@ -147,6 +147,13 @@
 244                 #clock-cells = <1>;
 245         };
 246
 247 +       pio: pinctrl@10211000 {
 248 +               compatible = "mediatek,mt7622-pinctrl";
 249 +               reg = <0 0x10211000 0 0x1000>;
 250 +               gpio-controller;
 251 +               #gpio-cells = <2>;
 252 +       };
 253 +
 254         gic: interrupt-controller@10300000 {
 255                 compatible = "arm,gic-400";
 256                 interrupt-controller;
 257 --
 258 2.11.0
 259