1 From 19fc79333af0d3733d4987bc1e554ae7e8a8cb0d Mon Sep 17 00:00:00 2001
2 From: Sean Wang <sean.wang@mediatek.com>
3 Date: Thu, 28 Dec 2017 16:26:10 +0800
4 Subject: [PATCH 214/224] arm64: dts: mt7622: add cpufreq related device nodes
6 Add clocks, regulators and opp information into cpu nodes.
7 In addition, the power supply for cpu nodes is deployed on
10 Signed-off-by: Sean Wang <sean.wang@mediatek.com>
11 Cc: Viresh Kumar <viresh.kumar@linaro.org>
13 arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts | 12 +++++++
14 arch/arm64/boot/dts/mediatek/mt7622.dtsi | 52 ++++++++++++++++++++++++++++
15 2 files changed, 64 insertions(+)
17 --- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
18 +++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
20 bootargs = "console=ttyS0,115200n1";
25 + proc-supply = <&mt6380_vcpu_reg>;
26 + sram-supply = <&mt6380_vm_reg>;
30 + proc-supply = <&mt6380_vcpu_reg>;
31 + sram-supply = <&mt6380_vm_reg>;
36 compatible = "gpio-keys-polled";
37 poll-interval = <100>;
38 --- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
39 +++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
44 + cpu_opp_table: opp-table {
45 + compatible = "operating-points-v2";
48 + opp-hz = /bits/ 64 <30000000>;
49 + opp-microvolt = <950000>;
53 + opp-hz = /bits/ 64 <437500000>;
54 + opp-microvolt = <1000000>;
58 + opp-hz = /bits/ 64 <600000000>;
59 + opp-microvolt = <1050000>;
63 + opp-hz = /bits/ 64 <812500000>;
64 + opp-microvolt = <1100000>;
68 + opp-hz = /bits/ 64 <1025000000>;
69 + opp-microvolt = <1150000>;
73 + opp-hz = /bits/ 64 <1137500000>;
74 + opp-microvolt = <1200000>;
78 + opp-hz = /bits/ 64 <1262500000>;
79 + opp-microvolt = <1250000>;
83 + opp-hz = /bits/ 64 <1350000000>;
84 + opp-microvolt = <1310000>;
93 compatible = "arm,cortex-a53", "arm,armv8";
95 + clocks = <&infracfg CLK_INFRA_MUX1_SEL>,
96 + <&apmixedsys CLK_APMIXED_MAIN_CORE_EN>;
97 + clock-names = "cpu", "intermediate";
98 + operating-points-v2 = <&cpu_opp_table>;
99 enable-method = "psci";
100 clock-frequency = <1300000000>;
104 compatible = "arm,cortex-a53", "arm,armv8";
106 + clocks = <&infracfg CLK_INFRA_MUX1_SEL>,
107 + <&apmixedsys CLK_APMIXED_MAIN_CORE_EN>;
108 + clock-names = "cpu", "intermediate";
109 + operating-points-v2 = <&cpu_opp_table>;
110 enable-method = "psci";
111 clock-frequency = <1300000000>;