target/linux/mediatek/patches-4.14/0214-arm64-dts-mt7622-add-cpufreq-related-device-nodes.patch

   1 From 19fc79333af0d3733d4987bc1e554ae7e8a8cb0d Mon Sep 17 00:00:00 2001
   2 From: Sean Wang <sean.wang@mediatek.com>
   3 Date: Thu, 28 Dec 2017 16:26:10 +0800
   4 Subject: [PATCH 214/224] arm64: dts: mt7622: add cpufreq related device nodes
   5
   6 Add clocks, regulators and opp information into cpu nodes.
   7 In addition, the power supply for cpu nodes is deployed on
   8 mt7622-rfb1 board.
   9
  10 Signed-off-by: Sean Wang <sean.wang@mediatek.com>
  11 Cc: Viresh Kumar <viresh.kumar@linaro.org>
  12 ---
  13  arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts | 12 +++++++
  14  arch/arm64/boot/dts/mediatek/mt7622.dtsi     | 52 ++++++++++++++++++++++++++++
  15  2 files changed, 64 insertions(+)
  16
  17 diff --git a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
  18 index 42bd3a4c9a93..b3878656475c 100644
  19 --- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
  20 +++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
  21 @@ -20,6 +20,18 @@
  22                 bootargs = "console=ttyS0,115200n1";
  23         };
  24
  25 +       cpus {
  26 +               cpu@0 {
  27 +                       proc-supply = <&mt6380_vcpu_reg>;
  28 +                       sram-supply = <&mt6380_vm_reg>;
  29 +               };
  30 +
  31 +               cpu@1 {
  32 +                       proc-supply = <&mt6380_vcpu_reg>;
  33 +                       sram-supply = <&mt6380_vm_reg>;
  34 +               };
  35 +       };
  36 +
  37         gpio-keys {
  38                 compatible = "gpio-keys-polled";
  39                 poll-interval = <100>;
  40 diff --git a/arch/arm64/boot/dts/mediatek/mt7622.dtsi b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
  41 index c387c4cb7d3e..7256879de4c9 100644
  42 --- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
  43 +++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
  44 @@ -18,6 +18,50 @@
  45         #address-cells = <2>;
  46         #size-cells = <2>;
  47
  48 +       cpu_opp_table: opp-table {
  49 +               compatible = "operating-points-v2";
  50 +               opp-shared;
  51 +               opp-300000000 {
  52 +                       opp-hz = /bits/ 64 <30000000>;
  53 +                       opp-microvolt = <950000>;
  54 +               };
  55 +
  56 +               opp-437500000 {
  57 +                       opp-hz = /bits/ 64 <437500000>;
  58 +                       opp-microvolt = <1000000>;
  59 +               };
  60 +
  61 +               opp-600000000 {
  62 +                       opp-hz = /bits/ 64 <600000000>;
  63 +                       opp-microvolt = <1050000>;
  64 +               };
  65 +
  66 +               opp-812500000 {
  67 +                       opp-hz = /bits/ 64 <812500000>;
  68 +                       opp-microvolt = <1100000>;
  69 +               };
  70 +
  71 +               opp-1025000000 {
  72 +                       opp-hz = /bits/ 64 <1025000000>;
  73 +                       opp-microvolt = <1150000>;
  74 +               };
  75 +
  76 +               opp-1137500000 {
  77 +                       opp-hz = /bits/ 64 <1137500000>;
  78 +                       opp-microvolt = <1200000>;
  79 +               };
  80 +
  81 +               opp-1262500000 {
  82 +                       opp-hz = /bits/ 64 <1262500000>;
  83 +                       opp-microvolt = <1250000>;
  84 +               };
  85 +
  86 +               opp-1350000000 {
  87 +                       opp-hz = /bits/ 64 <1350000000>;
  88 +                       opp-microvolt = <1310000>;
  89 +               };
  90 +       };
  91 +
  92         cpus {
  93                 #address-cells = <2>;
  94                 #size-cells = <0>;
  95 @@ -26,6 +70,10 @@
  96                         device_type = "cpu";
  97                         compatible = "arm,cortex-a53", "arm,armv8";
  98                         reg = <0x0 0x0>;
  99 +                       clocks = <&infracfg CLK_INFRA_MUX1_SEL>,
 100 +                                <&apmixedsys CLK_APMIXED_MAIN_CORE_EN>;
 101 +                       clock-names = "cpu", "intermediate";
 102 +                       operating-points-v2 = <&cpu_opp_table>;
 103                         enable-method = "psci";
 104                         clock-frequency = <1300000000>;
 105                 };
 106 @@ -34,6 +82,10 @@
 107                         device_type = "cpu";
 108                         compatible = "arm,cortex-a53", "arm,armv8";
 109                         reg = <0x0 0x1>;
 110 +                       clocks = <&infracfg CLK_INFRA_MUX1_SEL>,
 111 +                                <&apmixedsys CLK_APMIXED_MAIN_CORE_EN>;
 112 +                       clock-names = "cpu", "intermediate";
 113 +                       operating-points-v2 = <&cpu_opp_table>;
 114                         enable-method = "psci";
 115                         clock-frequency = <1300000000>;
 116                 };
 117 --
 118 2.11.0
 119