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mediatek: backport upstream mediatek patches
[openwrt/staging/hauke.git] / target / linux / mediatek / patches-4.14 / 0216-arm64-dts-mt7622-add-SoC-and-peripheral-related-devi.patch
1 From a69ac853def2f93194e244974f611477a1521a4a Mon Sep 17 00:00:00 2001
2 From: Sean Wang <sean.wang@mediatek.com>
3 Date: Thu, 28 Dec 2017 18:18:26 +0800
4 Subject: [PATCH 216/224] arm64: dts: mt7622: add SoC and peripheral related
5 device nodes
6
7 Add watchdog, rtc, auxadc, cir, efuse, rng, uart[1-4], pwm, i2c[0-2],
8 spi[0-1], btif and thermal related nodes.
9
10 Signed-off-by: Sean Wang <sean.wang@mediatek.com>
11 Cc: Andrew-CT Chen <andrew-ct.chen@mediatek.com>
12 Cc: Zhiyong Tao <zhiyong.tao@mediatek.com>
13 Cc: Zhi Mao <zhi.mao@mediatek.com>
14 Cc: Jun Gao <jun.gao@mediatek.com>
15 Cc: Leilk Liu <leilk.liu@mediatek.com>
16 Cc: Matthias Brugger <matthias.bgg@gmail.com>
17 ---
18 arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts | 54 ++++++
19 arch/arm64/boot/dts/mediatek/mt7622.dtsi | 264 +++++++++++++++++++++++++++
20 2 files changed, 318 insertions(+)
21
22 diff --git a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
23 index b3878656475c..ba6a79caca21 100644
24 --- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
25 +++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
26 @@ -235,6 +235,34 @@
27 };
28 };
29
30 +&btif {
31 + status = "okay";
32 +};
33 +
34 +&cir {
35 + pinctrl-names = "default";
36 + pinctrl-0 = <&irrx_pins>;
37 + status = "okay";
38 +};
39 +
40 +&i2c1 {
41 + pinctrl-names = "default";
42 + pinctrl-0 = <&i2c1_pins>;
43 + status = "okay";
44 +};
45 +
46 +&i2c2 {
47 + pinctrl-names = "default";
48 + pinctrl-0 = <&i2c2_pins>;
49 + status = "okay";
50 +};
51 +
52 +&pwm {
53 + pinctrl-names = "default";
54 + pinctrl-0 = <&pwm7_pins>;
55 + status = "okay";
56 +};
57 +
58 &pwrap {
59 pinctrl-names = "default";
60 pinctrl-0 = <&pmic_bus_pins>;
61 @@ -242,6 +270,32 @@
62 status = "okay";
63 };
64
65 +&spi0 {
66 + pinctrl-names = "default";
67 + pinctrl-0 = <&spic0_pins>;
68 + status = "okay";
69 +};
70 +
71 +&spi1 {
72 + pinctrl-names = "default";
73 + pinctrl-0 = <&spic1_pins>;
74 + status = "okay";
75 +};
76 +
77 &uart0 {
78 + pinctrl-names = "default";
79 + pinctrl-0 = <&uart0_pins>;
80 + status = "okay";
81 +};
82 +
83 +&uart2 {
84 + pinctrl-names = "default";
85 + pinctrl-0 = <&uart2_pins>;
86 + status = "okay";
87 +};
88 +
89 +&watchdog {
90 + pinctrl-names = "default";
91 + pinctrl-0 = <&watchdog_pins>;
92 status = "okay";
93 };
94 diff --git a/arch/arm64/boot/dts/mediatek/mt7622.dtsi b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
95 index d8a17d10e2ff..448cd366995b 100644
96 --- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
97 +++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
98 @@ -11,6 +11,7 @@
99 #include <dt-bindings/clock/mt7622-clk.h>
100 #include <dt-bindings/power/mt7622-power.h>
101 #include <dt-bindings/reset/mt7622-reset.h>
102 +#include <dt-bindings/thermal/thermal.h>
103
104 / {
105 compatible = "mediatek,mt7622";
106 @@ -74,6 +75,7 @@
107 <&apmixedsys CLK_APMIXED_MAIN_CORE_EN>;
108 clock-names = "cpu", "intermediate";
109 operating-points-v2 = <&cpu_opp_table>;
110 + #cooling-cells = <2>;
111 enable-method = "psci";
112 clock-frequency = <1300000000>;
113 };
114 @@ -121,6 +123,58 @@
115 };
116 };
117
118 + thermal-zones {
119 + cpu_thermal: cpu-thermal {
120 + polling-delay-passive = <1000>;
121 + polling-delay = <1000>;
122 +
123 + thermal-sensors = <&thermal 0>;
124 +
125 + trips {
126 + cpu_passive: cpu-passive {
127 + temperature = <47000>;
128 + hysteresis = <2000>;
129 + type = "passive";
130 + };
131 +
132 + cpu_active: cpu-active {
133 + temperature = <67000>;
134 + hysteresis = <2000>;
135 + type = "active";
136 + };
137 +
138 + cpu_hot: cpu-hot {
139 + temperature = <87000>;
140 + hysteresis = <2000>;
141 + type = "hot";
142 + };
143 +
144 + cpu-crit {
145 + temperature = <107000>;
146 + hysteresis = <2000>;
147 + type = "critical";
148 + };
149 + };
150 +
151 + cooling-maps {
152 + map0 {
153 + trip = <&cpu_passive>;
154 + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
155 + };
156 +
157 + map1 {
158 + trip = <&cpu_active>;
159 + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
160 + };
161 +
162 + map2 {
163 + trip = <&cpu_hot>;
164 + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
165 + };
166 + };
167 + };
168 + };
169 +
170 timer {
171 compatible = "arm,armv8-timer";
172 interrupt-parent = <&gic>;
173 @@ -176,6 +230,16 @@
174 clock-names = "hif_sel";
175 };
176
177 + cir: cir@10009000 {
178 + compatible = "mediatek,mt7622-cir";
179 + reg = <0 0x10009000 0 0x1000>;
180 + interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_LOW>;
181 + clocks = <&infracfg CLK_INFRA_IRRX_PD>,
182 + <&topckgen CLK_TOP_AXI_SEL>;
183 + clock-names = "clk", "bus";
184 + status = "disabled";
185 + };
186 +
187 sysirq: interrupt-controller@10200620 {
188 compatible = "mediatek,mt7622-sysirq",
189 "mediatek,mt6577-sysirq";
190 @@ -185,6 +249,18 @@
191 reg = <0 0x10200620 0 0x20>;
192 };
193
194 + efuse: efuse@10206000 {
195 + compatible = "mediatek,mt7622-efuse",
196 + "mediatek,efuse";
197 + reg = <0 0x10206000 0 0x1000>;
198 + #address-cells = <1>;
199 + #size-cells = <1>;
200 +
201 + thermal_calibration: calib@198 {
202 + reg = <0x198 0xc>;
203 + };
204 + };
205 +
206 apmixedsys: apmixedsys@10209000 {
207 compatible = "mediatek,mt7622-apmixedsys",
208 "syscon";
209 @@ -199,6 +275,14 @@
210 #clock-cells = <1>;
211 };
212
213 + rng: rng@1020f000 {
214 + compatible = "mediatek,mt7622-rng",
215 + "mediatek,mt7623-rng";
216 + reg = <0 0x1020f000 0 0x1000>;
217 + clocks = <&infracfg CLK_INFRA_TRNG>;
218 + clock-names = "rng";
219 + };
220 +
221 pio: pinctrl@10211000 {
222 compatible = "mediatek,mt7622-pinctrl";
223 reg = <0 0x10211000 0 0x1000>;
224 @@ -206,6 +290,21 @@
225 #gpio-cells = <2>;
226 };
227
228 + watchdog: watchdog@10212000 {
229 + compatible = "mediatek,mt7622-wdt",
230 + "mediatek,mt6589-wdt";
231 + reg = <0 0x10212000 0 0x800>;
232 + };
233 +
234 + rtc: rtc@10212800 {
235 + compatible = "mediatek,mt7622-rtc",
236 + "mediatek,soc-rtc";
237 + reg = <0 0x10212800 0 0x200>;
238 + interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_LOW>;
239 + clocks = <&topckgen CLK_TOP_RTC>;
240 + clock-names = "rtc";
241 + };
242 +
243 gic: interrupt-controller@10300000 {
244 compatible = "arm,gic-400";
245 interrupt-controller;
246 @@ -217,6 +316,14 @@
247 <0 0x10360000 0 0x2000>;
248 };
249
250 + auxadc: adc@11001000 {
251 + compatible = "mediatek,mt7622-auxadc";
252 + reg = <0 0x11001000 0 0x1000>;
253 + clocks = <&pericfg CLK_PERI_AUXADC_PD>;
254 + clock-names = "main";
255 + #io-channel-cells = <1>;
256 + };
257 +
258 uart0: serial@11002000 {
259 compatible = "mediatek,mt7622-uart",
260 "mediatek,mt6577-uart";
261 @@ -228,6 +335,163 @@
262 status = "disabled";
263 };
264
265 + uart1: serial@11003000 {
266 + compatible = "mediatek,mt7622-uart",
267 + "mediatek,mt6577-uart";
268 + reg = <0 0x11003000 0 0x400>;
269 + interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
270 + clocks = <&topckgen CLK_TOP_UART_SEL>,
271 + <&pericfg CLK_PERI_UART1_PD>;
272 + clock-names = "baud", "bus";
273 + status = "disabled";
274 + };
275 +
276 + uart2: serial@11004000 {
277 + compatible = "mediatek,mt7622-uart",
278 + "mediatek,mt6577-uart";
279 + reg = <0 0x11004000 0 0x400>;
280 + interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
281 + clocks = <&topckgen CLK_TOP_UART_SEL>,
282 + <&pericfg CLK_PERI_UART2_PD>;
283 + clock-names = "baud", "bus";
284 + status = "disabled";
285 + };
286 +
287 + uart3: serial@11005000 {
288 + compatible = "mediatek,mt7622-uart",
289 + "mediatek,mt6577-uart";
290 + reg = <0 0x11005000 0 0x400>;
291 + interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>;
292 + clocks = <&topckgen CLK_TOP_UART_SEL>,
293 + <&pericfg CLK_PERI_UART3_PD>;
294 + clock-names = "baud", "bus";
295 + status = "disabled";
296 + };
297 +
298 + pwm: pwm@11006000 {
299 + compatible = "mediatek,mt7622-pwm";
300 + reg = <0 0x11006000 0 0x1000>;
301 + interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>;
302 + clocks = <&topckgen CLK_TOP_PWM_SEL>,
303 + <&pericfg CLK_PERI_PWM_PD>,
304 + <&pericfg CLK_PERI_PWM1_PD>,
305 + <&pericfg CLK_PERI_PWM2_PD>,
306 + <&pericfg CLK_PERI_PWM3_PD>,
307 + <&pericfg CLK_PERI_PWM4_PD>,
308 + <&pericfg CLK_PERI_PWM5_PD>,
309 + <&pericfg CLK_PERI_PWM6_PD>;
310 + clock-names = "top", "main", "pwm1", "pwm2", "pwm3", "pwm4",
311 + "pwm5", "pwm6";
312 + status = "disabled";
313 + };
314 +
315 + i2c0: i2c@11007000 {
316 + compatible = "mediatek,mt7622-i2c";
317 + reg = <0 0x11007000 0 0x90>,
318 + <0 0x11000100 0 0x80>;
319 + interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>;
320 + clock-div = <16>;
321 + clocks = <&pericfg CLK_PERI_I2C0_PD>,
322 + <&pericfg CLK_PERI_AP_DMA_PD>;
323 + clock-names = "main", "dma";
324 + #address-cells = <1>;
325 + #size-cells = <0>;
326 + status = "disabled";
327 + };
328 +
329 + i2c1: i2c@11008000 {
330 + compatible = "mediatek,mt7622-i2c";
331 + reg = <0 0x11008000 0 0x90>,
332 + <0 0x11000180 0 0x80>;
333 + interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>;
334 + clock-div = <16>;
335 + clocks = <&pericfg CLK_PERI_I2C1_PD>,
336 + <&pericfg CLK_PERI_AP_DMA_PD>;
337 + clock-names = "main", "dma";
338 + #address-cells = <1>;
339 + #size-cells = <0>;
340 + status = "disabled";
341 + };
342 +
343 + i2c2: i2c@11009000 {
344 + compatible = "mediatek,mt7622-i2c";
345 + reg = <0 0x11009000 0 0x90>,
346 + <0 0x11000200 0 0x80>;
347 + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>;
348 + clock-div = <16>;
349 + clocks = <&pericfg CLK_PERI_I2C2_PD>,
350 + <&pericfg CLK_PERI_AP_DMA_PD>;
351 + clock-names = "main", "dma";
352 + #address-cells = <1>;
353 + #size-cells = <0>;
354 + status = "disabled";
355 + };
356 +
357 + spi0: spi@1100a000 {
358 + compatible = "mediatek,mt7622-spi";
359 + reg = <0 0x1100a000 0 0x100>;
360 + interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_LOW>;
361 + clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
362 + <&topckgen CLK_TOP_SPI0_SEL>,
363 + <&pericfg CLK_PERI_SPI0_PD>;
364 + clock-names = "parent-clk", "sel-clk", "spi-clk";
365 + #address-cells = <1>;
366 + #size-cells = <0>;
367 + status = "disabled";
368 + };
369 +
370 + thermal: thermal@1100b000 {
371 + #thermal-sensor-cells = <1>;
372 + compatible = "mediatek,mt7622-thermal";
373 + reg = <0 0x1100b000 0 0x1000>;
374 + interrupts = <0 78 IRQ_TYPE_LEVEL_LOW>;
375 + clocks = <&pericfg CLK_PERI_THERM_PD>,
376 + <&pericfg CLK_PERI_AUXADC_PD>;
377 + clock-names = "therm", "auxadc";
378 + resets = <&pericfg MT7622_PERI_THERM_SW_RST>;
379 + reset-names = "therm";
380 + mediatek,auxadc = <&auxadc>;
381 + mediatek,apmixedsys = <&apmixedsys>;
382 + nvmem-cells = <&thermal_calibration>;
383 + nvmem-cell-names = "calibration-data";
384 + };
385 +
386 + btif: serial@1100c000 {
387 + compatible = "mediatek,mt7622-btif",
388 + "mediatek,mtk-btif";
389 + reg = <0 0x1100c000 0 0x1000>;
390 + interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_LOW>;
391 + clocks = <&pericfg CLK_PERI_BTIF_PD>;
392 + clock-names = "main";
393 + reg-shift = <2>;
394 + reg-io-width = <4>;
395 + status = "disabled";
396 + };
397 +
398 + spi1: spi@11016000 {
399 + compatible = "mediatek,mt7622-spi";
400 + reg = <0 0x11016000 0 0x100>;
401 + interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_LOW>;
402 + clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
403 + <&topckgen CLK_TOP_SPI1_SEL>,
404 + <&pericfg CLK_PERI_SPI1_PD>;
405 + clock-names = "parent-clk", "sel-clk", "spi-clk";
406 + #address-cells = <1>;
407 + #size-cells = <0>;
408 + status = "disabled";
409 + };
410 +
411 + uart4: serial@11019000 {
412 + compatible = "mediatek,mt7622-uart",
413 + "mediatek,mt6577-uart";
414 + reg = <0 0x11019000 0 0x400>;
415 + interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_LOW>;
416 + clocks = <&topckgen CLK_TOP_UART_SEL>,
417 + <&pericfg CLK_PERI_UART4_PD>;
418 + clock-names = "baud", "bus";
419 + status = "disabled";
420 + };
421 +
422 ssusbsys: ssusbsys@1a000000 {
423 compatible = "mediatek,mt7622-ssusbsys",
424 "syscon";
425 --
426 2.11.0
427
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