1 From a69ac853def2f93194e244974f611477a1521a4a Mon Sep 17 00:00:00 2001
2 From: Sean Wang <sean.wang@mediatek.com>
3 Date: Thu, 28 Dec 2017 18:18:26 +0800
4 Subject: [PATCH 216/224] arm64: dts: mt7622: add SoC and peripheral related
7 Add watchdog, rtc, auxadc, cir, efuse, rng, uart[1-4], pwm, i2c[0-2],
8 spi[0-1], btif and thermal related nodes.
10 Signed-off-by: Sean Wang <sean.wang@mediatek.com>
11 Cc: Andrew-CT Chen <andrew-ct.chen@mediatek.com>
12 Cc: Zhiyong Tao <zhiyong.tao@mediatek.com>
13 Cc: Zhi Mao <zhi.mao@mediatek.com>
14 Cc: Jun Gao <jun.gao@mediatek.com>
15 Cc: Leilk Liu <leilk.liu@mediatek.com>
16 Cc: Matthias Brugger <matthias.bgg@gmail.com>
18 arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts | 54 ++++++
19 arch/arm64/boot/dts/mediatek/mt7622.dtsi | 264 +++++++++++++++++++++++++++
20 2 files changed, 318 insertions(+)
22 --- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
23 +++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
33 + pinctrl-names = "default";
34 + pinctrl-0 = <&irrx_pins>;
39 + pinctrl-names = "default";
40 + pinctrl-0 = <&i2c1_pins>;
45 + pinctrl-names = "default";
46 + pinctrl-0 = <&i2c2_pins>;
51 + pinctrl-names = "default";
52 + pinctrl-0 = <&pwm7_pins>;
57 pinctrl-names = "default";
58 pinctrl-0 = <&pmic_bus_pins>;
64 + pinctrl-names = "default";
65 + pinctrl-0 = <&spic0_pins>;
70 + pinctrl-names = "default";
71 + pinctrl-0 = <&spic1_pins>;
76 + pinctrl-names = "default";
77 + pinctrl-0 = <&uart0_pins>;
82 + pinctrl-names = "default";
83 + pinctrl-0 = <&uart2_pins>;
88 + pinctrl-names = "default";
89 + pinctrl-0 = <&watchdog_pins>;
92 --- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
93 +++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
95 #include <dt-bindings/clock/mt7622-clk.h>
96 #include <dt-bindings/power/mt7622-power.h>
97 #include <dt-bindings/reset/mt7622-reset.h>
98 +#include <dt-bindings/thermal/thermal.h>
101 compatible = "mediatek,mt7622";
103 <&apmixedsys CLK_APMIXED_MAIN_CORE_EN>;
104 clock-names = "cpu", "intermediate";
105 operating-points-v2 = <&cpu_opp_table>;
106 + #cooling-cells = <2>;
107 enable-method = "psci";
108 clock-frequency = <1300000000>;
115 + cpu_thermal: cpu-thermal {
116 + polling-delay-passive = <1000>;
117 + polling-delay = <1000>;
119 + thermal-sensors = <&thermal 0>;
122 + cpu_passive: cpu-passive {
123 + temperature = <47000>;
124 + hysteresis = <2000>;
128 + cpu_active: cpu-active {
129 + temperature = <67000>;
130 + hysteresis = <2000>;
135 + temperature = <87000>;
136 + hysteresis = <2000>;
141 + temperature = <107000>;
142 + hysteresis = <2000>;
149 + trip = <&cpu_passive>;
150 + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
154 + trip = <&cpu_active>;
155 + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
160 + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
167 compatible = "arm,armv8-timer";
168 interrupt-parent = <&gic>;
170 clock-names = "hif_sel";
173 + cir: cir@10009000 {
174 + compatible = "mediatek,mt7622-cir";
175 + reg = <0 0x10009000 0 0x1000>;
176 + interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_LOW>;
177 + clocks = <&infracfg CLK_INFRA_IRRX_PD>,
178 + <&topckgen CLK_TOP_AXI_SEL>;
179 + clock-names = "clk", "bus";
180 + status = "disabled";
183 sysirq: interrupt-controller@10200620 {
184 compatible = "mediatek,mt7622-sysirq",
185 "mediatek,mt6577-sysirq";
187 reg = <0 0x10200620 0 0x20>;
190 + efuse: efuse@10206000 {
191 + compatible = "mediatek,mt7622-efuse",
193 + reg = <0 0x10206000 0 0x1000>;
194 + #address-cells = <1>;
197 + thermal_calibration: calib@198 {
202 apmixedsys: apmixedsys@10209000 {
203 compatible = "mediatek,mt7622-apmixedsys",
209 + rng: rng@1020f000 {
210 + compatible = "mediatek,mt7622-rng",
211 + "mediatek,mt7623-rng";
212 + reg = <0 0x1020f000 0 0x1000>;
213 + clocks = <&infracfg CLK_INFRA_TRNG>;
214 + clock-names = "rng";
217 pio: pinctrl@10211000 {
218 compatible = "mediatek,mt7622-pinctrl";
219 reg = <0 0x10211000 0 0x1000>;
224 + watchdog: watchdog@10212000 {
225 + compatible = "mediatek,mt7622-wdt",
226 + "mediatek,mt6589-wdt";
227 + reg = <0 0x10212000 0 0x800>;
230 + rtc: rtc@10212800 {
231 + compatible = "mediatek,mt7622-rtc",
232 + "mediatek,soc-rtc";
233 + reg = <0 0x10212800 0 0x200>;
234 + interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_LOW>;
235 + clocks = <&topckgen CLK_TOP_RTC>;
236 + clock-names = "rtc";
239 gic: interrupt-controller@10300000 {
240 compatible = "arm,gic-400";
241 interrupt-controller;
243 <0 0x10360000 0 0x2000>;
246 + auxadc: adc@11001000 {
247 + compatible = "mediatek,mt7622-auxadc";
248 + reg = <0 0x11001000 0 0x1000>;
249 + clocks = <&pericfg CLK_PERI_AUXADC_PD>;
250 + clock-names = "main";
251 + #io-channel-cells = <1>;
254 uart0: serial@11002000 {
255 compatible = "mediatek,mt7622-uart",
256 "mediatek,mt6577-uart";
257 @@ -227,6 +334,163 @@
258 clock-names = "baud", "bus";
262 + uart1: serial@11003000 {
263 + compatible = "mediatek,mt7622-uart",
264 + "mediatek,mt6577-uart";
265 + reg = <0 0x11003000 0 0x400>;
266 + interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
267 + clocks = <&topckgen CLK_TOP_UART_SEL>,
268 + <&pericfg CLK_PERI_UART1_PD>;
269 + clock-names = "baud", "bus";
270 + status = "disabled";
273 + uart2: serial@11004000 {
274 + compatible = "mediatek,mt7622-uart",
275 + "mediatek,mt6577-uart";
276 + reg = <0 0x11004000 0 0x400>;
277 + interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
278 + clocks = <&topckgen CLK_TOP_UART_SEL>,
279 + <&pericfg CLK_PERI_UART2_PD>;
280 + clock-names = "baud", "bus";
281 + status = "disabled";
284 + uart3: serial@11005000 {
285 + compatible = "mediatek,mt7622-uart",
286 + "mediatek,mt6577-uart";
287 + reg = <0 0x11005000 0 0x400>;
288 + interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>;
289 + clocks = <&topckgen CLK_TOP_UART_SEL>,
290 + <&pericfg CLK_PERI_UART3_PD>;
291 + clock-names = "baud", "bus";
292 + status = "disabled";
295 + pwm: pwm@11006000 {
296 + compatible = "mediatek,mt7622-pwm";
297 + reg = <0 0x11006000 0 0x1000>;
298 + interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>;
299 + clocks = <&topckgen CLK_TOP_PWM_SEL>,
300 + <&pericfg CLK_PERI_PWM_PD>,
301 + <&pericfg CLK_PERI_PWM1_PD>,
302 + <&pericfg CLK_PERI_PWM2_PD>,
303 + <&pericfg CLK_PERI_PWM3_PD>,
304 + <&pericfg CLK_PERI_PWM4_PD>,
305 + <&pericfg CLK_PERI_PWM5_PD>,
306 + <&pericfg CLK_PERI_PWM6_PD>;
307 + clock-names = "top", "main", "pwm1", "pwm2", "pwm3", "pwm4",
309 + status = "disabled";
312 + i2c0: i2c@11007000 {
313 + compatible = "mediatek,mt7622-i2c";
314 + reg = <0 0x11007000 0 0x90>,
315 + <0 0x11000100 0 0x80>;
316 + interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>;
318 + clocks = <&pericfg CLK_PERI_I2C0_PD>,
319 + <&pericfg CLK_PERI_AP_DMA_PD>;
320 + clock-names = "main", "dma";
321 + #address-cells = <1>;
323 + status = "disabled";
326 + i2c1: i2c@11008000 {
327 + compatible = "mediatek,mt7622-i2c";
328 + reg = <0 0x11008000 0 0x90>,
329 + <0 0x11000180 0 0x80>;
330 + interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>;
332 + clocks = <&pericfg CLK_PERI_I2C1_PD>,
333 + <&pericfg CLK_PERI_AP_DMA_PD>;
334 + clock-names = "main", "dma";
335 + #address-cells = <1>;
337 + status = "disabled";
340 + i2c2: i2c@11009000 {
341 + compatible = "mediatek,mt7622-i2c";
342 + reg = <0 0x11009000 0 0x90>,
343 + <0 0x11000200 0 0x80>;
344 + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>;
346 + clocks = <&pericfg CLK_PERI_I2C2_PD>,
347 + <&pericfg CLK_PERI_AP_DMA_PD>;
348 + clock-names = "main", "dma";
349 + #address-cells = <1>;
351 + status = "disabled";
354 + spi0: spi@1100a000 {
355 + compatible = "mediatek,mt7622-spi";
356 + reg = <0 0x1100a000 0 0x100>;
357 + interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_LOW>;
358 + clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
359 + <&topckgen CLK_TOP_SPI0_SEL>,
360 + <&pericfg CLK_PERI_SPI0_PD>;
361 + clock-names = "parent-clk", "sel-clk", "spi-clk";
362 + #address-cells = <1>;
364 + status = "disabled";
367 + thermal: thermal@1100b000 {
368 + #thermal-sensor-cells = <1>;
369 + compatible = "mediatek,mt7622-thermal";
370 + reg = <0 0x1100b000 0 0x1000>;
371 + interrupts = <0 78 IRQ_TYPE_LEVEL_LOW>;
372 + clocks = <&pericfg CLK_PERI_THERM_PD>,
373 + <&pericfg CLK_PERI_AUXADC_PD>;
374 + clock-names = "therm", "auxadc";
375 + resets = <&pericfg MT7622_PERI_THERM_SW_RST>;
376 + reset-names = "therm";
377 + mediatek,auxadc = <&auxadc>;
378 + mediatek,apmixedsys = <&apmixedsys>;
379 + nvmem-cells = <&thermal_calibration>;
380 + nvmem-cell-names = "calibration-data";
383 + btif: serial@1100c000 {
384 + compatible = "mediatek,mt7622-btif",
385 + "mediatek,mtk-btif";
386 + reg = <0 0x1100c000 0 0x1000>;
387 + interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_LOW>;
388 + clocks = <&pericfg CLK_PERI_BTIF_PD>;
389 + clock-names = "main";
391 + reg-io-width = <4>;
392 + status = "disabled";
395 + spi1: spi@11016000 {
396 + compatible = "mediatek,mt7622-spi";
397 + reg = <0 0x11016000 0 0x100>;
398 + interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_LOW>;
399 + clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
400 + <&topckgen CLK_TOP_SPI1_SEL>,
401 + <&pericfg CLK_PERI_SPI1_PD>;
402 + clock-names = "parent-clk", "sel-clk", "spi-clk";
403 + #address-cells = <1>;
405 + status = "disabled";
408 + uart4: serial@11019000 {
409 + compatible = "mediatek,mt7622-uart",
410 + "mediatek,mt6577-uart";
411 + reg = <0 0x11019000 0 0x400>;
412 + interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_LOW>;
413 + clocks = <&topckgen CLK_TOP_UART_SEL>,
414 + <&pericfg CLK_PERI_UART4_PD>;
415 + clock-names = "baud", "bus";
416 + status = "disabled";
419 ssusbsys: ssusbsys@1a000000 {
420 compatible = "mediatek,mt7622-ssusbsys",