1 From e84732bd6022dd12839dd34d508eb27428367c24 Mon Sep 17 00:00:00 2001
2 From: Ryder Lee <ryder.lee@mediatek.com>
3 Date: Wed, 20 Dec 2017 15:57:30 +0800
4 Subject: [PATCH 219/224] arm64: dts: mt7622: add PCIe device nodes
6 This patch adds PCIe support fot MT7622.
8 Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
9 Signed-off-by: Sean Wang <sean.wang@mediatek.com>
11 arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts | 10 ++++
12 arch/arm64/boot/dts/mediatek/mt7622.dtsi | 74 ++++++++++++++++++++++++++++
13 2 files changed, 84 insertions(+)
15 --- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
16 +++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
22 + pinctrl-names = "default";
23 + pinctrl-0 = <&pcie0_pins>;
32 /* eMMC is shared pin with parallel NAND */
33 emmc_pins_default: emmc-pins-default {
34 --- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
35 +++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
40 + pcie: pcie@1a140000 {
41 + compatible = "mediatek,mt7622-pcie";
42 + device_type = "pci";
43 + reg = <0 0x1a140000 0 0x1000>,
44 + <0 0x1a143000 0 0x1000>,
45 + <0 0x1a145000 0 0x1000>;
46 + reg-names = "subsys", "port0", "port1";
47 + #address-cells = <3>;
49 + interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_LOW>,
50 + <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;
51 + clocks = <&pciesys CLK_PCIE_P0_MAC_EN>,
52 + <&pciesys CLK_PCIE_P1_MAC_EN>,
53 + <&pciesys CLK_PCIE_P0_AHB_EN>,
54 + <&pciesys CLK_PCIE_P0_AHB_EN>,
55 + <&pciesys CLK_PCIE_P0_AUX_EN>,
56 + <&pciesys CLK_PCIE_P1_AUX_EN>,
57 + <&pciesys CLK_PCIE_P0_AXI_EN>,
58 + <&pciesys CLK_PCIE_P1_AXI_EN>,
59 + <&pciesys CLK_PCIE_P0_OBFF_EN>,
60 + <&pciesys CLK_PCIE_P1_OBFF_EN>,
61 + <&pciesys CLK_PCIE_P0_PIPE_EN>,
62 + <&pciesys CLK_PCIE_P1_PIPE_EN>;
63 + clock-names = "sys_ck0", "sys_ck1", "ahb_ck0", "ahb_ck1",
64 + "aux_ck0", "aux_ck1", "axi_ck0", "axi_ck1",
65 + "obff_ck0", "obff_ck1", "pipe_ck0", "pipe_ck1";
66 + power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
67 + bus-range = <0x00 0xff>;
68 + ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>;
69 + status = "disabled";
72 + reg = <0x0000 0 0 0 0>;
73 + #address-cells = <3>;
75 + #interrupt-cells = <1>;
77 + status = "disabled";
80 + interrupt-map-mask = <0 0 0 7>;
81 + interrupt-map = <0 0 0 1 &pcie_intc0 0>,
82 + <0 0 0 2 &pcie_intc0 1>,
83 + <0 0 0 3 &pcie_intc0 2>,
84 + <0 0 0 4 &pcie_intc0 3>;
85 + pcie_intc0: interrupt-controller {
86 + interrupt-controller;
87 + #address-cells = <0>;
88 + #interrupt-cells = <1>;
93 + reg = <0x0800 0 0 0 0>;
94 + #address-cells = <3>;
96 + #interrupt-cells = <1>;
98 + status = "disabled";
101 + interrupt-map-mask = <0 0 0 7>;
102 + interrupt-map = <0 0 0 1 &pcie_intc1 0>,
103 + <0 0 0 2 &pcie_intc1 1>,
104 + <0 0 0 3 &pcie_intc1 2>,
105 + <0 0 0 4 &pcie_intc1 3>;
106 + pcie_intc1: interrupt-controller {
107 + interrupt-controller;
108 + #address-cells = <0>;
109 + #interrupt-cells = <1>;
114 ethsys: syscon@1b000000 {
115 compatible = "mediatek,mt7622-ethsys",