1 From 3e23988f5c9c5d54732eda1e8017409ef223048b Mon Sep 17 00:00:00 2001
2 From: Chunfeng Yun <chunfeng.yun@mediatek.com>
3 Date: Fri, 12 Jan 2018 12:28:31 +0800
4 Subject: [PATCH 221/224] arm64: dts: mt7622: add usb device nodes
6 add xhci node and usb3 phy nodes
8 Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
9 Signed-off-by: Sean Wang <sean.wang@mediatek.com>
10 Tested-by: Jumin Li <jumin.li@mediatek.com>
12 arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts | 28 +++++++++++++++
13 arch/arm64/boot/dts/mediatek/mt7622.dtsi | 51 ++++++++++++++++++++++++++++
14 2 files changed, 79 insertions(+)
16 --- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
17 +++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
20 reg = <0 0x40000000 0 0x3F000000>;
23 + reg_3p3v: regulator-3p3v {
24 + compatible = "regulator-fixed";
25 + regulator-name = "fixed-3.3V";
26 + regulator-min-microvolt = <3300000>;
27 + regulator-max-microvolt = <3300000>;
29 + regulator-always-on;
32 + reg_5v: regulator-5v {
33 + compatible = "regulator-fixed";
34 + regulator-name = "fixed-5V";
35 + regulator-min-microvolt = <5000000>;
36 + regulator-max-microvolt = <5000000>;
38 + regulator-always-on;
48 + vusb33-supply = <®_3p3v>;
49 + vbus-supply = <®_5v>;
58 pinctrl-names = "default";
59 pinctrl-0 = <&uart0_pins>;
60 --- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
61 +++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
66 + ssusb: usb@1a0c0000 {
67 + compatible = "mediatek,mt7622-xhci",
68 + "mediatek,mtk-xhci";
69 + reg = <0 0x1a0c0000 0 0x01000>,
70 + <0 0x1a0c4700 0 0x0100>;
71 + reg-names = "mac", "ippc";
72 + interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_LOW>;
73 + power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF1>;
74 + clocks = <&ssusbsys CLK_SSUSB_SYS_EN>,
75 + <&ssusbsys CLK_SSUSB_REF_EN>,
76 + <&ssusbsys CLK_SSUSB_MCU_EN>,
77 + <&ssusbsys CLK_SSUSB_DMA_EN>;
78 + clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck";
79 + phys = <&u2port0 PHY_TYPE_USB2>,
80 + <&u3port0 PHY_TYPE_USB3>,
81 + <&u2port1 PHY_TYPE_USB2>;
83 + status = "disabled";
86 + u3phy: usb-phy@1a0c4000 {
87 + compatible = "mediatek,mt7622-u3phy",
88 + "mediatek,generic-tphy-v1";
89 + reg = <0 0x1a0c4000 0 0x700>;
90 + #address-cells = <2>;
93 + status = "disabled";
95 + u2port0: usb-phy@1a0c4800 {
96 + reg = <0 0x1a0c4800 0 0x0100>;
98 + clocks = <&ssusbsys CLK_SSUSB_U2_PHY_EN>;
99 + clock-names = "ref";
102 + u3port0: usb-phy@1a0c4900 {
103 + reg = <0 0x1a0c4900 0 0x0700>;
105 + clocks = <&clk25m>;
106 + clock-names = "ref";
109 + u2port1: usb-phy@1a0c5000 {
110 + reg = <0 0x1a0c5000 0 0x0100>;
112 + clocks = <&ssusbsys CLK_SSUSB_U2_PHY_1P_EN>;
113 + clock-names = "ref";
117 pciesys: pciesys@1a100800 {
118 compatible = "mediatek,mt7622-pciesys",