1 From d41d41bfcbd8ad4bcbb1b433f7d5c3b613c58419 Mon Sep 17 00:00:00 2001
2 From: Sean Wang <sean.wang@mediatek.com>
3 Date: Mon, 22 Jan 2018 16:58:36 +0800
4 Subject: [PATCH 223/224] arm64: dts: mt7622: add mmc related device nodes
6 add mmc device nodes and proper setup for used pins
8 Signed-off-by: Sean Wang <sean.wang@mediatek.com>
9 Signed-off-by: Jimin Wang <jimin.wang@mediatek.com>
11 arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts | 106 +++++++++++++++++++++++++++
12 arch/arm64/boot/dts/mediatek/mt7622.dtsi | 20 +++++
13 2 files changed, 126 insertions(+)
15 --- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
16 +++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
20 #include <dt-bindings/input/input.h>
21 +#include <dt-bindings/gpio/gpio.h>
23 #include "mt7622.dtsi"
24 #include "mt6380.dtsi"
26 reg = <0 0x40000000 0 0x3F000000>;
29 + reg_1p8v: regulator-1p8v {
30 + compatible = "regulator-fixed";
31 + regulator-name = "fixed-1.8V";
32 + regulator-min-microvolt = <1800000>;
33 + regulator-max-microvolt = <1800000>;
34 + regulator-always-on;
37 reg_3p3v: regulator-3p3v {
38 compatible = "regulator-fixed";
39 regulator-name = "fixed-3.3V";
41 function = "emmc", "emmc_rst";
45 + /* "NDL0","NDL1","NDL2","NDL3","NDL4","NDL5","NDL6","NDL7",
46 + * "NRB","NCLE" pins are used as DAT0,DAT1,DAT2,DAT3,DAT4,
47 + * DAT5,DAT6,DAT7,CMD,CLK for eMMC respectively
50 + pins = "NDL0", "NDL1", "NDL2",
51 + "NDL3", "NDL4", "NDL5",
52 + "NDL6", "NDL7", "NRB";
63 emmc_pins_uhs: emmc-pins-uhs {
70 + pins = "NDL0", "NDL1", "NDL2",
71 + "NDL3", "NDL4", "NDL5",
72 + "NDL6", "NDL7", "NRB";
74 + drive-strength = <4>;
80 + drive-strength = <4>;
91 + /* "I2S2_OUT, "I2S4_IN"", "I2S3_IN", "I2S2_IN",
92 + * "I2S4_OUT", "I2S3_OUT" are used as DAT0, DAT1,
93 + * DAT2, DAT3, CMD, CLK for SD respectively.
96 + pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
97 + "I2S2_IN","I2S4_OUT";
99 + drive-strength = <8>;
104 + drive-strength = <12>;
113 sd0_pins_uhs: sd0-pins-uhs {
120 + pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
121 + "I2S2_IN","I2S4_OUT";
132 /* Serial NAND is shared pin with SPI-NOR */
138 + pinctrl-names = "default", "state_uhs";
139 + pinctrl-0 = <&emmc_pins_default>;
140 + pinctrl-1 = <&emmc_pins_uhs>;
143 + max-frequency = <50000000>;
146 + vmmc-supply = <®_3p3v>;
147 + vqmmc-supply = <®_1p8v>;
148 + assigned-clocks = <&topckgen CLK_TOP_MSDC30_0_SEL>;
149 + assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
154 + pinctrl-names = "default", "state_uhs";
155 + pinctrl-0 = <&sd0_pins_default>;
156 + pinctrl-1 = <&sd0_pins_uhs>;
159 + max-frequency = <50000000>;
162 + cd-gpios = <&pio 81 GPIO_ACTIVE_LOW>;
163 + vmmc-supply = <®_3p3v>;
164 + vqmmc-supply = <®_3p3v>;
165 + assigned-clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>;
166 + assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
170 pinctrl-names = "default";
171 pinctrl-0 = <¶llel_nand_pins>;
172 --- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
173 +++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
178 + mmc0: mmc@11230000 {
179 + compatible = "mediatek,mt7622-mmc";
180 + reg = <0 0x11230000 0 0x1000>;
181 + interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
182 + clocks = <&pericfg CLK_PERI_MSDC30_0_PD>,
183 + <&topckgen CLK_TOP_MSDC50_0_SEL>;
184 + clock-names = "source", "hclk";
185 + status = "disabled";
188 + mmc1: mmc@11240000 {
189 + compatible = "mediatek,mt7622-mmc";
190 + reg = <0 0x11240000 0 0x1000>;
191 + interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>;
192 + clocks = <&pericfg CLK_PERI_MSDC30_1_PD>,
193 + <&topckgen CLK_TOP_AXI_SEL>;
194 + clock-names = "source", "hclk";
195 + status = "disabled";
198 ssusbsys: ssusbsys@1a000000 {
199 compatible = "mediatek,mt7622-ssusbsys",