target/linux/mediatek/patches-4.14/0223-arm64-dts-mt7622-add-mmc-related-device-nodes.patch

   1 From d41d41bfcbd8ad4bcbb1b433f7d5c3b613c58419 Mon Sep 17 00:00:00 2001
   2 From: Sean Wang <sean.wang@mediatek.com>
   3 Date: Mon, 22 Jan 2018 16:58:36 +0800
   4 Subject: [PATCH 223/224] arm64: dts: mt7622: add mmc related device nodes
   5
   6 add mmc device nodes and proper setup for used pins
   7
   8 Signed-off-by: Sean Wang <sean.wang@mediatek.com>
   9 Signed-off-by: Jimin Wang <jimin.wang@mediatek.com>
  10 ---
  11  arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts | 106 +++++++++++++++++++++++++++
  12  arch/arm64/boot/dts/mediatek/mt7622.dtsi     |  20 +++++
  13  2 files changed, 126 insertions(+)
  14
  15 diff --git a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
  16 index cc89e2e3c597..45d8655ee423 100644
  17 --- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
  18 +++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
  19 @@ -8,6 +8,7 @@
  20
  21  /dts-v1/;
  22  #include <dt-bindings/input/input.h>
  23 +#include <dt-bindings/gpio/gpio.h>
  24
  25  #include "mt7622.dtsi"
  26  #include "mt6380.dtsi"
  27 @@ -53,6 +54,14 @@
  28                 reg = <0 0x40000000 0 0x3F000000>;
  29         };
  30
  31 +       reg_1p8v: regulator-1p8v {
  32 +               compatible = "regulator-fixed";
  33 +               regulator-name = "fixed-1.8V";
  34 +               regulator-min-microvolt = <1800000>;
  35 +               regulator-max-microvolt = <1800000>;
  36 +               regulator-always-on;
  37 +       };
  38 +
  39         reg_3p3v: regulator-3p3v {
  40                 compatible = "regulator-fixed";
  41                 regulator-name = "fixed-3.3V";
  42 @@ -89,6 +98,23 @@
  43                         function = "emmc", "emmc_rst";
  44                         groups = "emmc";
  45                 };
  46 +
  47 +               /* "NDL0","NDL1","NDL2","NDL3","NDL4","NDL5","NDL6","NDL7",
  48 +                * "NRB","NCLE" pins are used as DAT0,DAT1,DAT2,DAT3,DAT4,
  49 +                * DAT5,DAT6,DAT7,CMD,CLK for eMMC respectively
  50 +                */
  51 +               conf-cmd-dat {
  52 +                       pins = "NDL0", "NDL1", "NDL2",
  53 +                              "NDL3", "NDL4", "NDL5",
  54 +                              "NDL6", "NDL7", "NRB";
  55 +                       input-enable;
  56 +                       bias-pull-up;
  57 +               };
  58 +
  59 +               conf-clk {
  60 +                       pins = "NCLE";
  61 +                       bias-pull-down;
  62 +               };
  63         };
  64
  65         emmc_pins_uhs: emmc-pins-uhs {
  66 @@ -96,6 +122,21 @@
  67                         function = "emmc";
  68                         groups = "emmc";
  69                 };
  70 +
  71 +               conf-cmd-dat {
  72 +                       pins = "NDL0", "NDL1", "NDL2",
  73 +                              "NDL3", "NDL4", "NDL5",
  74 +                              "NDL6", "NDL7", "NRB";
  75 +                       input-enable;
  76 +                       drive-strength = <4>;
  77 +                       bias-pull-up;
  78 +               };
  79 +
  80 +               conf-clk {
  81 +                       pins = "NCLE";
  82 +                       drive-strength = <4>;
  83 +                       bias-pull-down;
  84 +               };
  85         };
  86
  87         eth_pins: eth-pins {
  88 @@ -194,6 +235,27 @@
  89                         function = "sd";
  90                         groups = "sd_0";
  91                 };
  92 +
  93 +               /* "I2S2_OUT, "I2S4_IN"", "I2S3_IN", "I2S2_IN",
  94 +                *  "I2S4_OUT", "I2S3_OUT" are used as DAT0, DAT1,
  95 +                *  DAT2, DAT3, CMD, CLK for SD respectively.
  96 +                */
  97 +               conf-cmd-data {
  98 +                       pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
  99 +                              "I2S2_IN","I2S4_OUT";
 100 +                       input-enable;
 101 +                       drive-strength = <8>;
 102 +                       bias-pull-up;
 103 +               };
 104 +               conf-clk {
 105 +                       pins = "I2S3_OUT";
 106 +                       drive-strength = <12>;
 107 +                       bias-pull-down;
 108 +               };
 109 +               conf-cd {
 110 +                       pins = "TXD3";
 111 +                       bias-pull-up;
 112 +               };
 113         };
 114
 115         sd0_pins_uhs: sd0-pins-uhs {
 116 @@ -201,6 +263,18 @@
 117                         function = "sd";
 118                         groups = "sd_0";
 119                 };
 120 +
 121 +               conf-cmd-data {
 122 +                       pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
 123 +                              "I2S2_IN","I2S4_OUT";
 124 +                       input-enable;
 125 +                       bias-pull-up;
 126 +               };
 127 +
 128 +               conf-clk {
 129 +                       pins = "I2S3_OUT";
 130 +                       bias-pull-down;
 131 +               };
 132         };
 133
 134         /* Serial NAND is shared pin with SPI-NOR */
 135 @@ -311,6 +385,38 @@
 136         status = "okay";
 137  };
 138
 139 +&mmc0 {
 140 +       pinctrl-names = "default", "state_uhs";
 141 +       pinctrl-0 = <&emmc_pins_default>;
 142 +       pinctrl-1 = <&emmc_pins_uhs>;
 143 +       status = "okay";
 144 +       bus-width = <8>;
 145 +       max-frequency = <50000000>;
 146 +       cap-mmc-highspeed;
 147 +       mmc-hs200-1_8v;
 148 +       vmmc-supply = <&reg_3p3v>;
 149 +       vqmmc-supply = <&reg_1p8v>;
 150 +       assigned-clocks = <&topckgen CLK_TOP_MSDC30_0_SEL>;
 151 +       assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
 152 +       non-removable;
 153 +};
 154 +
 155 +&mmc1 {
 156 +       pinctrl-names = "default", "state_uhs";
 157 +       pinctrl-0 = <&sd0_pins_default>;
 158 +       pinctrl-1 = <&sd0_pins_uhs>;
 159 +       status = "okay";
 160 +       bus-width = <4>;
 161 +       max-frequency = <50000000>;
 162 +       cap-sd-highspeed;
 163 +       r_smpl = <1>;
 164 +       cd-gpios = <&pio 81 GPIO_ACTIVE_LOW>;
 165 +       vmmc-supply = <&reg_3p3v>;
 166 +       vqmmc-supply = <&reg_3p3v>;
 167 +       assigned-clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>;
 168 +       assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
 169 +};
 170 +
 171  &nandc {
 172         pinctrl-names = "default";
 173         pinctrl-0 = <&parallel_nand_pins>;
 174 diff --git a/arch/arm64/boot/dts/mediatek/mt7622.dtsi b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
 175 index ffb934b0a097..0f1ebddd6619 100644
 176 --- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
 177 +++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
 178 @@ -527,6 +527,26 @@
 179                 status = "disabled";
 180         };
 181
 182 +       mmc0: mmc@11230000 {
 183 +               compatible = "mediatek,mt7622-mmc";
 184 +               reg = <0 0x11230000 0 0x1000>;
 185 +               interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
 186 +               clocks = <&pericfg CLK_PERI_MSDC30_0_PD>,
 187 +                        <&topckgen CLK_TOP_MSDC50_0_SEL>;
 188 +               clock-names = "source", "hclk";
 189 +               status = "disabled";
 190 +       };
 191 +
 192 +       mmc1: mmc@11240000 {
 193 +               compatible = "mediatek,mt7622-mmc";
 194 +               reg = <0 0x11240000 0 0x1000>;
 195 +               interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>;
 196 +               clocks = <&pericfg CLK_PERI_MSDC30_1_PD>,
 197 +                        <&topckgen CLK_TOP_AXI_SEL>;
 198 +               clock-names = "source", "hclk";
 199 +               status = "disabled";
 200 +       };
 201 +
 202         ssusbsys: ssusbsys@1a000000 {
 203                 compatible = "mediatek,mt7622-ssusbsys",
 204                              "syscon";
 205 --
 206 2.11.0
 207