1 From 004eb24e939b5b31f828333f37fb5cb2a877d6f2 Mon Sep 17 00:00:00 2001
2 From: Kristian Evensen <kristian.evensen@gmail.com>
3 Date: Sun, 17 Jun 2018 14:41:47 +0200
4 Subject: [PATCH] arm: dts: Add Unielec U7623 DTS
7 arch/arm/boot/dts/Makefile | 1 +
8 .../dts/mt7623a-unielec-u7623-02-emmc-512M.dts | 18 +
9 .../boot/dts/mt7623a-unielec-u7623-02-emmc.dtsi | 366 +++++++++++++++++++++
10 3 files changed, 385 insertions(+)
11 create mode 100644 arch/arm/boot/dts/mt7623a-unielec-u7623-02-emmc-512M.dts
12 create mode 100644 arch/arm/boot/dts/mt7623a-unielec-u7623-02-emmc.dtsi
14 diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
15 index 3fec84fa0..e685ce9a4 100644
16 --- a/arch/arm/boot/dts/Makefile
17 +++ b/arch/arm/boot/dts/Makefile
18 @@ -1062,6 +1062,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
21 mt7623a-rfb-emmc.dtb \
22 + mt7623a-unielec-u7623-02-emmc-512M.dtb \
23 mt7623n-rfb-nand.dtb \
24 mt7623n-bananapi-bpi-r2.dtb \
26 diff --git a/arch/arm/boot/dts/mt7623a-unielec-u7623-02-emmc-512M.dts b/arch/arm/boot/dts/mt7623a-unielec-u7623-02-emmc-512M.dts
28 index 000000000..857d440d0
30 +++ b/arch/arm/boot/dts/mt7623a-unielec-u7623-02-emmc-512M.dts
33 + * Copyright 2018 Kristian Evensen <kristian.evensen@gmail.com>
35 + * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
39 +#include "mt7623a-unielec-u7623-02-emmc.dtsi"
42 + model = "UniElec U7623-02 eMMC (512M RAM)";
43 + compatible = "unielec,u7623-02-emmc-512m", "unielec,u7623-02-emmc", "mediatek,mt7623";
46 + device_type = "memory";
47 + reg = <0 0x80000000 0 0x20000000>;
50 diff --git a/arch/arm/boot/dts/mt7623a-unielec-u7623-02-emmc.dtsi b/arch/arm/boot/dts/mt7623a-unielec-u7623-02-emmc.dtsi
52 index 000000000..adc91266e
54 +++ b/arch/arm/boot/dts/mt7623a-unielec-u7623-02-emmc.dtsi
57 + * Copyright 2018 Kristian Evensen <kristian.evensen@gmail.com>
59 + * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
62 +#include <dt-bindings/input/input.h>
63 +#include "mt7623.dtsi"
64 +#include "mt6323.dtsi"
67 + compatible = "unielec,u7623-02-emmc", "mediatek,mt7623";
74 + bootargs = "root=/dev/mmcblk0p2 rootfstype=squashfs,f2fs";
75 + stdout-path = "serial2:115200n8";
80 + proc-supply = <&mt6323_vproc_reg>;
84 + proc-supply = <&mt6323_vproc_reg>;
88 + proc-supply = <&mt6323_vproc_reg>;
92 + proc-supply = <&mt6323_vproc_reg>;
96 + reg_1p8v: regulator-1p8v {
97 + compatible = "regulator-fixed";
98 + regulator-name = "fixed-1.8V";
99 + regulator-min-microvolt = <1800000>;
100 + regulator-max-microvolt = <1800000>;
102 + regulator-always-on;
105 + reg_3p3v: regulator-3p3v {
106 + compatible = "regulator-fixed";
107 + regulator-name = "fixed-3.3V";
108 + regulator-min-microvolt = <3300000>;
109 + regulator-max-microvolt = <3300000>;
111 + regulator-always-on;
114 + reg_5v: regulator-5v {
115 + compatible = "regulator-fixed";
116 + regulator-name = "fixed-5V";
117 + regulator-min-microvolt = <5000000>;
118 + regulator-max-microvolt = <5000000>;
120 + regulator-always-on;
124 + compatible = "gpio-keys";
125 + pinctrl-names = "default";
126 + pinctrl-0 = <&key_pins_a>;
130 + linux,code = <KEY_RESTART>;
131 + gpios = <&pio 256 GPIO_ACTIVE_LOW>;
136 + compatible = "gpio-leds";
137 + pinctrl-names = "default";
138 + pinctrl-0 = <&led_pins_unielec>;
141 + label = "u7623-01:green:led3";
142 + gpios = <&pio 14 GPIO_ACTIVE_LOW>;
143 + default-state = "off";
147 + label = "u7623-01:green:led4";
148 + gpios = <&pio 15 GPIO_ACTIVE_LOW>;
149 + default-state = "off";
154 + compatible = "mediatek,mt7530";
155 + #address-cells = <1>;
168 + compatible = "mediatek,eth-mac";
170 + phy-mode = "trgmii";
180 + #address-cells = <1>;
182 + phy5: ethernet-phy@5 {
184 + phy-mode = "rgmii-rxid";
190 + compatible = "mediatek,mt7530";
191 + #address-cells = <1>;
194 + pinctrl-names = "default";
196 + resets = <ðsys 2>;
197 + reset-names = "mcm";
198 + core-supply = <&mt6323_vpa_reg>;
199 + io-supply = <&mt6323_vemc3v3_reg>;
201 + dsa,mii-bus = <&mdio>;
204 + #address-cells = <1>;
211 + cpu = <&cpu_port0>;
217 + cpu = <&cpu_port0>;
223 + cpu = <&cpu_port0>;
229 + cpu = <&cpu_port0>;
235 + cpu = <&cpu_port0>;
238 + cpu_port0: port@6 {
241 + ethernet = <&gmac0>;
242 + phy-mode = "trgmii";
253 + pinctrl-names = "default", "state_uhs";
254 + pinctrl-0 = <&mmc0_pins_default>;
255 + pinctrl-1 = <&mmc0_pins_uhs>;
258 + max-frequency = <50000000>;
260 + vmmc-supply = <®_3p3v>;
261 + vqmmc-supply = <®_1p8v>;
266 + key_pins_a: keys-alt {
268 + pinmux = <MT7623_PIN_256_GPIO256_FUNC_GPIO256>,
269 + <MT7623_PIN_257_GPIO257_FUNC_GPIO257>;
274 + led_pins_unielec: leds-unielec {
276 + pinmux = <MT7623_PIN_14_GPIO14_FUNC_GPIO14>,
277 + <MT7623_PIN_15_GPIO15_FUNC_GPIO15>;
281 + mmc0_pins_default: mmc0default {
283 + pinmux = <MT7623_PIN_111_MSDC0_DAT7_FUNC_MSDC0_DAT7>,
284 + <MT7623_PIN_112_MSDC0_DAT6_FUNC_MSDC0_DAT6>,
285 + <MT7623_PIN_113_MSDC0_DAT5_FUNC_MSDC0_DAT5>,
286 + <MT7623_PIN_114_MSDC0_DAT4_FUNC_MSDC0_DAT4>,
287 + <MT7623_PIN_118_MSDC0_DAT3_FUNC_MSDC0_DAT3>,
288 + <MT7623_PIN_119_MSDC0_DAT2_FUNC_MSDC0_DAT2>,
289 + <MT7623_PIN_120_MSDC0_DAT1_FUNC_MSDC0_DAT1>,
290 + <MT7623_PIN_121_MSDC0_DAT0_FUNC_MSDC0_DAT0>,
291 + <MT7623_PIN_116_MSDC0_CMD_FUNC_MSDC0_CMD>;
297 + pinmux = <MT7623_PIN_117_MSDC0_CLK_FUNC_MSDC0_CLK>;
302 + pinmux = <MT7623_PIN_115_MSDC0_RSTB_FUNC_MSDC0_RSTB>;
307 + mmc0_pins_uhs: mmc0 {
309 + pinmux = <MT7623_PIN_111_MSDC0_DAT7_FUNC_MSDC0_DAT7>,
310 + <MT7623_PIN_112_MSDC0_DAT6_FUNC_MSDC0_DAT6>,
311 + <MT7623_PIN_113_MSDC0_DAT5_FUNC_MSDC0_DAT5>,
312 + <MT7623_PIN_114_MSDC0_DAT4_FUNC_MSDC0_DAT4>,
313 + <MT7623_PIN_118_MSDC0_DAT3_FUNC_MSDC0_DAT3>,
314 + <MT7623_PIN_119_MSDC0_DAT2_FUNC_MSDC0_DAT2>,
315 + <MT7623_PIN_120_MSDC0_DAT1_FUNC_MSDC0_DAT1>,
316 + <MT7623_PIN_121_MSDC0_DAT0_FUNC_MSDC0_DAT0>,
317 + <MT7623_PIN_116_MSDC0_CMD_FUNC_MSDC0_CMD>;
319 + drive-strength = <MTK_DRIVE_2mA>;
320 + bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
324 + pinmux = <MT7623_PIN_117_MSDC0_CLK_FUNC_MSDC0_CLK>;
325 + drive-strength = <MTK_DRIVE_2mA>;
326 + bias-pull-down = <MTK_PUPD_SET_R1R0_01>;
330 + pinmux = <MT7623_PIN_115_MSDC0_RSTB_FUNC_MSDC0_RSTB>;
335 + pwm_pins_a: pwm@0 {
337 + pinmux = <MT7623_PIN_203_PWM0_FUNC_PWM0>,
338 + <MT7623_PIN_204_PWM1_FUNC_PWM1>,
339 + <MT7623_PIN_205_PWM2_FUNC_PWM2>,
340 + <MT7623_PIN_206_PWM3_FUNC_PWM3>,
341 + <MT7623_PIN_207_PWM4_FUNC_PWM4>;
345 + uart2_pins_b: uart@2 {
347 + pinmux = <MT7623_PIN_200_URXD2_FUNC_URXD2>,
348 + <MT7623_PIN_201_UTXD2_FUNC_UTXD2>;
352 + pcie_default: pcie_pin_default {
354 + pinmux = <MT7623_PIN_208_AUD_EXT_CK1_FUNC_PCIE0_PERST_N>,
355 + <MT7623_PIN_209_AUD_EXT_CK2_FUNC_PCIE1_PERST_N>;
362 + pinctrl-names = "default";
363 + pinctrl-0 = <&pwm_pins_a>;
370 + compatible = "mediatek,mt6323-led";
371 + #address-cells = <1>;
377 + default-state = "off";
384 + pinctrl-names = "default";
385 + pinctrl-0 = <&uart2_pins_b>;
390 + vusb33-supply = <®_3p3v>;
391 + vbus-supply = <®_3p3v>;
401 + mediatek,phy-switch = <&hifsys>;
405 + pinctrl-names = "default";
406 + pinctrl-0 = <&pcie_default>;