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[openwrt/staging/jow.git] / target / linux / mediatek / patches-4.19 / 0003-mt7531-gsw-internal_phy_calibration.patch
1 --- a/drivers/net/phy/mtk/mt753x/Makefile
2 +++ b/drivers/net/phy/mtk/mt753x/Makefile
3 @@ -7,5 +7,5 @@ obj-$(CONFIG_MT753X_GSW) += mt753x.o
4 mt753x-$(CONFIG_SWCONFIG) += mt753x_swconfig.o
5
6 mt753x-y += mt753x_mdio.o mt7530.o mt7531.o \
7 - mt753x_common.o mt753x_nl.o
8 + mt753x_common.o mt753x_nl.o mt753x_phy.o
9
10 --- a/drivers/net/phy/mtk/mt753x/mt7531.c
11 +++ b/drivers/net/phy/mtk/mt753x/mt7531.c
12 @@ -582,6 +582,18 @@ static void mt7531_core_pll_setup(struct
13
14 static int mt7531_internal_phy_calibration(struct gsw_mt753x *gsw)
15 {
16 + u32 i, val;
17 + int ret;
18 + val = gsw->mmd_read(gsw, 0, PHY_DEV1F, PHY_DEV1F_REG_403);
19 + val |= GBE_EFUSE_SETTING;
20 + gsw->mmd_write(gsw, 0, PHY_DEV1F, PHY_DEV1F_REG_403, val);
21 + for (i = 0; i < 5; i++) {
22 + ret = mt753x_phy_calibration(gsw, i);
23 + /* set Auto-negotiation with giga extension. */
24 + gsw->mii_write(gsw, i, 0, 0x1340);
25 + if (ret)
26 + return ret;
27 + }
28 return 0;
29 }
30
31 --- a/drivers/net/phy/mtk/mt753x/mt753x.h
32 +++ b/drivers/net/phy/mtk/mt753x/mt753x.h
33 @@ -147,6 +147,8 @@ void mt753x_mmd_ind_write(struct gsw_mt7
34 void mt753x_irq_worker(struct work_struct *work);
35 void mt753x_irq_enable(struct gsw_mt753x *gsw);
36
37 +int mt753x_phy_calibration(struct gsw_mt753x *gsw, u8 phyaddr);
38 +
39 /* MDIO Indirect Access Registers */
40 #define MII_MMD_ACC_CTL_REG 0x0d
41 #define MMD_CMD_S 14
42 --- /dev/null
43 +++ b/drivers/net/phy/mtk/mt753x/mt753x_phy.c
44 @@ -0,0 +1,947 @@
45 +// SPDX-License-Identifier: GPL-2.0+
46 +/*
47 + * Common part for MediaTek MT753x gigabit switch
48 + *
49 + * Copyright (C) 2018 MediaTek Inc. All Rights Reserved.
50 + *
51 + * Author: Weijie Gao <weijie.gao@mediatek.com>
52 + */
53 +
54 +#include <linux/kernel.h>
55 +#include <linux/delay.h>
56 +
57 +#include "mt753x.h"
58 +#include "mt753x_regs.h"
59 +#include "mt753x_phy.h"
60 +
61 +u32 tc_phy_read_dev_reg(struct gsw_mt753x *gsw, u32 port_num, u32 dev_addr, u32 reg_addr)
62 +{
63 + u32 phy_val;
64 + phy_val = gsw->mmd_read(gsw, port_num, dev_addr, reg_addr);
65 + return phy_val;
66 +}
67 +
68 +void tc_phy_write_dev_reg(struct gsw_mt753x *gsw, u32 port_num, u32 dev_addr, u32 reg_addr, u32 write_data)
69 +{
70 + u32 phy_val;
71 + gsw->mmd_write(gsw, port_num, dev_addr, reg_addr, write_data);
72 + phy_val = gsw->mmd_read(gsw, port_num, dev_addr, reg_addr);
73 +}
74 +
75 +void switch_phy_write(struct gsw_mt753x *gsw, u32 port_num, u32 reg_addr, u32 write_data){
76 + gsw->mii_write(gsw, port_num, reg_addr, write_data);
77 +}
78 +
79 +u32 switch_phy_read(struct gsw_mt753x *gsw, u32 port_num, u32 reg_addr){
80 + return gsw->mii_read(gsw, port_num, reg_addr);
81 +}
82 +
83 +const u8 MT753x_ZCAL_TO_R50ohm_GE_TBL_100[64] = {
84 + 127, 127, 127, 127, 127, 127, 127, 127,
85 + 127, 127, 127, 127, 127, 123, 122, 117,
86 + 115, 112, 103, 100, 98, 87, 85, 83,
87 + 81, 72, 70, 68, 66, 64, 55, 53,
88 + 52, 50, 49, 48, 38, 36, 35, 34,
89 + 33, 32, 22, 21, 20, 19, 18, 17,
90 + 16, 7, 6, 5, 4, 3, 2, 1,
91 + 0, 0, 0, 0, 0, 0, 0, 0
92 +};
93 +
94 +const u8 MT753x_TX_OFFSET_TBL[64] = {
95 + 0x1f, 0x1e, 0x1d, 0x1c, 0x1b, 0x1a, 0x19, 0x18,
96 + 0x17, 0x16, 0x15, 0x14, 0x13, 0x12, 0x11, 0x10,
97 + 0xf, 0xe, 0xd, 0xc, 0xb, 0xa, 0x9, 0x8,
98 + 0x7, 0x6, 0x5, 0x4, 0x3, 0x2, 0x1, 0x0,
99 + 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27,
100 + 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f,
101 + 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37,
102 + 0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f
103 +};
104 +
105 +u8 ge_cal_flag;
106 +
107 +u8 all_ge_ana_cal_wait(struct gsw_mt753x *gsw, u32 delay, u32 phyaddr) // for EN7512
108 +{
109 + u8 all_ana_cal_status;
110 + u32 cnt, tmp_1e_17c;
111 + tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x17c, 0x0001);
112 + cnt = 10000;
113 + do {
114 + udelay(delay);
115 + cnt--;
116 + all_ana_cal_status = tc_phy_read_dev_reg(gsw, PHY0, 0x1e, 0x17b) & 0x1;
117 +
118 + } while ((all_ana_cal_status == 0) && (cnt != 0));
119 +
120 +
121 + if(all_ana_cal_status == 1) {
122 + tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x17c, 0);
123 + return all_ana_cal_status;
124 + } else {
125 + pr_info("MDC/MDIO error\n");
126 + return 0;
127 + }
128 +
129 + return all_ana_cal_status;
130 +}
131 +
132 +
133 +
134 +
135 +int ge_cal_rext(struct gsw_mt753x *gsw, u8 phyaddr, u32 delay)
136 +{
137 + u8 rg_zcal_ctrl, all_ana_cal_status;
138 + u16 ad_cal_comp_out_init;
139 + u16 dev1e_e0_ana_cal_r5;
140 + int calibration_polarity;
141 + u8 cnt = 0;
142 + u16 dev1e_17a_tmp, dev1e_e0_tmp;
143 +
144 + //tc_phy_write_dev_reg(phyaddr, 0x1e, 0x00db, 0x1110)
145 + tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x00db, 0x1110);
146 + //tc_phy_write_dev_reg(phyaddr, 0x1e, 0x00dc, 0x0000);
147 + tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x00dc, 0);
148 + //tc_phy_write_dev_reg(phyaddr, 0x1e, 0x00e1, 0x0000);
149 + //tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x00e1, 0x10);
150 +
151 + rg_zcal_ctrl = 0x20;
152 + dev1e_e0_ana_cal_r5 = tc_phy_read_dev_reg(gsw, PHY0, 0x1e, 0xe0);
153 + tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0xe0, rg_zcal_ctrl);
154 + all_ana_cal_status = all_ge_ana_cal_wait(gsw, delay, phyaddr);/* delay 20 usec */
155 + if (all_ana_cal_status == 0) {
156 + all_ana_cal_status = ANACAL_ERROR;
157 + printk(" GE Rext AnaCal ERROR init! \r\n");
158 + return -1;
159 + }
160 + ad_cal_comp_out_init = (tc_phy_read_dev_reg(gsw, PHY0, 0x1e, 0x017a) >> 8) & 0x1;
161 + if (ad_cal_comp_out_init == 1)
162 + calibration_polarity = -1;
163 + else /* ad_cal_comp_out_init == 0 */
164 + calibration_polarity = 1;
165 + cnt = 0;
166 + while (all_ana_cal_status < ANACAL_ERROR) {
167 + cnt++;
168 + rg_zcal_ctrl += calibration_polarity;
169 + tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0xe0, (rg_zcal_ctrl));
170 + all_ana_cal_status = all_ge_ana_cal_wait(gsw, delay, phyaddr); /* delay 20 usec */
171 + dev1e_17a_tmp = tc_phy_read_dev_reg(gsw, PHY0, 0x1e, 0x017a);
172 + if (all_ana_cal_status == 0) {
173 + all_ana_cal_status = ANACAL_ERROR;
174 + printk(" GE Rext AnaCal ERROR 2! \r\n");
175 + return -1;
176 + } else if (((dev1e_17a_tmp >> 8) & 0x1) != ad_cal_comp_out_init) {
177 + all_ana_cal_status = ANACAL_FINISH;
178 + //printk(" GE Rext AnaCal Done! (%d)(0x%x) \r\n", cnt, rg_zcal_ctrl);
179 + } else {
180 + dev1e_17a_tmp = tc_phy_read_dev_reg(gsw, PHY0, 0x1e, 0x017a);
181 + dev1e_e0_tmp = tc_phy_read_dev_reg(gsw, PHY0, 0x1e, 0xe0);
182 + if ((rg_zcal_ctrl == 0x3F) || (rg_zcal_ctrl == 0x00)) {
183 + all_ana_cal_status = ANACAL_SATURATION;
184 + printk(" GE Rext AnaCal Saturation! \r\n");
185 + rg_zcal_ctrl = 0x20; /* 0 dB */
186 + }
187 + }
188 + }
189 +
190 + if (all_ana_cal_status == ANACAL_ERROR) {
191 + rg_zcal_ctrl = 0x20;
192 + tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x00e0, (dev1e_e0_ana_cal_r5 | rg_zcal_ctrl));
193 + } else if(all_ana_cal_status == ANACAL_FINISH){
194 + //tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x00e0, (dev1e_e0_ana_cal_r5 | rg_zcal_ctrl));
195 + tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x00e0, ((rg_zcal_ctrl << 8) | rg_zcal_ctrl));
196 + printk("0x1e-e0 = %x\n", tc_phy_read_dev_reg(gsw, PHY0, 0x1e, 0x00e0));
197 + tc_phy_write_dev_reg(gsw, PHY0, 0x1f, 0x0115, ((rg_zcal_ctrl & 0x3f) >> 3));
198 + printk("0x1f-115 = %x\n", tc_phy_read_dev_reg(gsw, PHY0, 0x1f, 0x115));
199 + printk(" GE Rext AnaCal Done! (%d)(0x%x) \r\n", cnt, rg_zcal_ctrl);
200 + ge_cal_flag = 1;
201 + } else {
202 + printk("GE Rxet cal something wrong2\n");
203 + }
204 + tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x00db, 0x0000);
205 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00db, 0x0000);
206 + tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x00dc, 0x0000);
207 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00dc, 0x0000);
208 +}
209 +
210 +//-----------------------------------------------------------------
211 +int ge_cal_r50(struct gsw_mt753x *gsw, u8 phyaddr, u32 delay)
212 +{
213 + u8 rg_zcal_ctrl, all_ana_cal_status, calibration_pair;
214 + u16 ad_cal_comp_out_init;
215 + u16 dev1e_e0_ana_cal_r5;
216 + int calibration_polarity;
217 + u8 cnt = 0;
218 + tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x00db, 0x1100);
219 + tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x00dc, 0x0000);
220 +
221 + for(calibration_pair = ANACAL_PAIR_A; calibration_pair <= ANACAL_PAIR_D; calibration_pair ++) {
222 + rg_zcal_ctrl = 0x20;
223 + dev1e_e0_ana_cal_r5 = (tc_phy_read_dev_reg(gsw, PHY0, 0x1e, 0x00e0) & (~0x003f));
224 + tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x00e0, (dev1e_e0_ana_cal_r5 | rg_zcal_ctrl));
225 + if(calibration_pair == ANACAL_PAIR_A)
226 + {
227 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00db, 0x1101);
228 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00dc, 0x0000);
229 + //printk("R50 pair A 1e_db=%x 1e_db=%x\n", tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x00db), tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x00dc));
230 +
231 + }
232 + else if(calibration_pair == ANACAL_PAIR_B)
233 + {
234 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00db, 0x1100);
235 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00dc, 0x1000);
236 + //printk("R50 pair B 1e_db=%x 1e_db=%x\n", tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x00db),tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x00dc));
237 +
238 + }
239 + else if(calibration_pair == ANACAL_PAIR_C)
240 + {
241 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00db, 0x1100);
242 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00dc, 0x0100);
243 + //printk("R50 pair C 1e_db=%x 1e_db=%x\n", tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x00db), tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x00dc));
244 +
245 + }
246 + else // if(calibration_pair == ANACAL_PAIR_D)
247 + {
248 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00db, 0x1100);
249 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00dc, 0x0010);
250 + //printk("R50 pair D 1e_db=%x 1e_db=%x\n", tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x00db), tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x00dc));
251 +
252 + }
253 +
254 + all_ana_cal_status = all_ge_ana_cal_wait(gsw, delay, phyaddr); // delay 20 usec
255 + if(all_ana_cal_status == 0)
256 + {
257 + all_ana_cal_status = ANACAL_ERROR;
258 + printk( "GE R50 AnaCal ERROR init! \r\n");
259 + return -1;
260 + }
261 +
262 + ad_cal_comp_out_init = (tc_phy_read_dev_reg(gsw, PHY0, 0x1e, 0x017a)>>8) & 0x1;
263 + if(ad_cal_comp_out_init == 1)
264 + calibration_polarity = -1;
265 + else
266 + calibration_polarity = 1;
267 +
268 + cnt = 0;
269 + while(all_ana_cal_status < ANACAL_ERROR)
270 + {
271 + cnt ++;
272 + rg_zcal_ctrl += calibration_polarity;
273 + tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x00e0, (dev1e_e0_ana_cal_r5 | rg_zcal_ctrl));
274 + all_ana_cal_status = all_ge_ana_cal_wait(gsw, delay, phyaddr); // delay 20 usec
275 +
276 + if(all_ana_cal_status == 0)
277 + {
278 + all_ana_cal_status = ANACAL_ERROR;
279 + printk( " GE R50 AnaCal ERROR 2! \r\n");
280 + return -1;
281 + }
282 + else if(((tc_phy_read_dev_reg(gsw, PHY0, 0x1e, 0x017a)>>8)&0x1) != ad_cal_comp_out_init)
283 + {
284 + all_ana_cal_status = ANACAL_FINISH;
285 + }
286 + else {
287 + if((rg_zcal_ctrl == 0x3F)||(rg_zcal_ctrl == 0x00))
288 + {
289 + all_ana_cal_status = ANACAL_SATURATION; // need to FT
290 + printk( " GE R50 AnaCal Saturation! \r\n");
291 + }
292 + }
293 + }
294 +
295 + if(all_ana_cal_status == ANACAL_ERROR) {
296 + rg_zcal_ctrl = 0x20;
297 + //tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00e0, (dev1e_e0_ana_cal_r5 | rg_zcal_ctrl));
298 + }
299 + else {
300 + rg_zcal_ctrl = MT753x_ZCAL_TO_R50ohm_GE_TBL_100[rg_zcal_ctrl - 9];
301 + printk( " GE R50 AnaCal Done! (%d) (0x%x)(0x%x) \r\n", cnt, rg_zcal_ctrl, (rg_zcal_ctrl|0x80));
302 + }
303 +
304 + if(calibration_pair == ANACAL_PAIR_A) {
305 + ad_cal_comp_out_init = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0174) & (~0x7f00);
306 + //ad_cal_comp_out_init = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0174);
307 + //printk( " GE-a 1e_174(0x%x)(0x%x), 1e_175(0x%x) \r\n", tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0174), ad_cal_comp_out_init, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0175));
308 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x0174, (ad_cal_comp_out_init | (((rg_zcal_ctrl<<8)&0xff00) | 0x8000)));
309 + //printk( " GE-a 1e_174(0x%x), 1e_175(0x%x) \r\n", tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0174), tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0175));
310 + }
311 + else if(calibration_pair == ANACAL_PAIR_B) {
312 + ad_cal_comp_out_init = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0174) & (~0x007f);
313 + //ad_cal_comp_out_init = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0174);
314 + //printk( " GE-b 1e_174(0x%x)(0x%x), 1e_175(0x%x) \r\n", tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0174), ad_cal_comp_out_init, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0175));
315 +
316 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x0174, (ad_cal_comp_out_init | (((rg_zcal_ctrl<<0)&0x00ff) | 0x0080)));
317 + //printk( " GE-b 1e_174(0x%x), 1e_175(0x%x) \r\n", tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0174), tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0175));
318 + }
319 + else if(calibration_pair == ANACAL_PAIR_C) {
320 + ad_cal_comp_out_init = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0175) & (~0x7f00);
321 + //ad_cal_comp_out_init = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0175);
322 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x0175, (ad_cal_comp_out_init | (((rg_zcal_ctrl<<8)&0xff00) | 0x8000)));
323 + //printk( " GE-c 1e_174(0x%x), 1e_175(0x%x) \r\n", tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0174), tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0175));
324 + } else {// if(calibration_pair == ANACAL_PAIR_D)
325 + ad_cal_comp_out_init = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0175) & (~0x007f);
326 + //ad_cal_comp_out_init = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0175);
327 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x0175, (ad_cal_comp_out_init | (((rg_zcal_ctrl<<0)&0x00ff) | 0x0080)));
328 + //printk( " GE-d 1e_174(0x%x), 1e_175(0x%x) \r\n", tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0174), tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0175));
329 + }
330 + //tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00e0, ((rg_zcal_ctrl<<8)|rg_zcal_ctrl));
331 + }
332 +
333 + printk( " GE 1e_174(0x%x), 1e_175(0x%x) \r\n", tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0174), tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0175));
334 + tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x00db, 0x0000);
335 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00db, 0x0000);
336 + tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x00dc, 0x0000);
337 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00dc, 0x0000);
338 +}
339 +
340 +int ge_cal_tx_offset(struct gsw_mt753x *gsw, u8 phyaddr, u32 delay)
341 +{
342 + u8 all_ana_cal_status, calibration_pair;
343 + u16 ad_cal_comp_out_init;
344 + int calibration_polarity, tx_offset_temp;
345 + u8 tx_offset_reg_shift, tabl_idx, i;
346 + u8 cnt = 0;
347 + u16 tx_offset_reg, reg_temp, cal_temp;
348 + tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x00db, 0x0100);
349 + tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x00dc, 0x0001);
350 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x0096, 0x8000);
351 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x003e, 0xf808);
352 + for(i = 0; i <= 4; i++)
353 + tc_phy_write_dev_reg(gsw, i, 0x1e, 0x00dd, 0x0000);
354 + for(calibration_pair = ANACAL_PAIR_A; calibration_pair <= ANACAL_PAIR_D; calibration_pair ++)
355 + {
356 + tabl_idx = 31;
357 + tx_offset_temp = MT753x_TX_OFFSET_TBL[tabl_idx];
358 +
359 + if(calibration_pair == ANACAL_PAIR_A) {
360 + //tc_phy_write_dev_reg(phyaddr, 0x1e, 0x145, 0x5010);
361 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00dd, 0x1000);
362 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x017d, (0x8000|DAC_IN_0V));
363 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x0181, (0x8000|DAC_IN_0V));
364 + //printk("tx offset pairA 1e_dd = %x, 1e_17d=%x, 1e_181=%x\n", tc_phy_read_dev_reg(phyaddr, 0x1e, 0x00dd), tc_phy_read_dev_reg(phyaddr, 0x1e, 0x017d), tc_phy_read_dev_reg(phyaddr, 0x1e, 0x0181));
365 + reg_temp = (tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0172) & (~0x3f00));
366 + tx_offset_reg_shift = 8;
367 + tx_offset_reg = 0x0172;
368 +
369 + //tc_phy_write_dev_reg(phyaddr, 0x1e, tx_offset_reg, (reg_temp|(tx_offset_temp<<tx_offset_reg_shift)));
370 + } else if(calibration_pair == ANACAL_PAIR_B) {
371 + //tc_phy_write_dev_reg(phyaddr, 0x1e, 0x145, 0x5018);
372 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00dd, 0x0100);
373 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x017e, (0x8000|DAC_IN_0V));
374 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x0182, (0x8000|DAC_IN_0V));
375 + //printk("tx offset pairB 1e_dd = %x, 1e_17d=%x, 1e_181=%x\n", tc_phy_read_dev_reg(phyaddr, 0x1e, 0x00dd), tc_phy_read_dev_reg(phyaddr, 0x1e, 0x017d), tc_phy_read_dev_reg(phyaddr, 0x1e, 0x0181));
376 + reg_temp = (tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0172) & (~0x003f));
377 + tx_offset_reg_shift = 0;
378 + tx_offset_reg = 0x0172;
379 + //tc_phy_write_dev_reg(phyaddr, 0x1e, tx_offset_reg, (reg_temp|(tx_offset_temp<<tx_offset_reg_shift)));
380 + } else if(calibration_pair == ANACAL_PAIR_C) {
381 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00dd, 0x0010);
382 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x017f, (0x8000|DAC_IN_0V));
383 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x0183, (0x8000|DAC_IN_0V));
384 + reg_temp = (tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0173) & (~0x3f00));
385 + //printk("tx offset pairC 1e_dd = %x, 1e_17d=%x, 1e_181=%x\n", tc_phy_read_dev_reg(phyaddr, 0x1e, 0x00dd), tc_phy_read_dev_reg(phyaddr, 0x1e, 0x017d), tc_phy_read_dev_reg(phyaddr, 0x1e, 0x0181));
386 + tx_offset_reg_shift = 8;
387 + tx_offset_reg = 0x0173;
388 + //tc_phy_write_dev_reg(phyaddr, 0x1e, tx_offset_reg, (reg_temp|(tx_offset_temp<<tx_offset_reg_shift)));
389 + } else {// if(calibration_pair == ANACAL_PAIR_D)
390 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00dd, 0x0001);
391 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x0180, (0x8000|DAC_IN_0V));
392 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x0184, (0x8000|DAC_IN_0V));
393 + //printk("tx offset pairD 1e_dd = %x, 1e_17d=%x, 1e_181=%x\n", tc_phy_read_dev_reg(phyaddr, 0x1e, 0x00dd), tc_phy_read_dev_reg(phyaddr, 0x1e, 0x017d), tc_phy_read_dev_reg(phyaddr, 0x1e, 0x0181));
394 + reg_temp = (tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x0173) & (~0x003f));
395 + tx_offset_reg_shift = 0;
396 + tx_offset_reg = 0x0173;
397 + //tc_phy_write_dev_reg(phyaddr, 0x1e, tx_offset_reg, (reg_temp|(tx_offset_temp<<tx_offset_reg_shift)));
398 + }
399 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, tx_offset_reg, (reg_temp|(tx_offset_temp<<tx_offset_reg_shift)));
400 + all_ana_cal_status = all_ge_ana_cal_wait(gsw, delay, phyaddr); // delay 20 usec
401 + if(all_ana_cal_status == 0) {
402 + all_ana_cal_status = ANACAL_ERROR;
403 + printk( " GE Tx offset AnaCal ERROR init! \r\n");
404 + return -1;
405 + }
406 +
407 + ad_cal_comp_out_init = (tc_phy_read_dev_reg(gsw, PHY0, 0x1e, 0x017a)>>8) & 0x1;
408 + if(ad_cal_comp_out_init == 1)
409 + calibration_polarity = 1;
410 + else
411 + calibration_polarity = -1;
412 +
413 + cnt = 0;
414 + //printk("TX offset cnt = %d, tabl_idx= %x, offset_val = %x\n", cnt, tabl_idx, MT753x_TX_OFFSET_TBL[tabl_idx]);
415 + while(all_ana_cal_status < ANACAL_ERROR) {
416 +
417 + cnt ++;
418 + tabl_idx += calibration_polarity;
419 + //tx_offset_temp += calibration_polarity;
420 + //cal_temp = tx_offset_temp;
421 + cal_temp = MT753x_TX_OFFSET_TBL[tabl_idx];
422 + //printk("TX offset cnt = %d, tabl_idx= %x, offset_val = %x\n", cnt, tabl_idx, MT753x_TX_OFFSET_TBL[tabl_idx]);
423 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, tx_offset_reg, (reg_temp|(cal_temp<<tx_offset_reg_shift)));
424 +
425 + all_ana_cal_status = all_ge_ana_cal_wait(gsw, delay, phyaddr); // delay 20 usec
426 + if(all_ana_cal_status == 0) {
427 + all_ana_cal_status = ANACAL_ERROR;
428 + printk( " GE Tx offset AnaCal ERROR init 2! \r\n");
429 + return -1;
430 + } else if(((tc_phy_read_dev_reg(gsw, PHY0, 0x1e, 0x017a)>>8)&0x1) != ad_cal_comp_out_init) {
431 + all_ana_cal_status = ANACAL_FINISH;
432 + } else {
433 + if((tabl_idx == 0)||(tabl_idx == 0x3f)) {
434 + all_ana_cal_status = ANACAL_SATURATION;
435 + printk( " GE Tx offset AnaCal Saturation! \r\n");
436 + }
437 + }
438 + }
439 +
440 + if(all_ana_cal_status == ANACAL_ERROR) {
441 + tx_offset_temp = TX_AMP_OFFSET_0MV;
442 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, tx_offset_reg, (reg_temp|(tx_offset_temp<<tx_offset_reg_shift)));
443 + } else {
444 + printk( " GE Tx offset AnaCal Done! (pair-%d)(%d)(0x%x) 0x1e_%x=0x%x\n", calibration_pair, cnt, MT753x_TX_OFFSET_TBL[tabl_idx], tx_offset_reg, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_offset_reg));
445 + }
446 + }
447 +
448 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x017d, 0x0000);
449 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x017e, 0x0000);
450 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x017f, 0x0000);
451 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x0180, 0x0000);
452 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x0181, 0x0000);
453 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x0182, 0x0000);
454 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x0183, 0x0000);
455 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x0184, 0x0000);
456 +
457 + tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x00db, 0x0000);
458 + tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x00dc, 0x0000);
459 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00db, 0x0000);
460 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00dc, 0x0000);
461 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x003e, 0x0000);
462 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00dd, 0x0000);
463 +}
464 +
465 +int ge_cal_tx_amp(struct gsw_mt753x *gsw, u8 phyaddr, u32 delay)
466 +{
467 + u8 all_ana_cal_status, calibration_pair, i;
468 + u16 ad_cal_comp_out_init;
469 + int calibration_polarity;
470 + u32 tx_amp_reg_shift;
471 + u16 reg_temp;
472 + u32 tx_amp_temp, tx_amp_reg, cnt=0, tx_amp_reg_100;
473 + u32 reg_backup, reg_tmp;
474 + tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x00db, 0x1100);
475 + tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x00dc, 0x0001);
476 + tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x00e1, 0x0010);
477 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x003e, 0xf808);
478 +
479 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x11, 0xff00);
480 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1f, 0x27a, 0x33);
481 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0xc9, 0xffff);
482 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1f, 0x300, 0x4);
483 + for(i = 0; i <= 4; i++)
484 + tc_phy_write_dev_reg(gsw, i, 0x1e, 0x00dd, 0x0000);
485 + for(calibration_pair = ANACAL_PAIR_A; calibration_pair <= ANACAL_PAIR_D; calibration_pair ++) {
486 + tx_amp_temp = 0x20;
487 +
488 + if(calibration_pair == ANACAL_PAIR_A) {
489 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00dd, 0x1000); // 1e_dd[12]
490 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x017d, (0x8000|DAC_IN_2V)); // 1e_17d
491 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x0181, (0x8000|DAC_IN_2V)); // 1e_181
492 + reg_temp = (tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x012) & (~0xfc00));
493 + tx_amp_reg_shift = 10; // 1e_12[15:10]
494 + tx_amp_reg = 0x12;
495 + tx_amp_reg_100 = 0x16;
496 + } else if(calibration_pair == ANACAL_PAIR_B) {
497 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00dd, 0x0100); // 1e_dd[8]
498 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x017e, (0x8000|DAC_IN_2V)); // 1e_17e
499 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x0182, (0x8000|DAC_IN_2V)); // 1e_182
500 + reg_temp = (tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x017) & (~0x3f00));
501 + tx_amp_reg_shift = 8; // 1e_17[13:8]
502 + tx_amp_reg = 0x17;
503 + tx_amp_reg_100 = 0x18;
504 + } else if(calibration_pair == ANACAL_PAIR_C) {
505 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00dd, 0x0010); // 1e_dd[4]
506 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x017f, (0x8000|DAC_IN_2V)); // 1e_17f
507 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x0183, (0x8000|DAC_IN_2V)); // 1e_183
508 + reg_temp = (tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x019) & (~0x3f00));
509 + tx_amp_reg_shift = 8; // 1e_19[13:8]
510 + tx_amp_reg = 0x19;
511 + tx_amp_reg_100 = 0x20;
512 + } else { //if(calibration_pair == ANACAL_PAIR_D)
513 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00dd, 0x0001); // 1e_dd[0]
514 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x0180, (0x8000|DAC_IN_2V)); // 1e_180
515 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x0184, (0x8000|DAC_IN_2V)); // 1e_184
516 + reg_temp = (tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x021) & (~0x3f00));
517 + tx_amp_reg_shift = 8; // 1e_21[13:8]
518 + tx_amp_reg = 0x21;
519 + tx_amp_reg_100 = 0x22;
520 + }
521 + tc_phy_write_dev_reg( gsw, phyaddr, 0x1e, tx_amp_reg, (tx_amp_temp|(tx_amp_temp<<tx_amp_reg_shift))); // 1e_12, 1e_17, 1e_19, 1e_21
522 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg_100, (tx_amp_temp|(tx_amp_temp<<tx_amp_reg_shift)));
523 + all_ana_cal_status = all_ge_ana_cal_wait(gsw, delay, phyaddr); // delay 20 usec
524 + if(all_ana_cal_status == 0) {
525 + all_ana_cal_status = ANACAL_ERROR;
526 + printk( " GE Tx amp AnaCal ERROR init init! \r\n");
527 + return -1;
528 + }
529 +
530 + ad_cal_comp_out_init = (tc_phy_read_dev_reg(gsw, PHY0, 0x1e, 0x017a)>>8) & 0x1; // 1e_17a[8]
531 + if(ad_cal_comp_out_init == 1)
532 + calibration_polarity = -1;
533 + else
534 + calibration_polarity = 1;
535 +
536 + cnt =0;
537 + while(all_ana_cal_status < ANACAL_ERROR) {
538 + cnt ++;
539 + tx_amp_temp += calibration_polarity;
540 + //printk("tx_amp : %x, 1e %x = %x\n", tx_amp_temp, tx_amp_reg, (reg_temp|(tx_amp_temp<<tx_amp_reg_shift)));
541 + tc_phy_write_dev_reg( gsw, phyaddr, 0x1e, tx_amp_reg, (tx_amp_temp|(tx_amp_temp<<tx_amp_reg_shift)));
542 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg_100, (tx_amp_temp|(tx_amp_temp<<tx_amp_reg_shift)));
543 + all_ana_cal_status = all_ge_ana_cal_wait(gsw, delay, phyaddr); // delay 20 usec
544 + if(all_ana_cal_status == 0) {
545 + all_ana_cal_status = ANACAL_ERROR;
546 + printk( " GE Tx amp AnaCal ERROR 2! \r\n");
547 + return -1;
548 + } else if(((tc_phy_read_dev_reg(gsw, PHY0, 0x1e, 0x017a)>>8)&0x1) != ad_cal_comp_out_init) {
549 + //printk("TX AMP ANACAL_FINISH\n");
550 + all_ana_cal_status = ANACAL_FINISH;
551 + if (phyaddr == 0) {
552 + if (calibration_pair == ANACAL_PAIR_A)
553 + tx_amp_temp = tx_amp_temp - 2;
554 + else if(calibration_pair == ANACAL_PAIR_B)
555 + tx_amp_temp = tx_amp_temp - 1;
556 + else if(calibration_pair == ANACAL_PAIR_C)
557 + tx_amp_temp = tx_amp_temp - 2;
558 + else if(calibration_pair == ANACAL_PAIR_D)
559 + tx_amp_temp = tx_amp_temp - 1;
560 + } else if (phyaddr == 1) {
561 + if (calibration_pair == ANACAL_PAIR_A)
562 + tx_amp_temp = tx_amp_temp - 1;
563 + else if(calibration_pair == ANACAL_PAIR_B)
564 + tx_amp_temp = tx_amp_temp ;
565 + else if(calibration_pair == ANACAL_PAIR_C)
566 + tx_amp_temp = tx_amp_temp - 1;
567 + else if(calibration_pair == ANACAL_PAIR_D)
568 + tx_amp_temp = tx_amp_temp - 1;
569 + } else if (phyaddr == 2) {
570 + if (calibration_pair == ANACAL_PAIR_A)
571 + tx_amp_temp = tx_amp_temp;
572 + else if(calibration_pair == ANACAL_PAIR_B)
573 + tx_amp_temp = tx_amp_temp - 1;
574 + else if(calibration_pair == ANACAL_PAIR_C)
575 + tx_amp_temp = tx_amp_temp;
576 + else if(calibration_pair == ANACAL_PAIR_D)
577 + tx_amp_temp = tx_amp_temp - 1;
578 + } else if (phyaddr == 3) {
579 + tx_amp_temp = tx_amp_temp;
580 + } else if (phyaddr == 4) {
581 + if (calibration_pair == ANACAL_PAIR_A)
582 + tx_amp_temp = tx_amp_temp;
583 + else if(calibration_pair == ANACAL_PAIR_B)
584 + tx_amp_temp = tx_amp_temp - 1;
585 + else if(calibration_pair == ANACAL_PAIR_C)
586 + tx_amp_temp = tx_amp_temp;
587 + else if(calibration_pair == ANACAL_PAIR_D)
588 + tx_amp_temp = tx_amp_temp;
589 + }
590 + reg_temp = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg)&(~0xff00);
591 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg_100,(tx_amp_temp|((tx_amp_temp)<<tx_amp_reg_shift)));
592 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg, (tx_amp_temp|((tx_amp_temp)<<tx_amp_reg_shift)));
593 + if (phyaddr == 0) {
594 + if ((tx_amp_reg == 0x12) || (tx_amp_reg == 0x17)) {
595 + //printk("before : PORT[%d] 1e_%x = %x\n", phyaddr, tx_amp_reg, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg));
596 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg, ((tx_amp_temp|((tx_amp_temp)<<tx_amp_reg_shift)) + 7));
597 + //printk("after : PORT[%d] 1e_%x = %x\n", phyaddr, tx_amp_reg, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg));
598 + }
599 + if (tx_amp_reg_100 == 0x16) {
600 + //printk("before : PORT[%d] 1e_%x = %x\n", phyaddr, tx_amp_reg_100, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg_100));
601 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg_100,(tx_amp_temp|((tx_amp_temp+1+4)<<tx_amp_reg_shift)));
602 + //printk("after : PORT[%d] 1e_%x = %x\n", phyaddr, tx_amp_reg_100, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg_100));
603 + }
604 + if (tx_amp_reg_100 == 0x18) {
605 + //printk("before : PORT[%d] 1e_%x = %x\n", phyaddr, tx_amp_reg_100, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg_100));
606 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg_100,(tx_amp_temp|((tx_amp_temp+4)<<tx_amp_reg_shift)));
607 + //printk("after : PORT[%d] 1e_%x = %x\n", phyaddr, tx_amp_reg_100, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg_100));
608 + }
609 + } else if (phyaddr == 1) {
610 + if (tx_amp_reg == 0x12) {
611 + //printk("before : PORT[%d] 1e_%x = %x\n", phyaddr, tx_amp_reg, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg));
612 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg, ((tx_amp_temp|((tx_amp_temp)<<tx_amp_reg_shift)) + 9));
613 + //printk("after : PORT[%d] 1e_%x = %x\n", phyaddr, tx_amp_reg, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg));
614 + }
615 + if (tx_amp_reg == 0x17){
616 + //printk("before : PORT[%d] 1e_%x = %x\n", phyaddr, tx_amp_reg, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg));
617 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg, ((tx_amp_temp|((tx_amp_temp)<<tx_amp_reg_shift)) + 7));
618 + //printk("after : PORT[%d] 1e_%x = %x\n", phyaddr, tx_amp_reg, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg));
619 + }
620 + if (tx_amp_reg_100 == 0x16) {
621 + //printk("before : PORT[%d] 1e_%x = %x\n", phyaddr, tx_amp_reg_100, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg_100));
622 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg_100,(tx_amp_temp|((tx_amp_temp+4)<<tx_amp_reg_shift)));
623 + //printk("after : PORT[%d] 1e_%x = %x\n", phyaddr, tx_amp_reg_100, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg_100));
624 + }
625 + if (tx_amp_reg_100 == 0x18) {
626 + //printk("before : PORT[%d] 1e_%x = %x\n", phyaddr, tx_amp_reg_100, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg_100));
627 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg_100,(tx_amp_temp|((tx_amp_temp-1+4)<<tx_amp_reg_shift)));
628 + //printk("after : PORT[%d] 1e_%x = %x\n", phyaddr, tx_amp_reg_100, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg_100));
629 + }
630 + } else if (phyaddr == 2) {
631 + if ((tx_amp_reg == 0x12) || (tx_amp_reg == 0x17)) {
632 + //printk("before : PORT[%d] 1e_%x = %x\n", phyaddr, tx_amp_reg, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg));
633 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg, ((tx_amp_temp|((tx_amp_temp)<<tx_amp_reg_shift)) + 6));
634 + //printk("after : PORT[%d] 1e_%x = %x\n", phyaddr, tx_amp_reg, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg));
635 + }
636 + if ((tx_amp_reg_100 == 0x16) || (tx_amp_reg_100 == 0x18)) {
637 + //printk("before : PORT[%d] 1e_%x = %x\n", phyaddr, tx_amp_reg_100, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg_100));
638 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg_100,(tx_amp_temp|((tx_amp_temp-1+4)<<tx_amp_reg_shift)));
639 + //printk("after : PORT[%d] 1e_%x = %x\n", phyaddr, tx_amp_reg_100, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg_100));
640 + }
641 + } else if (phyaddr == 3) {
642 + if (tx_amp_reg == 0x12) {
643 + //printk("before : PORT[%d] 1e_%x = %x\n", phyaddr, tx_amp_reg, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg));
644 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg, ((tx_amp_temp|((tx_amp_temp)<<tx_amp_reg_shift)) + 4));
645 + //printk("after : PORT[%d] 1e_%x = %x\n", phyaddr, tx_amp_reg, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg));
646 + }
647 + if (tx_amp_reg == 0x17) {
648 + //printk("before : PORT[%d] 1e_%x = %x\n", phyaddr, tx_amp_reg, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg));
649 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg, ((tx_amp_temp|((tx_amp_temp)<<tx_amp_reg_shift)) + 7));
650 + //printk("after : PORT[%d] 1e_%x = %x\n", phyaddr, tx_amp_reg, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg));
651 + }
652 + if (tx_amp_reg_100 == 0x16) {
653 + //printk("before : PORT[%d] 1e_%x = %x\n", phyaddr, tx_amp_reg_100, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg_100));
654 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg_100,(tx_amp_temp|((tx_amp_temp-2+4)<<tx_amp_reg_shift)));
655 + //printk("after : PORT[%d] 1e_%x = %x\n", phyaddr, tx_amp_reg_100, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg_100));
656 + }
657 + if (tx_amp_reg_100 == 0x18) {
658 + //printk("before : PORT[%d] 1e_%x = %x\n", phyaddr, tx_amp_reg_100, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg_100));
659 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg_100,(tx_amp_temp|((tx_amp_temp-1+3)<<tx_amp_reg_shift)));
660 + //printk("after : PORT[%d] 1e_%x = %x\n", phyaddr, tx_amp_reg_100, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg_100));
661 + }
662 + } else if (phyaddr == 4) {
663 + if ((tx_amp_reg == 0x12) || (tx_amp_reg == 0x17)) {
664 + //printk("before : PORT[%d] 1e_%x = %x\n", phyaddr, tx_amp_reg, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg));
665 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg, ((tx_amp_temp|((tx_amp_temp)<<tx_amp_reg_shift)) + 5));
666 + //printk("after : PORT[%d] 1e_%x = %x\n", phyaddr, tx_amp_reg, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg));
667 + }
668 + if (tx_amp_reg_100 == 0x16) {
669 + //printk("before : PORT[%d] 1e_%x = %x\n", phyaddr, tx_amp_reg_100, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg_100));
670 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg_100,(tx_amp_temp|((tx_amp_temp-2+4)<<tx_amp_reg_shift)));
671 + //printk("after : PORT[%d] 1e_%x = %x\n", phyaddr, tx_amp_reg_100, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg_100));
672 + }
673 + if (tx_amp_reg_100 == 0x18) {
674 + //printk("before : PORT[%d] 1e_%x = %x\n", phyaddr, tx_amp_reg_100, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg_100));
675 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg_100,(tx_amp_temp|((tx_amp_temp-1+4)<<tx_amp_reg_shift)));
676 + //printk("after : PORT[%d] 1e_%x = %x\n", phyaddr, tx_amp_reg_100, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg_100));
677 + }
678 + }
679 +
680 + if (calibration_pair == ANACAL_PAIR_A){
681 + reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x12);
682 + reg_tmp = ((reg_backup & 0xfc00) >> 10);
683 + reg_tmp -= 8;
684 + reg_backup = 0x0000;
685 + reg_backup |= ((reg_tmp << 10) | (reg_tmp << 0));
686 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x12, reg_backup);
687 + reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x12);
688 + reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x16);
689 + reg_tmp = ((reg_backup & 0x3f) >> 0);
690 + reg_tmp -= 8;
691 + reg_backup = (reg_backup & (~0x3f));
692 + reg_backup |= (reg_tmp << 0);
693 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x16, reg_backup);
694 + reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x16);
695 + }
696 + else if(calibration_pair == ANACAL_PAIR_B){
697 + reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x17);
698 + reg_tmp = ((reg_backup & 0x3f00) >> 8);
699 + reg_tmp -= 8;
700 + reg_backup = 0x0000;
701 + reg_backup |= ((reg_tmp << 8) | (reg_tmp << 0));
702 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x17, reg_backup);
703 + reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x17);
704 + reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x18);
705 + reg_tmp = ((reg_backup & 0x3f) >> 0);
706 + reg_tmp -= 8;
707 + reg_backup = (reg_backup & (~0x3f));
708 + reg_backup |= (reg_tmp << 0);
709 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x18, reg_backup);
710 + reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x18);
711 + }
712 + else if(calibration_pair == ANACAL_PAIR_C){
713 + reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x19);
714 + reg_tmp = ((reg_backup & 0x3f00) >> 8);
715 + reg_tmp -= 8;
716 + reg_backup = (reg_backup & (~0x3f00));
717 + reg_backup |= (reg_tmp << 8);
718 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x19, reg_backup);
719 + reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x19);
720 + reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x20);
721 + reg_tmp = ((reg_backup & 0x3f) >> 0);
722 + reg_tmp -= 8;
723 + reg_backup = (reg_backup & (~0x3f));
724 + reg_backup |= (reg_tmp << 0);
725 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x20, reg_backup);
726 + reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x20);
727 + }
728 + else if(calibration_pair == ANACAL_PAIR_D){
729 + reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x21);
730 + reg_tmp = ((reg_backup & 0x3f00) >> 8);
731 + reg_tmp -= 8;
732 + reg_backup = (reg_backup & (~0x3f00));
733 + reg_backup |= (reg_tmp << 8);
734 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x21, reg_backup);
735 + reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x21);
736 + reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x22);
737 + reg_tmp = ((reg_backup & 0x3f) >> 0);
738 + reg_tmp -= 8;
739 + reg_backup = (reg_backup & (~0x3f));
740 + reg_backup |= (reg_tmp << 0);
741 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x22, reg_backup);
742 + reg_backup = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x22);
743 + }
744 + printk( " GE Tx amp AnaCal Done! (pair-%d)(1e_%x = 0x%x)\n", calibration_pair, tx_amp_reg, tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg));
745 +
746 + } else {
747 + if((tx_amp_temp == 0x3f)||(tx_amp_temp == 0x00)) {
748 + all_ana_cal_status = ANACAL_SATURATION;
749 + printk( " GE Tx amp AnaCal Saturation! \r\n");
750 + }
751 + }
752 + }
753 +
754 + if(all_ana_cal_status == ANACAL_ERROR) {
755 + tx_amp_temp = 0x20;
756 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, tx_amp_reg, (reg_temp|(tx_amp_temp<<tx_amp_reg_shift)));
757 + }
758 + }
759 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x017d, 0x0000);
760 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x017e, 0x0000);
761 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x017f, 0x0000);
762 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x0180, 0x0000);
763 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x0181, 0x0000);
764 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x0182, 0x0000);
765 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x0183, 0x0000);
766 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x0184, 0x0000);
767 +
768 + /* disable analog calibration circuit */
769 + tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x00db, 0x0000);
770 + tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x00dc, 0x0000);
771 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00db, 0x0000);
772 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00dc, 0x0000);
773 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x003e, 0x0000);
774 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x00dd, 0x0000);
775 +
776 +
777 +
778 + //tc_phy_write_dev_reg(gsw, phyaddr, 0x1f, 0x273, 0x2000);
779 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0xc9, 0x0fff);
780 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x145, 0x1000);
781 +
782 +}
783 +
784 +//-----------------------------------------------------------------
785 +
786 +int phy_calibration(struct gsw_mt753x *gsw, u8 phyaddr)
787 +{
788 + u32 reg_tmp,reg_tmp0, reg_tmp1, i;
789 + u32 CALDLY = 40;
790 + int ret;
791 + switch_phy_write(gsw, phyaddr, R0, 0x140);
792 +
793 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x145, 0x1010);
794 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, RG_185, 0);
795 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1f, 0x100, 0xc000);
796 + //tc_phy_write_dev_reg(gsw, phyaddr, 0x1f, 0x403, 0x1099);
797 +
798 +#if (1)
799 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1f, 0x27c, 0x1f1f);
800 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1f, 0x27c, 0x3300);
801 +
802 + reg_tmp1 = tc_phy_read_dev_reg(gsw, PHY0, 0x1f, 0x27c);
803 + reg_tmp = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x11);
804 + reg_tmp = reg_tmp | (0xf << 12);
805 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x11, reg_tmp);
806 + tc_phy_write_dev_reg(gsw, PHY0, 0x1e, 0x00e1, 0x10);
807 + /* calibration start ============ */
808 + printk("CALDLY = %d\n", CALDLY);
809 + if(ge_cal_flag == 0){
810 + ret = ge_cal_rext(gsw, 0, CALDLY);
811 + if (ret == -1){
812 + printk("ge_cal_rext error K port =%d\n", phyaddr);
813 + return ret;
814 + }
815 + ge_cal_flag = 1;
816 + }
817 +
818 + /* *** R50 Cal start ***************************** */
819 + /*phyaddress = 0*/
820 + ret = ge_cal_r50(gsw, phyaddr, CALDLY);
821 + if (ret == -1){
822 + printk("R50 error K port =%d\n", phyaddr);
823 + return ret;
824 + }
825 + /* *** R50 Cal end *** */
826 + /* *** Tx offset Cal start *********************** */
827 + ret = ge_cal_tx_offset(gsw, phyaddr, CALDLY);
828 + if (ret == -1){
829 + printk("ge_cal_tx_offset error K port =%d\n", phyaddr);
830 + return ret;
831 + }
832 + /* *** Tx offset Cal end *** */
833 +
834 + /* *** Tx Amp Cal start *** */
835 + ret = ge_cal_tx_amp(gsw, phyaddr, CALDLY);
836 + if (ret == -1){
837 + printk("ge_cal_tx_amp error K port =%d\n", phyaddr);
838 + return ret;
839 + }
840 + /* *** Tx Amp Cal end *** */
841 + /*tmp maybe changed*/
842 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1f, 0x27c, 0x1111);
843 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1f, 0x27b, 0x47);
844 + //tc_phy_write_dev_reg(gsw, phyaddr, 0x1f, 0x273, 0x2000);
845 +
846 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x3a8, 0x0810);
847 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x3aa, 0x0008);
848 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x3ab, 0x0810);
849 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x3ad, 0x0008);
850 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x3ae, 0x0106);
851 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x3b0, 0x0001);
852 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x3b1, 0x0106);
853 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x3b3, 0x0001);
854 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x18c, 0x0001);
855 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x18d, 0x0001);
856 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x18e, 0x0001);
857 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x18f, 0x0001);
858 +
859 + reg_tmp = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x3aa);
860 + reg_tmp = reg_tmp & ~(0x1f00);
861 + reg_tmp = reg_tmp | 0x2 << 8;
862 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x3aa, reg_tmp);
863 +
864 + reg_tmp = tc_phy_read_dev_reg(gsw, phyaddr, 0x1e, 0x3a9);
865 + reg_tmp = reg_tmp & ~(0x1f);
866 + reg_tmp = reg_tmp | 0x2;
867 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x3a9, reg_tmp);
868 +#endif
869 +}
870 +
871 +void rx_dc_offset(struct gsw_mt753x *gsw, u8 phyaddr)
872 +{
873 + u32 reg_tmp1;
874 +
875 + //pr_info("PORT %d RX_DC_OFFSET\n", phyaddr);
876 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x96, 0x8000);
877 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x37, 0x3);
878 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x107, 0x4000);
879 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x171, 0x1e5);
880 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x39, 0x200f);
881 + udelay(40);
882 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x39, 0x000f);
883 + udelay(40);
884 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x171, 0x65);
885 +}
886 +
887 +void check_rx_dc_offset_pair_a(struct gsw_mt753x *gsw, u8 phyaddr)
888 +{
889 + u32 reg_tmp;
890 + u8 reg_val;
891 +
892 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1f, 0x15, (phyaddr << 13) | 0x114f);
893 + reg_tmp = tc_phy_read_dev_reg(gsw, phyaddr, 0x1f, 0x1a);
894 + reg_tmp = reg_tmp & 0xff;
895 + udelay(40);
896 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1f, 0x15, (phyaddr << 13) | 0x1142);
897 + udelay(40);
898 + reg_tmp = tc_phy_read_dev_reg(gsw, phyaddr, 0x1f, 0x1a);
899 + reg_tmp = reg_tmp & 0xff;
900 + if ((reg_tmp & 0x80) != 0)
901 + reg_tmp = (~reg_tmp) + 1;
902 + if ((reg_tmp & 0xff) >4)
903 + pr_info("pairA RX_DC_OFFSET error");
904 +}
905 +
906 +void check_rx_dc_offset_pair_b(struct gsw_mt753x *gsw, u8 phyaddr)
907 +{
908 + u32 reg_tmp;
909 + u8 reg_val;
910 +
911 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1f, 0x15, (phyaddr << 13) | 0x1151);
912 + reg_tmp = tc_phy_read_dev_reg(gsw, phyaddr, 0x1f, 0x1a);
913 + reg_tmp = reg_tmp & 0xff;
914 + udelay(40);
915 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1f, 0x15, (phyaddr << 13) | 0x1143);
916 + udelay(40);
917 + reg_tmp = tc_phy_read_dev_reg(gsw, phyaddr, 0x1f, 0x1a);
918 + reg_tmp = reg_tmp & 0xff;
919 + if ((reg_tmp & 0x80) != 0)
920 + reg_tmp = (~reg_tmp) + 1;
921 + if ((reg_tmp & 0xff) >4)
922 + pr_info("pairB RX_DC_OFFSET error");
923 +}
924 +
925 +void check_rx_dc_offset_pair_c(struct gsw_mt753x *gsw, u8 phyaddr)
926 +{
927 + u32 reg_tmp;
928 + u8 reg_val;
929 +
930 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1f, 0x15, (phyaddr << 13) | 0x1153);
931 + reg_tmp = tc_phy_read_dev_reg(gsw, phyaddr, 0x1f, 0x1a);
932 + reg_tmp = reg_tmp & 0xff;
933 + udelay(40);
934 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1f, 0x15, (phyaddr << 13) | 0x1144);
935 + udelay(40);
936 + reg_tmp = tc_phy_read_dev_reg(gsw, phyaddr, 0x1f, 0x1a);
937 + reg_tmp = reg_tmp & 0xff;
938 + if ((reg_tmp & 0x80) != 0)
939 + reg_tmp = (~reg_tmp) + 1;
940 + if ((reg_tmp & 0xff) >4)
941 + pr_info("pairC RX_DC_OFFSET error");
942 +}
943 +
944 +void check_rx_dc_offset_pair_d(struct gsw_mt753x *gsw, u8 phyaddr)
945 +{
946 + u32 reg_tmp;
947 + u8 reg_val;
948 +
949 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1f, 0x15, (phyaddr << 13) | 0x1155);
950 + reg_tmp = tc_phy_read_dev_reg(gsw, phyaddr, 0x1f, 0x1a);
951 + reg_tmp = reg_tmp & 0xff;
952 + udelay(40);
953 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1f, 0x15, (phyaddr << 13) | 0x1145);
954 + udelay(40);
955 + reg_tmp = tc_phy_read_dev_reg(gsw, phyaddr, 0x1f, 0x1a);
956 + reg_tmp = reg_tmp & 0xff;
957 + if ((reg_tmp & 0x80) != 0)
958 + reg_tmp = (~reg_tmp) + 1;
959 + if ((reg_tmp & 0xff) >4)
960 + pr_info("pairD RX_DC_OFFSET error");
961 +}
962 +
963 +
964 +int mt753x_phy_calibration(struct gsw_mt753x *gsw, u8 phyaddr){
965 +
966 + int ret;
967 +
968 + phy_calibration(gsw, phyaddr);
969 +
970 + /*eye pic*/
971 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x0, 0x187);
972 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x1, 0x1c9);
973 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x2, 0x1c6);
974 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x3, 0x182);
975 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x4, 0x208);
976 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x5, 0x205);
977 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x6, 0x384);
978 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x7, 0x3cb);
979 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x8, 0x3c4);
980 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0x9, 0x30a);
981 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0xa, 0x00b);
982 + tc_phy_write_dev_reg(gsw, phyaddr, 0x1e, 0xb, 0x002);
983 +
984 + rx_dc_offset(gsw, phyaddr);
985 + check_rx_dc_offset_pair_a(gsw, phyaddr);
986 + check_rx_dc_offset_pair_b(gsw, phyaddr);
987 + check_rx_dc_offset_pair_c(gsw, phyaddr);
988 + check_rx_dc_offset_pair_d(gsw, phyaddr);
989 +
990 + return ret;
991 +}
992 --- /dev/null
993 +++ b/drivers/net/phy/mtk/mt753x/mt753x_phy.h
994 @@ -0,0 +1,145 @@
995 +/* SPDX-License-Identifier: GPL-2.0+ */
996 +/*
997 + * Register definitions for MediaTek MT753x Gigabit switches
998 + *
999 + * Copyright (C) 2018 MediaTek Inc. All Rights Reserved.
1000 + *
1001 + * Author: Weijie Gao <weijie.gao@mediatek.com>
1002 + */
1003 +
1004 +#ifndef _MT753X_PHY_H_
1005 +#define _MT753X_PHY_H_
1006 +
1007 +#include <linux/bitops.h>
1008 +
1009 +/*phy calibration use*/
1010 +#define DEV_1E 0x1E
1011 +/*global device 0x1f, always set P0*/
1012 +#define DEV_1F 0x1F
1013 +
1014 +
1015 +/************IEXT/REXT CAL***************/
1016 +/* bits range: for example BITS(16,23) = 0xFF0000*/
1017 +#define BITS(m, n) (~(BIT(m) - 1) & ((BIT(n) - 1) | BIT(n)))
1018 +#define ANACAL_INIT 0x01
1019 +#define ANACAL_ERROR 0xFD
1020 +#define ANACAL_SATURATION 0xFE
1021 +#define ANACAL_FINISH 0xFF
1022 +#define ANACAL_PAIR_A 0
1023 +#define ANACAL_PAIR_B 1
1024 +#define ANACAL_PAIR_C 2
1025 +#define ANACAL_PAIR_D 3
1026 +#define DAC_IN_0V 0x00
1027 +#define DAC_IN_2V 0xf0
1028 +#define TX_AMP_OFFSET_0MV 0x20
1029 +#define TX_AMP_OFFSET_VALID_BITS 6
1030 +
1031 +#define R0 0
1032 +#define PHY0 0
1033 +#define PHY1 1
1034 +#define PHY2 2
1035 +#define PHY3 3
1036 +#define PHY4 4
1037 +#define ANA_TEST_MODE BITS(8, 15)
1038 +#define TST_TCLK_SEL BITs(6, 7)
1039 +#define ANA_TEST_VGA_RG 0x100
1040 +
1041 +#define FORCE_MDI_CROSS_OVER BITS(3, 4)
1042 +#define T10_TEST_CTL_RG 0x145
1043 +#define RG_185 0x185
1044 +#define RG_TX_SLEW BIT(0)
1045 +#define ANA_CAL_0 0xdb
1046 +#define RG_CAL_CKINV BIT(12)
1047 +#define RG_ANA_CALEN BIT(8)
1048 +#define RG_REXT_CALEN BIT(4)
1049 +#define RG_ZCALEN_A BIT(0)
1050 +#define ANA_CAL_1 0xdc
1051 +#define RG_ZCALEN_B BIT(12)
1052 +#define RG_ZCALEN_C BIT(8)
1053 +#define RG_ZCALEN_D BIT(4)
1054 +#define RG_TXVOS_CALEN BIT(0)
1055 +#define ANA_CAL_6 0xe1
1056 +#define RG_CAL_REFSEL BIT(4)
1057 +#define RG_CAL_COMP_PWD BIT(0)
1058 +#define ANA_CAL_5 0xe0
1059 +#define RG_REXT_TRIM BITs(8, 13)
1060 +#define RG_ZCAL_CTRL BITs(0, 5)
1061 +#define RG_17A 0x17a
1062 +#define AD_CAL_COMP_OUT BIT(8)
1063 +#define RG_17B 0x17b
1064 +#define AD_CAL_CLK bit(0)
1065 +#define RG_17C 0x17c
1066 +#define DA_CALIN_FLAG bit(0)
1067 +/************R50 CAL****************************/
1068 +#define RG_174 0x174
1069 +#define RG_R50OHM_RSEL_TX_A_EN BIT[15]
1070 +#define CR_R50OHM_RSEL_TX_A BITS[8:14]
1071 +#define RG_R50OHM_RSEL_TX_B_EN BIT[7]
1072 +#define CR_R50OHM_RSEL_TX_B BITS[6:0]
1073 +#define RG_175 0x175
1074 +#define RG_R50OHM_RSEL_TX_C_EN BITS[15]
1075 +#define CR_R50OHM_RSEL_TX_C BITS[8:14]
1076 +#define RG_R50OHM_RSEL_TX_D_EN BIT[7]
1077 +#define CR_R50OHM_RSEL_TX_D BITS[0:6]
1078 +/**********TX offset Calibration***************************/
1079 +#define RG_95 0x96
1080 +#define BYPASS_TX_OFFSET_CAL BIT(15)
1081 +#define RG_3E 0x3e
1082 +#define BYPASS_PD_TXVLD_A BIT(15)
1083 +#define BYPASS_PD_TXVLD_B BIT(14)
1084 +#define BYPASS_PD_TXVLD_C BIT(13)
1085 +#define BYPASS_PD_TXVLD_D BIT(12)
1086 +#define BYPASS_PD_TX_10M BIT(11)
1087 +#define POWER_DOWN_TXVLD_A BIT(7)
1088 +#define POWER_DOWN_TXVLD_B BIT(6)
1089 +#define POWER_DOWN_TXVLD_C BIT(5)
1090 +#define POWER_DOWN_TXVLD_D BIT(4)
1091 +#define POWER_DOWN_TX_10M BIT(3)
1092 +#define RG_DD 0xdd
1093 +#define RG_TXG_CALEN_A BIT(12)
1094 +#define RG_TXG_CALEN_B BIT(8)
1095 +#define RG_TXG_CALEN_C BIT(4)
1096 +#define RG_TXG_CALEN_D BIT(0)
1097 +#define RG_17D 0x17D
1098 +#define FORCE_DASN_DAC_IN0_A BIT(15)
1099 +#define DASN_DAC_IN0_A BITS(0, 9)
1100 +#define RG_17E 0x17E
1101 +#define FORCE_DASN_DAC_IN0_B BIT(15)
1102 +#define DASN_DAC_IN0_B BITS(0, 9)
1103 +#define RG_17F 0x17F
1104 +
1105 +#define FORCE_DASN_DAC_IN0_C BIT(15)
1106 +#define DASN_DAC_IN0_C BITS(0, 9)
1107 +#define RG_180 0x180
1108 +#define FORCE_DASN_DAC_IN0_D BIT(15)
1109 +#define DASN_DAC_IN0_D BITS(0, 9)
1110 +
1111 +#define RG_181 0x181
1112 +#define FORCE_DASN_DAC_IN1_A BIT(15)
1113 +#define DASN_DAC_IN1_A BITS(0, 9)
1114 +#define RG_182 0x182
1115 +#define FORCE_DASN_DAC_IN1_B BIT(15)
1116 +#define DASN_DAC_IN1_B BITS(0, 9)
1117 +#define RG_183 0x183
1118 +#define FORCE_DASN_DAC_IN1_C BIT15]
1119 +#define DASN_DAC_IN1_C BITS(0, 9)
1120 +#define RG_184 0x184
1121 +#define FORCE_DASN_DAC_IN1_D BIT(15)
1122 +#define DASN_DAC_IN1_D BITS(0, 9)
1123 +#define RG_172 0x172
1124 +#define CR_TX_AMP_OFFSET_A BITS(8, 13)
1125 +#define CR_TX_AMP_OFFSET_B BITS(0, 5)
1126 +#define RG_173 0x173
1127 +#define CR_TX_AMP_OFFSET_C BITS(8, 13)
1128 +#define CR_TX_AMP_OFFSET_D BITS(0, 5)
1129 +/**********TX Amp Calibration ***************************/
1130 +#define RG_12 0x12
1131 +#define DA_TX_I2MPB_A_GBE BITS(10, 15)
1132 +#define RG_17 0x17
1133 +#define DA_TX_I2MPB_B_GBE BITS(8, 13)
1134 +#define RG_19 0x19
1135 +#define DA_TX_I2MPB_C_GBE BITS(8, 13)
1136 +#define RG_21 0x21
1137 +#define DA_TX_I2MPB_D_GBE BITS(8, 13)
1138 +
1139 +#endif /* _MT753X_REGS_H_ */
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