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octeon: disable edgerouter image
[openwrt/staging/dedeckeh.git] / target / linux / mediatek / patches-4.19 / 0005-pinctrl-mediatek-sync-with-5.3.patch
1 This patch squashes the following upstream commits:
2
3 5ca1b1c5cd98 pinctrl: mediatek: mt8183: Add pm_ops
4 5c0904488a20 pinctrl: mediatek: Add pm_ops to pinctrl-paris
5 1802d0beecaf treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 174
6 ec8f24b7faaf treewide: Add SPDX license identifier - Makefile/Kconfig
7 264667112ef0 pinctrl: mediatek: Add MT8516 Pinctrl driver
8 5e73de3413c5 pinctrl: add drive for I2C related pins on MT8183
9 e65372124cd7 Merge tag 'v5.0-rc6' into devel
10 2d2d478576d7 pinctrl: mediatek: fix Kconfig build errors for moore core
11 6e737a4e921e pinctrl: mediatek: add EINT support to virtual GPIOs
12 b5af33df50e9 pinctrl: mediatek: improve Kconfig dependencies
13 9ede2a76f66e pinctrl: mediatek: Convert to using %pOFn instead of device_node.name
14 b44677375fee pinctrl: mediatek: add pinctrl support for MT7629 SoC
15 f969b7aac980 pinctrl: mediatek: Add initial pinctrl driver for MT6797 SoC
16 7c68024a82a2 pinctrl: mediatek: Fix dependencies for EINT_MTK
17 78bf386daf8a pinctrl: mediatek: clean up indentation issues, add missing tab
18 28e0603c4df4 pinctrl: mediatek: Make eint_m u16
19 71a9d395aa12 pinctrl: mediatek: select GPIOLIB
20 ad335bee6ced pinctrl: mediatek: mark dummy helpers as 'static inline'
21 7a52127e3cf1 pinctrl: mediatek: fix check on EINT_NA comparison
22 bb8d8466ca25 pinctrl: mediatek: add eint support to MT6765 pinctrl driver
23 477fecee7ca9 pinctrl: mediatek: add MT6765 pinctrl driver
24 ecfcfb498860 pinctrl: mediatek: add no eint function for pin define
25 7f2e29e133ea pinctrl: mediatek: fix static checker warning caused by EINT_NA
26 068cfb9a0fd9 pinctrl: mediatek: moore: fix return value check in mtk_moore_pinctrl_probe()
27 07c6b037c2ba pinctrl: mediatek: make symbol 'mtk_drive' static
28 184744e9a014 pinctrl: mediatek: paris: fix return value check in mtk_paris_pinctrl_probe()
29 22d7fe4984a2 pinctrl: mtk: Fix up GPIO includes
30 55818b90233b Merge branch 'ib-mtk' into devel
31 6561859b067f pinctrl: mediatek: add eint support to MT8183 pinctrl driver
32 89132dd8ffd2 pinctrl: mediatek: extend eint build to pinctrl-mtk-common-v2.c
33 29686f0151df pintcrl: mediatek: add pull tweaks for I2C related pins on MT8183
34 79348f6fb713 pinctrl: mediatek: extend advanced pull support in pinctrl-mtk-common-v2.c
35 750cd15d9081 pinctrl: mediatek: add MT8183 pinctrl driver
36 805250982bb5 pinctrl: mediatek: add pinctrl-paris that implements the vendor dt-bindings
37 b7d7f9eeca55 pinctrl: mediatek: extend struct mtk_pin_desc which per-pin driver depends on
38 9d9b171c6897 pinctrl: mediatek: adjust error code and message when some register not supported is found
39 2bc47dfe4f8b pinctrl: mediatek: add multiple register bases support to pinctrl-mtk-common-v2.c
40 ea051eb38413 pinctrl: mediatek: use pin descriptor all in pinctrl-mtk-common-v2.c
41 e7507f57a93a pinctrl: mediatek: add MT7623 pinctrl driver based on generic pinctrl binding
42 9afc305bfad7 pinctrl: mediatek: add pullen, pullsel register support to pinctrl-mtk-common-v2.c
43 182c842fd5e6 pinctrl: mediatek: add ies register support to pinctrl-mtk-common-v2.c
44 0d7ca772148f pinctrl: mediatek: add advanced pull related support to pinctrl-mtk-common-v2.c
45 85430152ba46 pinctrl: mediatek: add pull related support to pinctrl-mtk-common-v2.c
46 3ad38a14e13c pinctrl: mediatek: add drv register support to pinctrl-mtk-common-v2.c
47 c28321979ba8 pinctrl: mediatek: add driving strength related support to pinctrl-mtk-common-v2.c
48 1dc5e5369159 pinctrl: mediatek: extend struct mtk_pin_soc to pinctrl-mtk-common-v2.c
49 fb5fa8dc151b pinctrl: mediatek: extend struct mtk_pin_desc to pinctrl-mtk-common-v2.c
50 b906faf7b61d pinctrl: mediatek: extend struct mtk_pin_field_calc to pinctrl-mtk-common-v2.c
51 e78d57b2f87c pinctrl: mediatek: add pinctrl-moore that implements the generic pinctrl dt-bindings
52 a1a503a8c332 pinctrl: mediatek: add pinctrl-mtk-common-v2 for all MediaTek pinctrls
53 1c5fb66afa2a pinctrl: Include <linux/gpio/driver.h> nothing else
54 94f4e54cecaf pinctrl: Convert to using %pOFn instead of device_node.name
55
56 --- a/drivers/pinctrl/mediatek/Kconfig
57 +++ b/drivers/pinctrl/mediatek/Kconfig
58 @@ -3,7 +3,8 @@ menu "MediaTek pinctrl drivers"
59
60 config EINT_MTK
61 bool "MediaTek External Interrupt Support"
62 - depends on PINCTRL_MTK || PINCTRL_MT7622 || COMPILE_TEST
63 + depends on PINCTRL_MTK || PINCTRL_MTK_MOORE || PINCTRL_MTK_PARIS || COMPILE_TEST
64 + select GPIOLIB
65 select IRQ_DOMAIN
66
67 config PINCTRL_MTK
68 @@ -15,6 +16,24 @@ config PINCTRL_MTK
69 select EINT_MTK
70 select OF_GPIO
71
72 +config PINCTRL_MTK_MOORE
73 + bool
74 + depends on OF
75 + select GENERIC_PINCONF
76 + select GENERIC_PINCTRL_GROUPS
77 + select GENERIC_PINMUX_FUNCTIONS
78 + select GPIOLIB
79 + select OF_GPIO
80 +
81 +config PINCTRL_MTK_PARIS
82 + bool
83 + depends on OF
84 + select PINMUX
85 + select GENERIC_PINCONF
86 + select GPIOLIB
87 + select EINT_MTK
88 + select OF_GPIO
89 +
90 # For ARMv7 SoCs
91 config PINCTRL_MT2701
92 bool "Mediatek MT2701 pin control"
93 @@ -23,6 +42,20 @@ config PINCTRL_MT2701
94 default MACH_MT2701
95 select PINCTRL_MTK
96
97 +config PINCTRL_MT7623
98 + bool "Mediatek MT7623 pin control with generic binding"
99 + depends on MACH_MT7623 || COMPILE_TEST
100 + depends on OF
101 + default MACH_MT7623
102 + select PINCTRL_MTK_MOORE
103 +
104 +config PINCTRL_MT7629
105 + bool "Mediatek MT7629 pin control"
106 + depends on MACH_MT7629 || COMPILE_TEST
107 + depends on OF
108 + default MACH_MT7629
109 + select PINCTRL_MTK_MOORE
110 +
111 config PINCTRL_MT8135
112 bool "Mediatek MT8135 pin control"
113 depends on MACH_MT8135 || COMPILE_TEST
114 @@ -45,21 +78,46 @@ config PINCTRL_MT2712
115 default ARM64 && ARCH_MEDIATEK
116 select PINCTRL_MTK
117
118 +config PINCTRL_MT6765
119 + bool "Mediatek MT6765 pin control"
120 + depends on OF
121 + depends on ARM64 || COMPILE_TEST
122 + default ARM64 && ARCH_MEDIATEK
123 + select PINCTRL_MTK_PARIS
124 +
125 +config PINCTRL_MT6797
126 + bool "Mediatek MT6797 pin control"
127 + depends on OF
128 + depends on ARM64 || COMPILE_TEST
129 + default ARM64 && ARCH_MEDIATEK
130 + select PINCTRL_MTK_PARIS
131 +
132 config PINCTRL_MT7622
133 bool "MediaTek MT7622 pin control"
134 depends on OF
135 depends on ARM64 || COMPILE_TEST
136 - select GENERIC_PINCONF
137 - select GENERIC_PINCTRL_GROUPS
138 - select GENERIC_PINMUX_FUNCTIONS
139 - select GPIOLIB
140 - select OF_GPIO
141 + default ARM64 && ARCH_MEDIATEK
142 + select PINCTRL_MTK_MOORE
143
144 config PINCTRL_MT8173
145 bool "Mediatek MT8173 pin control"
146 depends on OF
147 depends on ARM64 || COMPILE_TEST
148 default ARM64 && ARCH_MEDIATEK
149 + select PINCTRL_MTK
150 +
151 +config PINCTRL_MT8183
152 + bool "Mediatek MT8183 pin control"
153 + depends on OF
154 + depends on ARM64 || COMPILE_TEST
155 + default ARM64 && ARCH_MEDIATEK
156 + select PINCTRL_MTK_PARIS
157 +
158 +config PINCTRL_MT8516
159 + bool "Mediatek MT8516 pin control"
160 + depends on OF
161 + depends on ARM64 || COMPILE_TEST
162 + default ARM64 && ARCH_MEDIATEK
163 select PINCTRL_MTK
164
165 # For PMIC
166 --- a/drivers/pinctrl/mediatek/Makefile
167 +++ b/drivers/pinctrl/mediatek/Makefile
168 @@ -2,12 +2,20 @@
169 # Core
170 obj-$(CONFIG_EINT_MTK) += mtk-eint.o
171 obj-$(CONFIG_PINCTRL_MTK) += pinctrl-mtk-common.o
172 +obj-$(CONFIG_PINCTRL_MTK_MOORE) += pinctrl-moore.o pinctrl-mtk-common-v2.o
173 +obj-$(CONFIG_PINCTRL_MTK_PARIS) += pinctrl-paris.o pinctrl-mtk-common-v2.o
174
175 # SoC Drivers
176 obj-$(CONFIG_PINCTRL_MT2701) += pinctrl-mt2701.o
177 obj-$(CONFIG_PINCTRL_MT2712) += pinctrl-mt2712.o
178 obj-$(CONFIG_PINCTRL_MT8135) += pinctrl-mt8135.o
179 obj-$(CONFIG_PINCTRL_MT8127) += pinctrl-mt8127.o
180 +obj-$(CONFIG_PINCTRL_MT6765) += pinctrl-mt6765.o
181 +obj-$(CONFIG_PINCTRL_MT6797) += pinctrl-mt6797.o
182 obj-$(CONFIG_PINCTRL_MT7622) += pinctrl-mt7622.o
183 +obj-$(CONFIG_PINCTRL_MT7623) += pinctrl-mt7623.o
184 +obj-$(CONFIG_PINCTRL_MT7629) += pinctrl-mt7629.o
185 obj-$(CONFIG_PINCTRL_MT8173) += pinctrl-mt8173.o
186 +obj-$(CONFIG_PINCTRL_MT8183) += pinctrl-mt8183.o
187 +obj-$(CONFIG_PINCTRL_MT8516) += pinctrl-mt8516.o
188 obj-$(CONFIG_PINCTRL_MT6397) += pinctrl-mt6397.o
189 --- a/drivers/pinctrl/mediatek/mtk-eint.c
190 +++ b/drivers/pinctrl/mediatek/mtk-eint.c
191 @@ -11,7 +11,7 @@
192
193 #include <linux/delay.h>
194 #include <linux/err.h>
195 -#include <linux/gpio.h>
196 +#include <linux/gpio/driver.h>
197 #include <linux/io.h>
198 #include <linux/irqchip/chained_irq.h>
199 #include <linux/irqdomain.h>
200 --- a/drivers/pinctrl/mediatek/mtk-eint.h
201 +++ b/drivers/pinctrl/mediatek/mtk-eint.h
202 @@ -92,13 +92,13 @@ static inline int mtk_eint_do_resume(str
203 return -EOPNOTSUPP;
204 }
205
206 -int mtk_eint_set_debounce(struct mtk_eint *eint, unsigned long eint_n,
207 +static inline int mtk_eint_set_debounce(struct mtk_eint *eint, unsigned long eint_n,
208 unsigned int debounce)
209 {
210 return -EOPNOTSUPP;
211 }
212
213 -int mtk_eint_find_irq(struct mtk_eint *eint, unsigned long eint_n)
214 +static inline int mtk_eint_find_irq(struct mtk_eint *eint, unsigned long eint_n)
215 {
216 return -EOPNOTSUPP;
217 }
218 --- /dev/null
219 +++ b/drivers/pinctrl/mediatek/pinctrl-moore.c
220 @@ -0,0 +1,690 @@
221 +// SPDX-License-Identifier: GPL-2.0
222 +/*
223 + * MediaTek Pinctrl Moore Driver, which implement the generic dt-binding
224 + * pinctrl-bindings.txt for MediaTek SoC.
225 + *
226 + * Copyright (C) 2017-2018 MediaTek Inc.
227 + * Author: Sean Wang <sean.wang@mediatek.com>
228 + *
229 + */
230 +
231 +#include <linux/gpio/driver.h>
232 +#include "pinctrl-moore.h"
233 +
234 +#define PINCTRL_PINCTRL_DEV KBUILD_MODNAME
235 +
236 +/* Custom pinconf parameters */
237 +#define MTK_PIN_CONFIG_TDSEL (PIN_CONFIG_END + 1)
238 +#define MTK_PIN_CONFIG_RDSEL (PIN_CONFIG_END + 2)
239 +#define MTK_PIN_CONFIG_PU_ADV (PIN_CONFIG_END + 3)
240 +#define MTK_PIN_CONFIG_PD_ADV (PIN_CONFIG_END + 4)
241 +
242 +static const struct pinconf_generic_params mtk_custom_bindings[] = {
243 + {"mediatek,tdsel", MTK_PIN_CONFIG_TDSEL, 0},
244 + {"mediatek,rdsel", MTK_PIN_CONFIG_RDSEL, 0},
245 + {"mediatek,pull-up-adv", MTK_PIN_CONFIG_PU_ADV, 1},
246 + {"mediatek,pull-down-adv", MTK_PIN_CONFIG_PD_ADV, 1},
247 +};
248 +
249 +#ifdef CONFIG_DEBUG_FS
250 +static const struct pin_config_item mtk_conf_items[] = {
251 + PCONFDUMP(MTK_PIN_CONFIG_TDSEL, "tdsel", NULL, true),
252 + PCONFDUMP(MTK_PIN_CONFIG_RDSEL, "rdsel", NULL, true),
253 + PCONFDUMP(MTK_PIN_CONFIG_PU_ADV, "pu-adv", NULL, true),
254 + PCONFDUMP(MTK_PIN_CONFIG_PD_ADV, "pd-adv", NULL, true),
255 +};
256 +#endif
257 +
258 +static int mtk_pinmux_set_mux(struct pinctrl_dev *pctldev,
259 + unsigned int selector, unsigned int group)
260 +{
261 + struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
262 + struct function_desc *func;
263 + struct group_desc *grp;
264 + int i;
265 +
266 + func = pinmux_generic_get_function(pctldev, selector);
267 + if (!func)
268 + return -EINVAL;
269 +
270 + grp = pinctrl_generic_get_group(pctldev, group);
271 + if (!grp)
272 + return -EINVAL;
273 +
274 + dev_dbg(pctldev->dev, "enable function %s group %s\n",
275 + func->name, grp->name);
276 +
277 + for (i = 0; i < grp->num_pins; i++) {
278 + const struct mtk_pin_desc *desc;
279 + int *pin_modes = grp->data;
280 + int pin = grp->pins[i];
281 +
282 + desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin];
283 +
284 + mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_MODE,
285 + pin_modes[i]);
286 + }
287 +
288 + return 0;
289 +}
290 +
291 +static int mtk_pinmux_gpio_request_enable(struct pinctrl_dev *pctldev,
292 + struct pinctrl_gpio_range *range,
293 + unsigned int pin)
294 +{
295 + struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
296 + const struct mtk_pin_desc *desc;
297 +
298 + desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin];
299 +
300 + return mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_MODE,
301 + hw->soc->gpio_m);
302 +}
303 +
304 +static int mtk_pinmux_gpio_set_direction(struct pinctrl_dev *pctldev,
305 + struct pinctrl_gpio_range *range,
306 + unsigned int pin, bool input)
307 +{
308 + struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
309 + const struct mtk_pin_desc *desc;
310 +
311 + desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin];
312 +
313 + /* hardware would take 0 as input direction */
314 + return mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR, !input);
315 +}
316 +
317 +static int mtk_pinconf_get(struct pinctrl_dev *pctldev,
318 + unsigned int pin, unsigned long *config)
319 +{
320 + struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
321 + u32 param = pinconf_to_config_param(*config);
322 + int val, val2, err, reg, ret = 1;
323 + const struct mtk_pin_desc *desc;
324 +
325 + desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin];
326 +
327 + switch (param) {
328 + case PIN_CONFIG_BIAS_DISABLE:
329 + if (hw->soc->bias_disable_get) {
330 + err = hw->soc->bias_disable_get(hw, desc, &ret);
331 + if (err)
332 + return err;
333 + } else {
334 + return -ENOTSUPP;
335 + }
336 + break;
337 + case PIN_CONFIG_BIAS_PULL_UP:
338 + if (hw->soc->bias_get) {
339 + err = hw->soc->bias_get(hw, desc, 1, &ret);
340 + if (err)
341 + return err;
342 + } else {
343 + return -ENOTSUPP;
344 + }
345 + break;
346 + case PIN_CONFIG_BIAS_PULL_DOWN:
347 + if (hw->soc->bias_get) {
348 + err = hw->soc->bias_get(hw, desc, 0, &ret);
349 + if (err)
350 + return err;
351 + } else {
352 + return -ENOTSUPP;
353 + }
354 + break;
355 + case PIN_CONFIG_SLEW_RATE:
356 + err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_SR, &val);
357 + if (err)
358 + return err;
359 +
360 + if (!val)
361 + return -EINVAL;
362 +
363 + break;
364 + case PIN_CONFIG_INPUT_ENABLE:
365 + case PIN_CONFIG_OUTPUT_ENABLE:
366 + err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DIR, &val);
367 + if (err)
368 + return err;
369 +
370 + /* HW takes input mode as zero; output mode as non-zero */
371 + if ((val && param == PIN_CONFIG_INPUT_ENABLE) ||
372 + (!val && param == PIN_CONFIG_OUTPUT_ENABLE))
373 + return -EINVAL;
374 +
375 + break;
376 + case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
377 + err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DIR, &val);
378 + if (err)
379 + return err;
380 +
381 + err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_SMT, &val2);
382 + if (err)
383 + return err;
384 +
385 + if (val || !val2)
386 + return -EINVAL;
387 +
388 + break;
389 + case PIN_CONFIG_DRIVE_STRENGTH:
390 + if (hw->soc->drive_get) {
391 + err = hw->soc->drive_get(hw, desc, &ret);
392 + if (err)
393 + return err;
394 + } else {
395 + err = -ENOTSUPP;
396 + }
397 + break;
398 + case MTK_PIN_CONFIG_TDSEL:
399 + case MTK_PIN_CONFIG_RDSEL:
400 + reg = (param == MTK_PIN_CONFIG_TDSEL) ?
401 + PINCTRL_PIN_REG_TDSEL : PINCTRL_PIN_REG_RDSEL;
402 +
403 + err = mtk_hw_get_value(hw, desc, reg, &val);
404 + if (err)
405 + return err;
406 +
407 + ret = val;
408 +
409 + break;
410 + case MTK_PIN_CONFIG_PU_ADV:
411 + case MTK_PIN_CONFIG_PD_ADV:
412 + if (hw->soc->adv_pull_get) {
413 + bool pullup;
414 +
415 + pullup = param == MTK_PIN_CONFIG_PU_ADV;
416 + err = hw->soc->adv_pull_get(hw, desc, pullup, &ret);
417 + if (err)
418 + return err;
419 + } else {
420 + return -ENOTSUPP;
421 + }
422 + break;
423 + default:
424 + return -ENOTSUPP;
425 + }
426 +
427 + *config = pinconf_to_config_packed(param, ret);
428 +
429 + return 0;
430 +}
431 +
432 +static int mtk_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
433 + unsigned long *configs, unsigned int num_configs)
434 +{
435 + struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
436 + const struct mtk_pin_desc *desc;
437 + u32 reg, param, arg;
438 + int cfg, err = 0;
439 +
440 + desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin];
441 +
442 + for (cfg = 0; cfg < num_configs; cfg++) {
443 + param = pinconf_to_config_param(configs[cfg]);
444 + arg = pinconf_to_config_argument(configs[cfg]);
445 +
446 + switch (param) {
447 + case PIN_CONFIG_BIAS_DISABLE:
448 + if (hw->soc->bias_disable_set) {
449 + err = hw->soc->bias_disable_set(hw, desc);
450 + if (err)
451 + return err;
452 + } else {
453 + return -ENOTSUPP;
454 + }
455 + break;
456 + case PIN_CONFIG_BIAS_PULL_UP:
457 + if (hw->soc->bias_set) {
458 + err = hw->soc->bias_set(hw, desc, 1);
459 + if (err)
460 + return err;
461 + } else {
462 + return -ENOTSUPP;
463 + }
464 + break;
465 + case PIN_CONFIG_BIAS_PULL_DOWN:
466 + if (hw->soc->bias_set) {
467 + err = hw->soc->bias_set(hw, desc, 0);
468 + if (err)
469 + return err;
470 + } else {
471 + return -ENOTSUPP;
472 + }
473 + break;
474 + case PIN_CONFIG_OUTPUT_ENABLE:
475 + err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_SMT,
476 + MTK_DISABLE);
477 + if (err)
478 + goto err;
479 +
480 + err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR,
481 + MTK_OUTPUT);
482 + if (err)
483 + goto err;
484 + break;
485 + case PIN_CONFIG_INPUT_ENABLE:
486 +
487 + if (hw->soc->ies_present) {
488 + mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_IES,
489 + MTK_ENABLE);
490 + }
491 +
492 + err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR,
493 + MTK_INPUT);
494 + if (err)
495 + goto err;
496 + break;
497 + case PIN_CONFIG_SLEW_RATE:
498 + err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_SR,
499 + arg);
500 + if (err)
501 + goto err;
502 +
503 + break;
504 + case PIN_CONFIG_OUTPUT:
505 + err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR,
506 + MTK_OUTPUT);
507 + if (err)
508 + goto err;
509 +
510 + err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DO,
511 + arg);
512 + if (err)
513 + goto err;
514 + break;
515 + case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
516 + /* arg = 1: Input mode & SMT enable ;
517 + * arg = 0: Output mode & SMT disable
518 + */
519 + arg = arg ? 2 : 1;
520 + err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR,
521 + arg & 1);
522 + if (err)
523 + goto err;
524 +
525 + err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_SMT,
526 + !!(arg & 2));
527 + if (err)
528 + goto err;
529 + break;
530 + case PIN_CONFIG_DRIVE_STRENGTH:
531 + if (hw->soc->drive_set) {
532 + err = hw->soc->drive_set(hw, desc, arg);
533 + if (err)
534 + return err;
535 + } else {
536 + err = -ENOTSUPP;
537 + }
538 + break;
539 + case MTK_PIN_CONFIG_TDSEL:
540 + case MTK_PIN_CONFIG_RDSEL:
541 + reg = (param == MTK_PIN_CONFIG_TDSEL) ?
542 + PINCTRL_PIN_REG_TDSEL : PINCTRL_PIN_REG_RDSEL;
543 +
544 + err = mtk_hw_set_value(hw, desc, reg, arg);
545 + if (err)
546 + goto err;
547 + break;
548 + case MTK_PIN_CONFIG_PU_ADV:
549 + case MTK_PIN_CONFIG_PD_ADV:
550 + if (hw->soc->adv_pull_set) {
551 + bool pullup;
552 +
553 + pullup = param == MTK_PIN_CONFIG_PU_ADV;
554 + err = hw->soc->adv_pull_set(hw, desc, pullup,
555 + arg);
556 + if (err)
557 + return err;
558 + } else {
559 + return -ENOTSUPP;
560 + }
561 + break;
562 + default:
563 + err = -ENOTSUPP;
564 + }
565 + }
566 +err:
567 + return err;
568 +}
569 +
570 +static int mtk_pinconf_group_get(struct pinctrl_dev *pctldev,
571 + unsigned int group, unsigned long *config)
572 +{
573 + const unsigned int *pins;
574 + unsigned int i, npins, old = 0;
575 + int ret;
576 +
577 + ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins);
578 + if (ret)
579 + return ret;
580 +
581 + for (i = 0; i < npins; i++) {
582 + if (mtk_pinconf_get(pctldev, pins[i], config))
583 + return -ENOTSUPP;
584 +
585 + /* configs do not match between two pins */
586 + if (i && old != *config)
587 + return -ENOTSUPP;
588 +
589 + old = *config;
590 + }
591 +
592 + return 0;
593 +}
594 +
595 +static int mtk_pinconf_group_set(struct pinctrl_dev *pctldev,
596 + unsigned int group, unsigned long *configs,
597 + unsigned int num_configs)
598 +{
599 + const unsigned int *pins;
600 + unsigned int i, npins;
601 + int ret;
602 +
603 + ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins);
604 + if (ret)
605 + return ret;
606 +
607 + for (i = 0; i < npins; i++) {
608 + ret = mtk_pinconf_set(pctldev, pins[i], configs, num_configs);
609 + if (ret)
610 + return ret;
611 + }
612 +
613 + return 0;
614 +}
615 +
616 +static const struct pinctrl_ops mtk_pctlops = {
617 + .get_groups_count = pinctrl_generic_get_group_count,
618 + .get_group_name = pinctrl_generic_get_group_name,
619 + .get_group_pins = pinctrl_generic_get_group_pins,
620 + .dt_node_to_map = pinconf_generic_dt_node_to_map_all,
621 + .dt_free_map = pinconf_generic_dt_free_map,
622 +};
623 +
624 +static const struct pinmux_ops mtk_pmxops = {
625 + .get_functions_count = pinmux_generic_get_function_count,
626 + .get_function_name = pinmux_generic_get_function_name,
627 + .get_function_groups = pinmux_generic_get_function_groups,
628 + .set_mux = mtk_pinmux_set_mux,
629 + .gpio_request_enable = mtk_pinmux_gpio_request_enable,
630 + .gpio_set_direction = mtk_pinmux_gpio_set_direction,
631 + .strict = true,
632 +};
633 +
634 +static const struct pinconf_ops mtk_confops = {
635 + .is_generic = true,
636 + .pin_config_get = mtk_pinconf_get,
637 + .pin_config_set = mtk_pinconf_set,
638 + .pin_config_group_get = mtk_pinconf_group_get,
639 + .pin_config_group_set = mtk_pinconf_group_set,
640 + .pin_config_config_dbg_show = pinconf_generic_dump_config,
641 +};
642 +
643 +static struct pinctrl_desc mtk_desc = {
644 + .name = PINCTRL_PINCTRL_DEV,
645 + .pctlops = &mtk_pctlops,
646 + .pmxops = &mtk_pmxops,
647 + .confops = &mtk_confops,
648 + .owner = THIS_MODULE,
649 +};
650 +
651 +static int mtk_gpio_get(struct gpio_chip *chip, unsigned int gpio)
652 +{
653 + struct mtk_pinctrl *hw = gpiochip_get_data(chip);
654 + const struct mtk_pin_desc *desc;
655 + int value, err;
656 +
657 + desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio];
658 +
659 + err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DI, &value);
660 + if (err)
661 + return err;
662 +
663 + return !!value;
664 +}
665 +
666 +static void mtk_gpio_set(struct gpio_chip *chip, unsigned int gpio, int value)
667 +{
668 + struct mtk_pinctrl *hw = gpiochip_get_data(chip);
669 + const struct mtk_pin_desc *desc;
670 +
671 + desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio];
672 +
673 + mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DO, !!value);
674 +}
675 +
676 +static int mtk_gpio_direction_input(struct gpio_chip *chip, unsigned int gpio)
677 +{
678 + return pinctrl_gpio_direction_input(chip->base + gpio);
679 +}
680 +
681 +static int mtk_gpio_direction_output(struct gpio_chip *chip, unsigned int gpio,
682 + int value)
683 +{
684 + mtk_gpio_set(chip, gpio, value);
685 +
686 + return pinctrl_gpio_direction_output(chip->base + gpio);
687 +}
688 +
689 +static int mtk_gpio_to_irq(struct gpio_chip *chip, unsigned int offset)
690 +{
691 + struct mtk_pinctrl *hw = gpiochip_get_data(chip);
692 + const struct mtk_pin_desc *desc;
693 +
694 + if (!hw->eint)
695 + return -ENOTSUPP;
696 +
697 + desc = (const struct mtk_pin_desc *)&hw->soc->pins[offset];
698 +
699 + if (desc->eint.eint_n == (u16)EINT_NA)
700 + return -ENOTSUPP;
701 +
702 + return mtk_eint_find_irq(hw->eint, desc->eint.eint_n);
703 +}
704 +
705 +static int mtk_gpio_set_config(struct gpio_chip *chip, unsigned int offset,
706 + unsigned long config)
707 +{
708 + struct mtk_pinctrl *hw = gpiochip_get_data(chip);
709 + const struct mtk_pin_desc *desc;
710 + u32 debounce;
711 +
712 + desc = (const struct mtk_pin_desc *)&hw->soc->pins[offset];
713 +
714 + if (!hw->eint ||
715 + pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE ||
716 + desc->eint.eint_n == (u16)EINT_NA)
717 + return -ENOTSUPP;
718 +
719 + debounce = pinconf_to_config_argument(config);
720 +
721 + return mtk_eint_set_debounce(hw->eint, desc->eint.eint_n, debounce);
722 +}
723 +
724 +static int mtk_build_gpiochip(struct mtk_pinctrl *hw, struct device_node *np)
725 +{
726 + struct gpio_chip *chip = &hw->chip;
727 + int ret;
728 +
729 + chip->label = PINCTRL_PINCTRL_DEV;
730 + chip->parent = hw->dev;
731 + chip->request = gpiochip_generic_request;
732 + chip->free = gpiochip_generic_free;
733 + chip->direction_input = mtk_gpio_direction_input;
734 + chip->direction_output = mtk_gpio_direction_output;
735 + chip->get = mtk_gpio_get;
736 + chip->set = mtk_gpio_set;
737 + chip->to_irq = mtk_gpio_to_irq,
738 + chip->set_config = mtk_gpio_set_config,
739 + chip->base = -1;
740 + chip->ngpio = hw->soc->npins;
741 + chip->of_node = np;
742 + chip->of_gpio_n_cells = 2;
743 +
744 + ret = gpiochip_add_data(chip, hw);
745 + if (ret < 0)
746 + return ret;
747 +
748 + /* Just for backward compatible for these old pinctrl nodes without
749 + * "gpio-ranges" property. Otherwise, called directly from a
750 + * DeviceTree-supported pinctrl driver is DEPRECATED.
751 + * Please see Section 2.1 of
752 + * Documentation/devicetree/bindings/gpio/gpio.txt on how to
753 + * bind pinctrl and gpio drivers via the "gpio-ranges" property.
754 + */
755 + if (!of_find_property(np, "gpio-ranges", NULL)) {
756 + ret = gpiochip_add_pin_range(chip, dev_name(hw->dev), 0, 0,
757 + chip->ngpio);
758 + if (ret < 0) {
759 + gpiochip_remove(chip);
760 + return ret;
761 + }
762 + }
763 +
764 + return 0;
765 +}
766 +
767 +static int mtk_build_groups(struct mtk_pinctrl *hw)
768 +{
769 + int err, i;
770 +
771 + for (i = 0; i < hw->soc->ngrps; i++) {
772 + const struct group_desc *group = hw->soc->grps + i;
773 +
774 + err = pinctrl_generic_add_group(hw->pctrl, group->name,
775 + group->pins, group->num_pins,
776 + group->data);
777 + if (err < 0) {
778 + dev_err(hw->dev, "Failed to register group %s\n",
779 + group->name);
780 + return err;
781 + }
782 + }
783 +
784 + return 0;
785 +}
786 +
787 +static int mtk_build_functions(struct mtk_pinctrl *hw)
788 +{
789 + int i, err;
790 +
791 + for (i = 0; i < hw->soc->nfuncs ; i++) {
792 + const struct function_desc *func = hw->soc->funcs + i;
793 +
794 + err = pinmux_generic_add_function(hw->pctrl, func->name,
795 + func->group_names,
796 + func->num_group_names,
797 + func->data);
798 + if (err < 0) {
799 + dev_err(hw->dev, "Failed to register function %s\n",
800 + func->name);
801 + return err;
802 + }
803 + }
804 +
805 + return 0;
806 +}
807 +
808 +int mtk_moore_pinctrl_probe(struct platform_device *pdev,
809 + const struct mtk_pin_soc *soc)
810 +{
811 + struct pinctrl_pin_desc *pins;
812 + struct resource *res;
813 + struct mtk_pinctrl *hw;
814 + int err, i;
815 +
816 + hw = devm_kzalloc(&pdev->dev, sizeof(*hw), GFP_KERNEL);
817 + if (!hw)
818 + return -ENOMEM;
819 +
820 + hw->soc = soc;
821 + hw->dev = &pdev->dev;
822 +
823 + if (!hw->soc->nbase_names) {
824 + dev_err(&pdev->dev,
825 + "SoC should be assigned at least one register base\n");
826 + return -EINVAL;
827 + }
828 +
829 + hw->base = devm_kmalloc_array(&pdev->dev, hw->soc->nbase_names,
830 + sizeof(*hw->base), GFP_KERNEL);
831 + if (!hw->base)
832 + return -ENOMEM;
833 +
834 + for (i = 0; i < hw->soc->nbase_names; i++) {
835 + res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
836 + hw->soc->base_names[i]);
837 + if (!res) {
838 + dev_err(&pdev->dev, "missing IO resource\n");
839 + return -ENXIO;
840 + }
841 +
842 + hw->base[i] = devm_ioremap_resource(&pdev->dev, res);
843 + if (IS_ERR(hw->base[i]))
844 + return PTR_ERR(hw->base[i]);
845 + }
846 +
847 + hw->nbase = hw->soc->nbase_names;
848 +
849 + /* Copy from internal struct mtk_pin_desc to register to the core */
850 + pins = devm_kmalloc_array(&pdev->dev, hw->soc->npins, sizeof(*pins),
851 + GFP_KERNEL);
852 + if (!pins)
853 + return -ENOMEM;
854 +
855 + for (i = 0; i < hw->soc->npins; i++) {
856 + pins[i].number = hw->soc->pins[i].number;
857 + pins[i].name = hw->soc->pins[i].name;
858 + }
859 +
860 + /* Setup pins descriptions per SoC types */
861 + mtk_desc.pins = (const struct pinctrl_pin_desc *)pins;
862 + mtk_desc.npins = hw->soc->npins;
863 + mtk_desc.num_custom_params = ARRAY_SIZE(mtk_custom_bindings);
864 + mtk_desc.custom_params = mtk_custom_bindings;
865 +#ifdef CONFIG_DEBUG_FS
866 + mtk_desc.custom_conf_items = mtk_conf_items;
867 +#endif
868 +
869 + err = devm_pinctrl_register_and_init(&pdev->dev, &mtk_desc, hw,
870 + &hw->pctrl);
871 + if (err)
872 + return err;
873 +
874 + /* Setup groups descriptions per SoC types */
875 + err = mtk_build_groups(hw);
876 + if (err) {
877 + dev_err(&pdev->dev, "Failed to build groups\n");
878 + return err;
879 + }
880 +
881 + /* Setup functions descriptions per SoC types */
882 + err = mtk_build_functions(hw);
883 + if (err) {
884 + dev_err(&pdev->dev, "Failed to build functions\n");
885 + return err;
886 + }
887 +
888 + /* For able to make pinctrl_claim_hogs, we must not enable pinctrl
889 + * until all groups and functions are being added one.
890 + */
891 + err = pinctrl_enable(hw->pctrl);
892 + if (err)
893 + return err;
894 +
895 + err = mtk_build_eint(hw, pdev);
896 + if (err)
897 + dev_warn(&pdev->dev,
898 + "Failed to add EINT, but pinctrl still can work\n");
899 +
900 + /* Build gpiochip should be after pinctrl_enable is done */
901 + err = mtk_build_gpiochip(hw, pdev->dev.of_node);
902 + if (err) {
903 + dev_err(&pdev->dev, "Failed to add gpio_chip\n");
904 + return err;
905 + }
906 +
907 + platform_set_drvdata(pdev, hw);
908 +
909 + return 0;
910 +}
911 --- /dev/null
912 +++ b/drivers/pinctrl/mediatek/pinctrl-moore.h
913 @@ -0,0 +1,51 @@
914 +/* SPDX-License-Identifier: GPL-2.0 */
915 +/*
916 + * Copyright (C) 2017-2018 MediaTek Inc.
917 + *
918 + * Author: Sean Wang <sean.wang@mediatek.com>
919 + *
920 + */
921 +#ifndef __PINCTRL_MOORE_H
922 +#define __PINCTRL_MOORE_H
923 +
924 +#include <linux/io.h>
925 +#include <linux/init.h>
926 +#include <linux/of.h>
927 +#include <linux/of_platform.h>
928 +#include <linux/platform_device.h>
929 +#include <linux/pinctrl/pinctrl.h>
930 +#include <linux/pinctrl/pinmux.h>
931 +#include <linux/pinctrl/pinconf.h>
932 +#include <linux/pinctrl/pinconf-generic.h>
933 +
934 +#include "../core.h"
935 +#include "../pinconf.h"
936 +#include "../pinmux.h"
937 +#include "mtk-eint.h"
938 +#include "pinctrl-mtk-common-v2.h"
939 +
940 +#define MTK_RANGE(_a) { .range = (_a), .nranges = ARRAY_SIZE(_a), }
941 +
942 +#define MTK_PIN(_number, _name, _eint_m, _eint_n, _drv_n) { \
943 + .number = _number, \
944 + .name = _name, \
945 + .eint = { \
946 + .eint_m = _eint_m, \
947 + .eint_n = _eint_n, \
948 + }, \
949 + .drv_n = _drv_n, \
950 + .funcs = NULL, \
951 + }
952 +
953 +#define PINCTRL_PIN_GROUP(name, id) \
954 + { \
955 + name, \
956 + id##_pins, \
957 + ARRAY_SIZE(id##_pins), \
958 + id##_funcs, \
959 + }
960 +
961 +int mtk_moore_pinctrl_probe(struct platform_device *pdev,
962 + const struct mtk_pin_soc *soc);
963 +
964 +#endif /* __PINCTRL_MOORE_H */
965 --- /dev/null
966 +++ b/drivers/pinctrl/mediatek/pinctrl-mt6765.c
967 @@ -0,0 +1,1108 @@
968 +// SPDX-License-Identifier: GPL-2.0
969 +/*
970 + * Copyright (C) 2018 MediaTek Inc.
971 + *
972 + * Author: ZH Chen <zh.chen@mediatek.com>
973 + *
974 + */
975 +
976 +#include "pinctrl-mtk-mt6765.h"
977 +#include "pinctrl-paris.h"
978 +
979 +/* MT6765 have multiple bases to program pin configuration listed as the below:
980 + * iocfg[0]:0x10005000, iocfg[1]:0x10002C00, iocfg[2]:0x10002800,
981 + * iocfg[3]:0x10002A00, iocfg[4]:0x10002000, iocfg[5]:0x10002200,
982 + * iocfg[6]:0x10002500, iocfg[7]:0x10002600.
983 + * _i_base could be used to indicate what base the pin should be mapped into.
984 + */
985 +
986 +#define PIN_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, _x_bits) \
987 + PIN_FIELD_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \
988 + _x_bits, 32, 0)
989 +
990 +#define PINS_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, _x_bits) \
991 + PIN_FIELD_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \
992 + _x_bits, 32, 1)
993 +
994 +static const struct mtk_pin_field_calc mt6765_pin_mode_range[] = {
995 + PIN_FIELD(0, 202, 0x300, 0x10, 0, 4),
996 +};
997 +
998 +static const struct mtk_pin_field_calc mt6765_pin_dir_range[] = {
999 + PIN_FIELD(0, 202, 0x0, 0x10, 0, 1),
1000 +};
1001 +
1002 +static const struct mtk_pin_field_calc mt6765_pin_di_range[] = {
1003 + PIN_FIELD(0, 202, 0x200, 0x10, 0, 1),
1004 +};
1005 +
1006 +static const struct mtk_pin_field_calc mt6765_pin_do_range[] = {
1007 + PIN_FIELD(0, 202, 0x100, 0x10, 0, 1),
1008 +};
1009 +
1010 +static const struct mtk_pin_field_calc mt6765_pin_smt_range[] = {
1011 + PINS_FIELD_BASE(0, 3, 2, 0x00b0, 0x10, 4, 1),
1012 + PINS_FIELD_BASE(4, 7, 2, 0x00b0, 0x10, 5, 1),
1013 + PIN_FIELD_BASE(8, 8, 3, 0x0080, 0x10, 3, 1),
1014 + PINS_FIELD_BASE(9, 11, 2, 0x00b0, 0x10, 6, 1),
1015 + PIN_FIELD_BASE(12, 12, 5, 0x0060, 0x10, 9, 1),
1016 + PINS_FIELD_BASE(13, 16, 6, 0x00b0, 0x10, 10, 1),
1017 + PINS_FIELD_BASE(17, 20, 6, 0x00b0, 0x10, 8, 1),
1018 + PINS_FIELD_BASE(21, 24, 6, 0x00b0, 0x10, 9, 1),
1019 + PINS_FIELD_BASE(25, 28, 6, 0x00b0, 0x10, 7, 1),
1020 + PIN_FIELD_BASE(29, 29, 6, 0x00b0, 0x10, 0, 1),
1021 + PIN_FIELD_BASE(30, 30, 6, 0x00b0, 0x10, 1, 1),
1022 + PINS_FIELD_BASE(31, 34, 6, 0x00b0, 0x10, 2, 1),
1023 + PINS_FIELD_BASE(35, 36, 6, 0x00b0, 0x10, 5, 1),
1024 + PIN_FIELD_BASE(37, 37, 6, 0x00b0, 0x10, 6, 1),
1025 + PIN_FIELD_BASE(38, 38, 6, 0x00b0, 0x10, 4, 1),
1026 + PINS_FIELD_BASE(39, 40, 6, 0x00b0, 0x10, 3, 1),
1027 + PINS_FIELD_BASE(41, 42, 7, 0x00c0, 0x10, 6, 1),
1028 + PIN_FIELD_BASE(43, 43, 7, 0x00c0, 0x10, 3, 1),
1029 + PIN_FIELD_BASE(44, 44, 7, 0x00c0, 0x10, 4, 1),
1030 + PIN_FIELD_BASE(45, 45, 7, 0x00c0, 0x10, 8, 1),
1031 + PINS_FIELD_BASE(46, 47, 7, 0x00c0, 0x10, 7, 1),
1032 + PIN_FIELD_BASE(48, 48, 7, 0x00c0, 0x10, 15, 1),
1033 + PIN_FIELD_BASE(49, 49, 7, 0x00c0, 0x10, 17, 1),
1034 + PIN_FIELD_BASE(50, 50, 7, 0x00c0, 0x10, 14, 1),
1035 + PIN_FIELD_BASE(51, 51, 7, 0x00c0, 0x10, 16, 1),
1036 + PINS_FIELD_BASE(52, 57, 7, 0x00c0, 0x10, 0, 1),
1037 + PINS_FIELD_BASE(58, 60, 7, 0x00c0, 0x10, 12, 1),
1038 + PINS_FIELD_BASE(61, 62, 3, 0x0080, 0x10, 5, 1),
1039 + PINS_FIELD_BASE(63, 64, 3, 0x0080, 0x10, 4, 1),
1040 + PINS_FIELD_BASE(65, 66, 3, 0x0080, 0x10, 7, 1),
1041 + PINS_FIELD_BASE(67, 68, 3, 0x0080, 0x10, 6, 1),
1042 + PINS_FIELD_BASE(69, 73, 3, 0x0080, 0x10, 1, 1),
1043 + PINS_FIELD_BASE(74, 78, 3, 0x0080, 0x10, 2, 1),
1044 + PINS_FIELD_BASE(79, 80, 3, 0x0080, 0x10, 0, 1),
1045 + PIN_FIELD_BASE(81, 81, 3, 0x0080, 0x10, 12, 1),
1046 + PIN_FIELD_BASE(82, 82, 3, 0x0080, 0x10, 11, 1),
1047 + PIN_FIELD_BASE(83, 83, 3, 0x0080, 0x10, 9, 1),
1048 + PIN_FIELD_BASE(84, 84, 3, 0x0080, 0x10, 10, 1),
1049 + PIN_FIELD_BASE(85, 85, 7, 0x00c0, 0x10, 12, 1),
1050 + PIN_FIELD_BASE(86, 86, 7, 0x00c0, 0x10, 13, 1),
1051 + PIN_FIELD_BASE(87, 87, 7, 0x00c0, 0x10, 2, 1),
1052 + PIN_FIELD_BASE(88, 88, 7, 0x00c0, 0x10, 1, 1),
1053 + PIN_FIELD_BASE(89, 89, 2, 0x00b0, 0x10, 13, 1),
1054 + PIN_FIELD_BASE(90, 90, 3, 0x0080, 0x10, 8, 1),
1055 + PINS_FIELD_BASE(91, 92, 2, 0x00b0, 0x10, 8, 1),
1056 + PINS_FIELD_BASE(93, 94, 2, 0x00b0, 0x10, 7, 1),
1057 + PINS_FIELD_BASE(95, 96, 2, 0x00b0, 0x10, 14, 1),
1058 + PINS_FIELD_BASE(97, 98, 2, 0x00b0, 0x10, 2, 1),
1059 + PIN_FIELD_BASE(99, 99, 2, 0x00b0, 0x10, 0, 1),
1060 + PIN_FIELD_BASE(100, 100, 2, 0x00b0, 0x10, 1, 1),
1061 + PINS_FIELD_BASE(101, 102, 2, 0x00b0, 0x10, 3, 1),
1062 + PIN_FIELD_BASE(103, 103, 2, 0x00b0, 0x10, 9, 1),
1063 + PIN_FIELD_BASE(104, 104, 2, 0x00b0, 0x10, 11, 1),
1064 + PIN_FIELD_BASE(105, 105, 2, 0x00b0, 0x10, 10, 1),
1065 + PIN_FIELD_BASE(106, 106, 2, 0x00b0, 0x10, 12, 1),
1066 + PIN_FIELD_BASE(107, 107, 1, 0x0080, 0x10, 4, 1),
1067 + PIN_FIELD_BASE(108, 108, 1, 0x0080, 0x10, 3, 1),
1068 + PIN_FIELD_BASE(109, 109, 1, 0x0080, 0x10, 5, 1),
1069 + PIN_FIELD_BASE(110, 110, 1, 0x0080, 0x10, 0, 1),
1070 + PIN_FIELD_BASE(111, 111, 1, 0x0080, 0x10, 1, 1),
1071 + PIN_FIELD_BASE(112, 112, 1, 0x0080, 0x10, 2, 1),
1072 + PIN_FIELD_BASE(113, 113, 1, 0x0080, 0x10, 9, 1),
1073 + PIN_FIELD_BASE(114, 114, 1, 0x0080, 0x10, 10, 1),
1074 + PIN_FIELD_BASE(115, 115, 1, 0x0080, 0x10, 6, 1),
1075 + PIN_FIELD_BASE(116, 116, 1, 0x0080, 0x10, 7, 1),
1076 + PIN_FIELD_BASE(117, 117, 1, 0x0080, 0x10, 12, 1),
1077 + PIN_FIELD_BASE(118, 118, 1, 0x0080, 0x10, 13, 1),
1078 + PIN_FIELD_BASE(119, 119, 1, 0x0080, 0x10, 14, 1),
1079 + PIN_FIELD_BASE(120, 120, 1, 0x0080, 0x10, 11, 1),
1080 + PIN_FIELD_BASE(121, 121, 1, 0x0080, 0x10, 8, 1),
1081 + PIN_FIELD_BASE(122, 122, 4, 0x0080, 0x10, 2, 1),
1082 + PIN_FIELD_BASE(123, 123, 4, 0x0080, 0x10, 3, 1),
1083 + PIN_FIELD_BASE(124, 124, 4, 0x0080, 0x10, 1, 1),
1084 + PIN_FIELD_BASE(125, 125, 4, 0x0080, 0x10, 5, 1),
1085 + PIN_FIELD_BASE(126, 126, 4, 0x0080, 0x10, 7, 1),
1086 + PIN_FIELD_BASE(127, 127, 4, 0x0080, 0x10, 9, 1),
1087 + PIN_FIELD_BASE(128, 128, 4, 0x0080, 0x10, 4, 1),
1088 + PIN_FIELD_BASE(129, 129, 4, 0x0080, 0x10, 8, 1),
1089 + PIN_FIELD_BASE(130, 130, 4, 0x0080, 0x10, 10, 1),
1090 + PIN_FIELD_BASE(131, 131, 4, 0x0080, 0x10, 11, 1),
1091 + PIN_FIELD_BASE(132, 132, 4, 0x0080, 0x10, 6, 1),
1092 + PIN_FIELD_BASE(133, 133, 4, 0x0080, 0x10, 12, 1),
1093 + PIN_FIELD_BASE(134, 134, 5, 0x0060, 0x10, 11, 1),
1094 + PIN_FIELD_BASE(135, 135, 5, 0x0060, 0x10, 13, 1),
1095 + PIN_FIELD_BASE(136, 136, 5, 0x0060, 0x10, 1, 1),
1096 + PIN_FIELD_BASE(137, 137, 5, 0x0060, 0x10, 7, 1),
1097 + PIN_FIELD_BASE(138, 138, 5, 0x0060, 0x10, 4, 1),
1098 + PIN_FIELD_BASE(139, 139, 5, 0x0060, 0x10, 5, 1),
1099 + PIN_FIELD_BASE(140, 140, 5, 0x0060, 0x10, 0, 1),
1100 + PIN_FIELD_BASE(141, 141, 5, 0x0060, 0x10, 6, 1),
1101 + PIN_FIELD_BASE(142, 142, 5, 0x0060, 0x10, 2, 1),
1102 + PIN_FIELD_BASE(143, 143, 5, 0x0060, 0x10, 3, 1),
1103 + PINS_FIELD_BASE(144, 147, 5, 0x0060, 0x10, 10, 1),
1104 + PINS_FIELD_BASE(148, 149, 5, 0x0060, 0x10, 12, 1),
1105 + PINS_FIELD_BASE(150, 151, 7, 0x00c0, 0x10, 9, 1),
1106 + PINS_FIELD_BASE(152, 153, 7, 0x00c0, 0x10, 10, 1),
1107 + PIN_FIELD_BASE(154, 154, 7, 0x00c0, 0x10, 11, 1),
1108 + PINS_FIELD_BASE(155, 158, 3, 0x0080, 0x10, 13, 1),
1109 + PIN_FIELD_BASE(159, 159, 7, 0x00c0, 0x10, 11, 1),
1110 + PIN_FIELD_BASE(160, 160, 5, 0x0060, 0x10, 8, 1),
1111 + PIN_FIELD_BASE(161, 161, 1, 0x0080, 0x10, 15, 1),
1112 + PIN_FIELD_BASE(162, 162, 1, 0x0080, 0x10, 16, 1),
1113 + PINS_FIELD_BASE(163, 170, 4, 0x0080, 0x10, 0, 1),
1114 + PINS_FIELD_BASE(171, 179, 7, 0x00c0, 0x10, 5, 1),
1115 +};
1116 +
1117 +static const struct mtk_pin_field_calc mt6765_pin_pd_range[] = {
1118 + PIN_FIELD_BASE(0, 0, 2, 0x0040, 0x10, 6, 1),
1119 + PIN_FIELD_BASE(1, 1, 2, 0x0040, 0x10, 7, 1),
1120 + PIN_FIELD_BASE(2, 2, 2, 0x0040, 0x10, 10, 1),
1121 + PIN_FIELD_BASE(3, 3, 2, 0x0040, 0x10, 11, 1),
1122 + PIN_FIELD_BASE(4, 4, 2, 0x0040, 0x10, 12, 1),
1123 + PIN_FIELD_BASE(5, 5, 2, 0x0040, 0x10, 13, 1),
1124 + PIN_FIELD_BASE(6, 6, 2, 0x0040, 0x10, 14, 1),
1125 + PIN_FIELD_BASE(7, 7, 2, 0x0040, 0x10, 15, 1),
1126 + PIN_FIELD_BASE(8, 8, 3, 0x0040, 0x10, 12, 1),
1127 + PIN_FIELD_BASE(9, 9, 2, 0x0040, 0x10, 16, 1),
1128 + PIN_FIELD_BASE(10, 10, 2, 0x0040, 0x10, 8, 1),
1129 + PIN_FIELD_BASE(11, 11, 2, 0x0040, 0x10, 9, 1),
1130 + PIN_FIELD_BASE(12, 12, 5, 0x0030, 0x10, 9, 1),
1131 + PIN_FIELD_BASE(13, 13, 6, 0x0040, 0x10, 14, 1),
1132 + PIN_FIELD_BASE(14, 14, 6, 0x0040, 0x10, 13, 1),
1133 + PIN_FIELD_BASE(15, 15, 6, 0x0040, 0x10, 15, 1),
1134 + PIN_FIELD_BASE(16, 16, 6, 0x0040, 0x10, 12, 1),
1135 + PIN_FIELD_BASE(17, 17, 6, 0x0040, 0x10, 7, 1),
1136 + PIN_FIELD_BASE(18, 18, 6, 0x0040, 0x10, 4, 1),
1137 + PIN_FIELD_BASE(19, 19, 6, 0x0040, 0x10, 6, 1),
1138 + PIN_FIELD_BASE(20, 20, 6, 0x0040, 0x10, 5, 1),
1139 + PIN_FIELD_BASE(21, 21, 6, 0x0040, 0x10, 10, 1),
1140 + PIN_FIELD_BASE(22, 22, 6, 0x0040, 0x10, 9, 1),
1141 + PIN_FIELD_BASE(23, 23, 6, 0x0040, 0x10, 11, 1),
1142 + PIN_FIELD_BASE(24, 24, 6, 0x0040, 0x10, 8, 1),
1143 + PIN_FIELD_BASE(25, 25, 6, 0x0040, 0x10, 2, 1),
1144 + PIN_FIELD_BASE(26, 26, 6, 0x0040, 0x10, 1, 1),
1145 + PIN_FIELD_BASE(27, 27, 6, 0x0040, 0x10, 3, 1),
1146 + PINS_FIELD_BASE(28, 40, 6, 0x0040, 0x10, 0, 1),
1147 + PIN_FIELD_BASE(41, 41, 7, 0x0060, 0x10, 19, 1),
1148 + PIN_FIELD_BASE(42, 42, 7, 0x0060, 0x10, 9, 1),
1149 + PIN_FIELD_BASE(43, 43, 7, 0x0060, 0x10, 8, 1),
1150 + PIN_FIELD_BASE(44, 44, 7, 0x0060, 0x10, 10, 1),
1151 + PIN_FIELD_BASE(45, 45, 7, 0x0060, 0x10, 22, 1),
1152 + PIN_FIELD_BASE(46, 46, 7, 0x0060, 0x10, 21, 1),
1153 + PIN_FIELD_BASE(47, 47, 7, 0x0060, 0x10, 20, 1),
1154 + PIN_FIELD_BASE(48, 48, 7, 0x0070, 0x10, 3, 1),
1155 + PIN_FIELD_BASE(49, 49, 7, 0x0070, 0x10, 5, 1),
1156 + PIN_FIELD_BASE(50, 50, 7, 0x0070, 0x10, 2, 1),
1157 + PIN_FIELD_BASE(51, 51, 7, 0x0070, 0x10, 4, 1),
1158 + PIN_FIELD_BASE(52, 52, 7, 0x0060, 0x10, 1, 1),
1159 + PIN_FIELD_BASE(53, 53, 7, 0x0060, 0x10, 0, 1),
1160 + PIN_FIELD_BASE(54, 54, 7, 0x0060, 0x10, 5, 1),
1161 + PIN_FIELD_BASE(55, 55, 7, 0x0060, 0x10, 3, 1),
1162 + PIN_FIELD_BASE(56, 56, 7, 0x0060, 0x10, 4, 1),
1163 + PIN_FIELD_BASE(57, 57, 7, 0x0060, 0x10, 2, 1),
1164 + PIN_FIELD_BASE(58, 58, 7, 0x0070, 0x10, 0, 1),
1165 + PIN_FIELD_BASE(59, 59, 7, 0x0060, 0x10, 31, 1),
1166 + PIN_FIELD_BASE(60, 60, 7, 0x0060, 0x10, 30, 1),
1167 + PIN_FIELD_BASE(61, 61, 3, 0x0040, 0x10, 18, 1),
1168 + PIN_FIELD_BASE(62, 62, 3, 0x0040, 0x10, 14, 1),
1169 + PIN_FIELD_BASE(63, 63, 3, 0x0040, 0x10, 17, 1),
1170 + PIN_FIELD_BASE(64, 64, 3, 0x0040, 0x10, 13, 1),
1171 + PIN_FIELD_BASE(65, 65, 3, 0x0040, 0x10, 20, 1),
1172 + PIN_FIELD_BASE(66, 66, 3, 0x0040, 0x10, 16, 1),
1173 + PIN_FIELD_BASE(67, 67, 3, 0x0040, 0x10, 19, 1),
1174 + PIN_FIELD_BASE(68, 68, 3, 0x0040, 0x10, 15, 1),
1175 + PIN_FIELD_BASE(69, 69, 3, 0x0040, 0x10, 8, 1),
1176 + PIN_FIELD_BASE(70, 70, 3, 0x0040, 0x10, 7, 1),
1177 + PIN_FIELD_BASE(71, 71, 3, 0x0040, 0x10, 6, 1),
1178 + PIN_FIELD_BASE(72, 72, 3, 0x0040, 0x10, 5, 1),
1179 + PIN_FIELD_BASE(73, 73, 3, 0x0040, 0x10, 4, 1),
1180 + PIN_FIELD_BASE(74, 74, 3, 0x0040, 0x10, 3, 1),
1181 + PIN_FIELD_BASE(75, 75, 3, 0x0040, 0x10, 2, 1),
1182 + PIN_FIELD_BASE(76, 76, 3, 0x0040, 0x10, 1, 1),
1183 + PIN_FIELD_BASE(77, 77, 3, 0x0040, 0x10, 0, 1),
1184 + PIN_FIELD_BASE(78, 78, 3, 0x0040, 0x10, 9, 1),
1185 + PIN_FIELD_BASE(79, 79, 3, 0x0040, 0x10, 11, 1),
1186 + PIN_FIELD_BASE(80, 80, 3, 0x0040, 0x10, 10, 1),
1187 + PIN_FIELD_BASE(81, 81, 3, 0x0040, 0x10, 25, 1),
1188 + PIN_FIELD_BASE(82, 82, 3, 0x0040, 0x10, 24, 1),
1189 + PIN_FIELD_BASE(83, 83, 3, 0x0040, 0x10, 22, 1),
1190 + PIN_FIELD_BASE(84, 84, 3, 0x0040, 0x10, 23, 1),
1191 + PIN_FIELD_BASE(85, 85, 7, 0x0070, 0x10, 1, 1),
1192 + PIN_FIELD_BASE(86, 86, 7, 0x0060, 0x10, 29, 1),
1193 + PIN_FIELD_BASE(87, 87, 7, 0x0060, 0x10, 7, 1),
1194 + PIN_FIELD_BASE(88, 88, 7, 0x0060, 0x10, 6, 1),
1195 + PIN_FIELD_BASE(89, 89, 2, 0x0040, 0x10, 21, 1),
1196 + PINS_FIELD_BASE(90, 94, 3, 0x0040, 0x10, 21, 1),
1197 + PIN_FIELD_BASE(95, 95, 2, 0x0040, 0x10, 22, 1),
1198 + PIN_FIELD_BASE(96, 96, 2, 0x0040, 0x10, 23, 1),
1199 + PIN_FIELD_BASE(97, 97, 2, 0x0040, 0x10, 2, 1),
1200 + PIN_FIELD_BASE(98, 98, 2, 0x0040, 0x10, 3, 1),
1201 + PIN_FIELD_BASE(99, 99, 2, 0x0040, 0x10, 0, 1),
1202 + PIN_FIELD_BASE(100, 100, 2, 0x0040, 0x10, 1, 1),
1203 + PIN_FIELD_BASE(101, 101, 2, 0x0040, 0x10, 4, 1),
1204 + PIN_FIELD_BASE(102, 102, 2, 0x0040, 0x10, 5, 1),
1205 + PIN_FIELD_BASE(103, 103, 2, 0x0040, 0x10, 17, 1),
1206 + PIN_FIELD_BASE(104, 104, 2, 0x0040, 0x10, 19, 1),
1207 + PIN_FIELD_BASE(105, 105, 2, 0x0040, 0x10, 18, 1),
1208 + PIN_FIELD_BASE(106, 106, 2, 0x0040, 0x10, 20, 1),
1209 + PIN_FIELD_BASE(107, 107, 1, 0x0040, 0x10, 4, 1),
1210 + PIN_FIELD_BASE(108, 108, 1, 0x0040, 0x10, 3, 1),
1211 + PIN_FIELD_BASE(109, 109, 1, 0x0040, 0x10, 5, 1),
1212 + PIN_FIELD_BASE(110, 110, 1, 0x0040, 0x10, 0, 1),
1213 + PIN_FIELD_BASE(111, 111, 1, 0x0040, 0x10, 1, 1),
1214 + PIN_FIELD_BASE(112, 112, 1, 0x0040, 0x10, 2, 1),
1215 + PIN_FIELD_BASE(113, 113, 1, 0x0040, 0x10, 9, 1),
1216 + PIN_FIELD_BASE(114, 114, 1, 0x0040, 0x10, 10, 1),
1217 + PIN_FIELD_BASE(115, 115, 1, 0x0040, 0x10, 6, 1),
1218 + PIN_FIELD_BASE(116, 116, 1, 0x0040, 0x10, 7, 1),
1219 + PIN_FIELD_BASE(117, 117, 1, 0x0040, 0x10, 12, 1),
1220 + PIN_FIELD_BASE(118, 118, 1, 0x0040, 0x10, 13, 1),
1221 + PIN_FIELD_BASE(119, 119, 1, 0x0040, 0x10, 14, 1),
1222 + PIN_FIELD_BASE(120, 120, 1, 0x0040, 0x10, 11, 1),
1223 + PINS_FIELD_BASE(121, 133, 1, 0x0040, 0x10, 8, 1),
1224 + PIN_FIELD_BASE(134, 134, 5, 0x0030, 0x10, 14, 1),
1225 + PIN_FIELD_BASE(135, 135, 5, 0x0030, 0x10, 19, 1),
1226 + PIN_FIELD_BASE(136, 136, 5, 0x0030, 0x10, 1, 1),
1227 + PIN_FIELD_BASE(137, 137, 5, 0x0030, 0x10, 7, 1),
1228 + PIN_FIELD_BASE(138, 138, 5, 0x0030, 0x10, 4, 1),
1229 + PIN_FIELD_BASE(139, 139, 5, 0x0030, 0x10, 5, 1),
1230 + PIN_FIELD_BASE(140, 140, 5, 0x0030, 0x10, 0, 1),
1231 + PIN_FIELD_BASE(141, 141, 5, 0x0030, 0x10, 6, 1),
1232 + PIN_FIELD_BASE(142, 142, 5, 0x0030, 0x10, 2, 1),
1233 + PIN_FIELD_BASE(143, 143, 5, 0x0030, 0x10, 3, 1),
1234 + PIN_FIELD_BASE(144, 144, 5, 0x0030, 0x10, 12, 1),
1235 + PIN_FIELD_BASE(145, 145, 5, 0x0030, 0x10, 11, 1),
1236 + PIN_FIELD_BASE(146, 146, 5, 0x0030, 0x10, 13, 1),
1237 + PIN_FIELD_BASE(147, 147, 5, 0x0030, 0x10, 10, 1),
1238 + PIN_FIELD_BASE(148, 148, 5, 0x0030, 0x10, 15, 1),
1239 + PIN_FIELD_BASE(149, 149, 5, 0x0030, 0x10, 16, 1),
1240 + PIN_FIELD_BASE(150, 150, 7, 0x0060, 0x10, 23, 1),
1241 + PIN_FIELD_BASE(151, 151, 7, 0x0060, 0x10, 24, 1),
1242 + PIN_FIELD_BASE(152, 152, 7, 0x0060, 0x10, 25, 1),
1243 + PIN_FIELD_BASE(153, 153, 7, 0x0060, 0x10, 26, 1),
1244 + PIN_FIELD_BASE(154, 154, 7, 0x0060, 0x10, 28, 1),
1245 + PIN_FIELD_BASE(155, 155, 3, 0x0040, 0x10, 28, 1),
1246 + PIN_FIELD_BASE(156, 156, 3, 0x0040, 0x10, 27, 1),
1247 + PIN_FIELD_BASE(157, 157, 3, 0x0040, 0x10, 29, 1),
1248 + PIN_FIELD_BASE(158, 158, 3, 0x0040, 0x10, 26, 1),
1249 + PIN_FIELD_BASE(159, 159, 7, 0x0060, 0x10, 27, 1),
1250 + PIN_FIELD_BASE(160, 160, 5, 0x0030, 0x10, 8, 1),
1251 + PIN_FIELD_BASE(161, 161, 1, 0x0040, 0x10, 15, 1),
1252 + PIN_FIELD_BASE(162, 162, 1, 0x0040, 0x10, 16, 1),
1253 + PIN_FIELD_BASE(163, 163, 4, 0x0020, 0x10, 0, 1),
1254 + PIN_FIELD_BASE(164, 164, 4, 0x0020, 0x10, 1, 1),
1255 + PIN_FIELD_BASE(165, 165, 4, 0x0020, 0x10, 2, 1),
1256 + PIN_FIELD_BASE(166, 166, 4, 0x0020, 0x10, 3, 1),
1257 + PIN_FIELD_BASE(167, 167, 4, 0x0020, 0x10, 4, 1),
1258 + PIN_FIELD_BASE(168, 168, 4, 0x0020, 0x10, 5, 1),
1259 + PIN_FIELD_BASE(169, 169, 4, 0x0020, 0x10, 6, 1),
1260 + PIN_FIELD_BASE(170, 170, 4, 0x0020, 0x10, 7, 1),
1261 + PIN_FIELD_BASE(171, 171, 7, 0x0060, 0x10, 17, 1),
1262 + PIN_FIELD_BASE(172, 172, 7, 0x0060, 0x10, 18, 1),
1263 + PIN_FIELD_BASE(173, 173, 7, 0x0060, 0x10, 11, 1),
1264 + PIN_FIELD_BASE(174, 174, 7, 0x0060, 0x10, 12, 1),
1265 + PIN_FIELD_BASE(175, 175, 7, 0x0060, 0x10, 13, 1),
1266 + PIN_FIELD_BASE(176, 176, 7, 0x0060, 0x10, 14, 1),
1267 + PIN_FIELD_BASE(177, 177, 7, 0x0060, 0x10, 15, 1),
1268 + PINS_FIELD_BASE(178, 179, 7, 0x0060, 0x10, 16, 1),
1269 +};
1270 +
1271 +static const struct mtk_pin_field_calc mt6765_pin_pu_range[] = {
1272 + PIN_FIELD_BASE(0, 0, 2, 0x0060, 0x10, 6, 1),
1273 + PIN_FIELD_BASE(1, 1, 2, 0x0060, 0x10, 7, 1),
1274 + PIN_FIELD_BASE(2, 2, 2, 0x0060, 0x10, 10, 1),
1275 + PIN_FIELD_BASE(3, 3, 2, 0x0060, 0x10, 11, 1),
1276 + PIN_FIELD_BASE(4, 4, 2, 0x0060, 0x10, 12, 1),
1277 + PIN_FIELD_BASE(5, 5, 2, 0x0060, 0x10, 13, 1),
1278 + PIN_FIELD_BASE(6, 6, 2, 0x0060, 0x10, 14, 1),
1279 + PIN_FIELD_BASE(7, 7, 2, 0x0060, 0x10, 15, 1),
1280 + PIN_FIELD_BASE(8, 8, 3, 0x0050, 0x10, 12, 1),
1281 + PIN_FIELD_BASE(9, 9, 2, 0x0060, 0x10, 16, 1),
1282 + PIN_FIELD_BASE(10, 10, 2, 0x0060, 0x10, 8, 1),
1283 + PIN_FIELD_BASE(11, 11, 2, 0x0060, 0x10, 9, 1),
1284 + PIN_FIELD_BASE(12, 12, 5, 0x0040, 0x10, 9, 1),
1285 + PIN_FIELD_BASE(13, 13, 6, 0x0060, 0x10, 14, 1),
1286 + PIN_FIELD_BASE(14, 14, 6, 0x0060, 0x10, 13, 1),
1287 + PIN_FIELD_BASE(15, 15, 6, 0x0060, 0x10, 15, 1),
1288 + PIN_FIELD_BASE(16, 16, 6, 0x0060, 0x10, 12, 1),
1289 + PIN_FIELD_BASE(17, 17, 6, 0x0060, 0x10, 7, 1),
1290 + PIN_FIELD_BASE(18, 18, 6, 0x0060, 0x10, 4, 1),
1291 + PIN_FIELD_BASE(19, 19, 6, 0x0060, 0x10, 6, 1),
1292 + PIN_FIELD_BASE(20, 20, 6, 0x0060, 0x10, 5, 1),
1293 + PIN_FIELD_BASE(21, 21, 6, 0x0060, 0x10, 10, 1),
1294 + PIN_FIELD_BASE(22, 22, 6, 0x0060, 0x10, 9, 1),
1295 + PIN_FIELD_BASE(23, 23, 6, 0x0060, 0x10, 11, 1),
1296 + PIN_FIELD_BASE(24, 24, 6, 0x0060, 0x10, 8, 1),
1297 + PIN_FIELD_BASE(25, 25, 6, 0x0060, 0x10, 2, 1),
1298 + PIN_FIELD_BASE(26, 26, 6, 0x0060, 0x10, 1, 1),
1299 + PIN_FIELD_BASE(27, 27, 6, 0x0060, 0x10, 3, 1),
1300 + PINS_FIELD_BASE(28, 40, 6, 0x0060, 0x10, 0, 1),
1301 + PIN_FIELD_BASE(41, 41, 7, 0x0080, 0x10, 19, 1),
1302 + PIN_FIELD_BASE(42, 42, 7, 0x0080, 0x10, 9, 1),
1303 + PIN_FIELD_BASE(43, 43, 7, 0x0080, 0x10, 8, 1),
1304 + PIN_FIELD_BASE(44, 44, 7, 0x0080, 0x10, 10, 1),
1305 + PIN_FIELD_BASE(45, 45, 7, 0x0080, 0x10, 22, 1),
1306 + PIN_FIELD_BASE(46, 46, 7, 0x0080, 0x10, 21, 1),
1307 + PIN_FIELD_BASE(47, 47, 7, 0x0080, 0x10, 20, 1),
1308 + PIN_FIELD_BASE(48, 48, 7, 0x0090, 0x10, 3, 1),
1309 + PIN_FIELD_BASE(49, 49, 7, 0x0090, 0x10, 5, 1),
1310 + PIN_FIELD_BASE(50, 50, 7, 0x0090, 0x10, 2, 1),
1311 + PIN_FIELD_BASE(51, 51, 7, 0x0090, 0x10, 4, 1),
1312 + PIN_FIELD_BASE(52, 52, 7, 0x0080, 0x10, 1, 1),
1313 + PIN_FIELD_BASE(53, 53, 7, 0x0080, 0x10, 0, 1),
1314 + PIN_FIELD_BASE(54, 54, 7, 0x0080, 0x10, 5, 1),
1315 + PIN_FIELD_BASE(55, 55, 7, 0x0080, 0x10, 3, 1),
1316 + PIN_FIELD_BASE(56, 56, 7, 0x0080, 0x10, 4, 1),
1317 + PIN_FIELD_BASE(57, 57, 7, 0x0080, 0x10, 2, 1),
1318 + PIN_FIELD_BASE(58, 58, 7, 0x0090, 0x10, 0, 1),
1319 + PIN_FIELD_BASE(59, 59, 7, 0x0080, 0x10, 31, 1),
1320 + PIN_FIELD_BASE(60, 60, 7, 0x0080, 0x10, 30, 1),
1321 + PIN_FIELD_BASE(61, 61, 3, 0x0050, 0x10, 18, 1),
1322 + PIN_FIELD_BASE(62, 62, 3, 0x0050, 0x10, 14, 1),
1323 + PIN_FIELD_BASE(63, 63, 3, 0x0050, 0x10, 17, 1),
1324 + PIN_FIELD_BASE(64, 64, 3, 0x0050, 0x10, 13, 1),
1325 + PIN_FIELD_BASE(65, 65, 3, 0x0050, 0x10, 20, 1),
1326 + PIN_FIELD_BASE(66, 66, 3, 0x0050, 0x10, 16, 1),
1327 + PIN_FIELD_BASE(67, 67, 3, 0x0050, 0x10, 19, 1),
1328 + PIN_FIELD_BASE(68, 68, 3, 0x0050, 0x10, 15, 1),
1329 + PIN_FIELD_BASE(69, 69, 3, 0x0050, 0x10, 8, 1),
1330 + PIN_FIELD_BASE(70, 70, 3, 0x0050, 0x10, 7, 1),
1331 + PIN_FIELD_BASE(71, 71, 3, 0x0050, 0x10, 6, 1),
1332 + PIN_FIELD_BASE(72, 72, 3, 0x0050, 0x10, 5, 1),
1333 + PIN_FIELD_BASE(73, 73, 3, 0x0050, 0x10, 4, 1),
1334 + PIN_FIELD_BASE(74, 74, 3, 0x0050, 0x10, 3, 1),
1335 + PIN_FIELD_BASE(75, 75, 3, 0x0050, 0x10, 2, 1),
1336 + PIN_FIELD_BASE(76, 76, 3, 0x0050, 0x10, 1, 1),
1337 + PIN_FIELD_BASE(77, 77, 3, 0x0050, 0x10, 0, 1),
1338 + PIN_FIELD_BASE(78, 78, 3, 0x0050, 0x10, 9, 1),
1339 + PIN_FIELD_BASE(79, 79, 3, 0x0050, 0x10, 11, 1),
1340 + PIN_FIELD_BASE(80, 80, 3, 0x0050, 0x10, 10, 1),
1341 + PIN_FIELD_BASE(81, 81, 3, 0x0050, 0x10, 25, 1),
1342 + PIN_FIELD_BASE(82, 82, 3, 0x0050, 0x10, 24, 1),
1343 + PIN_FIELD_BASE(83, 83, 3, 0x0050, 0x10, 22, 1),
1344 + PIN_FIELD_BASE(84, 84, 3, 0x0050, 0x10, 23, 1),
1345 + PIN_FIELD_BASE(85, 85, 7, 0x0090, 0x10, 1, 1),
1346 + PIN_FIELD_BASE(86, 86, 7, 0x0080, 0x10, 29, 1),
1347 + PIN_FIELD_BASE(87, 87, 7, 0x0080, 0x10, 7, 1),
1348 + PIN_FIELD_BASE(88, 88, 7, 0x0080, 0x10, 6, 1),
1349 + PIN_FIELD_BASE(89, 89, 2, 0x0060, 0x10, 21, 1),
1350 + PINS_FIELD_BASE(90, 94, 3, 0x0050, 0x10, 21, 1),
1351 + PIN_FIELD_BASE(95, 95, 2, 0x0060, 0x10, 22, 1),
1352 + PIN_FIELD_BASE(96, 96, 2, 0x0060, 0x10, 23, 1),
1353 + PIN_FIELD_BASE(97, 97, 2, 0x0060, 0x10, 2, 1),
1354 + PIN_FIELD_BASE(98, 98, 2, 0x0060, 0x10, 3, 1),
1355 + PIN_FIELD_BASE(99, 99, 2, 0x0060, 0x10, 0, 1),
1356 + PIN_FIELD_BASE(100, 100, 2, 0x0060, 0x10, 1, 1),
1357 + PIN_FIELD_BASE(101, 101, 2, 0x0060, 0x10, 4, 1),
1358 + PIN_FIELD_BASE(102, 102, 2, 0x0060, 0x10, 5, 1),
1359 + PIN_FIELD_BASE(103, 103, 2, 0x0060, 0x10, 17, 1),
1360 + PIN_FIELD_BASE(104, 104, 2, 0x0060, 0x10, 19, 1),
1361 + PIN_FIELD_BASE(105, 105, 2, 0x0060, 0x10, 18, 1),
1362 + PIN_FIELD_BASE(106, 106, 2, 0x0060, 0x10, 20, 1),
1363 + PIN_FIELD_BASE(107, 107, 1, 0x0050, 0x10, 4, 1),
1364 + PIN_FIELD_BASE(108, 108, 1, 0x0050, 0x10, 3, 1),
1365 + PIN_FIELD_BASE(109, 109, 1, 0x0050, 0x10, 5, 1),
1366 + PIN_FIELD_BASE(110, 110, 1, 0x0050, 0x10, 0, 1),
1367 + PIN_FIELD_BASE(111, 111, 1, 0x0050, 0x10, 1, 1),
1368 + PIN_FIELD_BASE(112, 112, 1, 0x0050, 0x10, 2, 1),
1369 + PIN_FIELD_BASE(113, 113, 1, 0x0050, 0x10, 9, 1),
1370 + PIN_FIELD_BASE(114, 114, 1, 0x0050, 0x10, 10, 1),
1371 + PIN_FIELD_BASE(115, 115, 1, 0x0050, 0x10, 6, 1),
1372 + PIN_FIELD_BASE(116, 116, 1, 0x0050, 0x10, 7, 1),
1373 + PIN_FIELD_BASE(117, 117, 1, 0x0050, 0x10, 12, 1),
1374 + PIN_FIELD_BASE(118, 118, 1, 0x0050, 0x10, 13, 1),
1375 + PIN_FIELD_BASE(119, 119, 1, 0x0050, 0x10, 14, 1),
1376 + PIN_FIELD_BASE(120, 120, 1, 0x0050, 0x10, 11, 1),
1377 + PINS_FIELD_BASE(121, 133, 1, 0x0050, 0x10, 8, 1),
1378 + PIN_FIELD_BASE(134, 134, 5, 0x0040, 0x10, 14, 1),
1379 + PIN_FIELD_BASE(135, 135, 5, 0x0040, 0x10, 19, 1),
1380 + PIN_FIELD_BASE(136, 136, 5, 0x0040, 0x10, 1, 1),
1381 + PIN_FIELD_BASE(137, 137, 5, 0x0040, 0x10, 7, 1),
1382 + PIN_FIELD_BASE(138, 138, 5, 0x0040, 0x10, 4, 1),
1383 + PIN_FIELD_BASE(139, 139, 5, 0x0040, 0x10, 5, 1),
1384 + PIN_FIELD_BASE(140, 140, 5, 0x0040, 0x10, 0, 1),
1385 + PIN_FIELD_BASE(141, 141, 5, 0x0040, 0x10, 6, 1),
1386 + PIN_FIELD_BASE(142, 142, 5, 0x0040, 0x10, 2, 1),
1387 + PIN_FIELD_BASE(143, 143, 5, 0x0040, 0x10, 3, 1),
1388 + PIN_FIELD_BASE(144, 144, 5, 0x0040, 0x10, 12, 1),
1389 + PIN_FIELD_BASE(145, 145, 5, 0x0040, 0x10, 11, 1),
1390 + PIN_FIELD_BASE(146, 146, 5, 0x0040, 0x10, 13, 1),
1391 + PIN_FIELD_BASE(147, 147, 5, 0x0040, 0x10, 10, 1),
1392 + PIN_FIELD_BASE(148, 148, 5, 0x0040, 0x10, 15, 1),
1393 + PIN_FIELD_BASE(149, 149, 5, 0x0040, 0x10, 16, 1),
1394 + PIN_FIELD_BASE(150, 150, 7, 0x0080, 0x10, 23, 1),
1395 + PIN_FIELD_BASE(151, 151, 7, 0x0080, 0x10, 24, 1),
1396 + PIN_FIELD_BASE(152, 152, 7, 0x0080, 0x10, 25, 1),
1397 + PIN_FIELD_BASE(153, 153, 7, 0x0080, 0x10, 26, 1),
1398 + PIN_FIELD_BASE(154, 154, 7, 0x0080, 0x10, 28, 1),
1399 + PIN_FIELD_BASE(155, 155, 3, 0x0050, 0x10, 28, 1),
1400 + PIN_FIELD_BASE(156, 156, 3, 0x0050, 0x10, 27, 1),
1401 + PIN_FIELD_BASE(157, 157, 3, 0x0050, 0x10, 29, 1),
1402 + PIN_FIELD_BASE(158, 158, 3, 0x0050, 0x10, 26, 1),
1403 + PIN_FIELD_BASE(159, 159, 7, 0x0080, 0x10, 27, 1),
1404 + PIN_FIELD_BASE(160, 160, 5, 0x0040, 0x10, 8, 1),
1405 + PIN_FIELD_BASE(161, 161, 1, 0x0050, 0x10, 15, 1),
1406 + PIN_FIELD_BASE(162, 162, 1, 0x0050, 0x10, 16, 1),
1407 + PIN_FIELD_BASE(163, 163, 4, 0x0040, 0x10, 0, 1),
1408 + PIN_FIELD_BASE(164, 164, 4, 0x0040, 0x10, 1, 1),
1409 + PIN_FIELD_BASE(165, 165, 4, 0x0040, 0x10, 2, 1),
1410 + PIN_FIELD_BASE(166, 166, 4, 0x0040, 0x10, 3, 1),
1411 + PIN_FIELD_BASE(167, 167, 4, 0x0040, 0x10, 4, 1),
1412 + PIN_FIELD_BASE(168, 168, 4, 0x0040, 0x10, 5, 1),
1413 + PIN_FIELD_BASE(169, 169, 4, 0x0040, 0x10, 6, 1),
1414 + PIN_FIELD_BASE(170, 170, 4, 0x0040, 0x10, 7, 1),
1415 + PIN_FIELD_BASE(171, 171, 7, 0x0080, 0x10, 17, 1),
1416 + PIN_FIELD_BASE(172, 172, 7, 0x0080, 0x10, 18, 1),
1417 + PIN_FIELD_BASE(173, 173, 7, 0x0080, 0x10, 11, 1),
1418 + PIN_FIELD_BASE(174, 174, 7, 0x0080, 0x10, 12, 1),
1419 + PIN_FIELD_BASE(175, 175, 7, 0x0080, 0x10, 13, 1),
1420 + PIN_FIELD_BASE(176, 176, 7, 0x0080, 0x10, 14, 1),
1421 + PIN_FIELD_BASE(177, 177, 7, 0x0080, 0x10, 15, 1),
1422 + PINS_FIELD_BASE(178, 179, 7, 0x0080, 0x10, 16, 1),
1423 +};
1424 +
1425 +static const struct mtk_pin_field_calc mt6765_pin_tdsel_range[] = {
1426 + PINS_FIELD_BASE(0, 3, 2, 0x00c0, 0x10, 16, 4),
1427 + PINS_FIELD_BASE(4, 7, 2, 0x00c0, 0x10, 20, 4),
1428 + PIN_FIELD_BASE(8, 8, 3, 0x0090, 0x10, 12, 4),
1429 + PINS_FIELD_BASE(9, 11, 2, 0x00c0, 0x10, 24, 4),
1430 + PIN_FIELD_BASE(12, 12, 5, 0x0080, 0x10, 4, 4),
1431 + PINS_FIELD_BASE(13, 16, 6, 0x00e0, 0x10, 8, 4),
1432 + PINS_FIELD_BASE(17, 20, 6, 0x00e0, 0x10, 0, 4),
1433 + PINS_FIELD_BASE(21, 24, 6, 0x00e0, 0x10, 4, 4),
1434 + PINS_FIELD_BASE(25, 28, 6, 0x00d0, 0x10, 28, 4),
1435 + PIN_FIELD_BASE(29, 29, 6, 0x00d0, 0x10, 0, 4),
1436 + PIN_FIELD_BASE(30, 30, 6, 0x00d0, 0x10, 4, 4),
1437 + PINS_FIELD_BASE(31, 34, 6, 0x00d0, 0x10, 8, 4),
1438 + PINS_FIELD_BASE(35, 36, 6, 0x00d0, 0x10, 20, 4),
1439 + PIN_FIELD_BASE(37, 37, 6, 0x00d0, 0x10, 24, 4),
1440 + PIN_FIELD_BASE(38, 38, 6, 0x00d0, 0x10, 16, 4),
1441 + PINS_FIELD_BASE(39, 40, 6, 0x00d0, 0x10, 12, 4),
1442 + PINS_FIELD_BASE(41, 42, 7, 0x00d0, 0x10, 24, 4),
1443 + PIN_FIELD_BASE(43, 43, 7, 0x00d0, 0x10, 12, 4),
1444 + PIN_FIELD_BASE(44, 44, 7, 0x00d0, 0x10, 16, 4),
1445 + PIN_FIELD_BASE(45, 45, 7, 0x00e0, 0x10, 0, 4),
1446 + PINS_FIELD_BASE(46, 47, 7, 0x00d0, 0x10, 28, 4),
1447 + PINS_FIELD_BASE(48, 49, 7, 0x00e0, 0x10, 28, 4),
1448 + PINS_FIELD_BASE(50, 51, 7, 0x00e0, 0x10, 24, 4),
1449 + PINS_FIELD_BASE(52, 57, 7, 0x00d0, 0x10, 0, 4),
1450 + PINS_FIELD_BASE(58, 60, 7, 0x00e0, 0x10, 16, 4),
1451 + PINS_FIELD_BASE(61, 62, 3, 0x0090, 0x10, 20, 4),
1452 + PINS_FIELD_BASE(63, 64, 3, 0x0090, 0x10, 16, 4),
1453 + PINS_FIELD_BASE(65, 66, 3, 0x0090, 0x10, 28, 4),
1454 + PINS_FIELD_BASE(67, 68, 3, 0x0090, 0x10, 24, 4),
1455 + PINS_FIELD_BASE(69, 73, 3, 0x0090, 0x10, 4, 4),
1456 + PINS_FIELD_BASE(74, 78, 3, 0x0090, 0x10, 8, 4),
1457 + PINS_FIELD_BASE(79, 80, 3, 0x0090, 0x10, 0, 4),
1458 + PIN_FIELD_BASE(81, 81, 3, 0x00a0, 0x10, 8, 4),
1459 + PINS_FIELD_BASE(82, 83, 3, 0x00a0, 0x10, 4, 4),
1460 + PIN_FIELD_BASE(84, 84, 3, 0x00a0, 0x10, 8, 4),
1461 + PIN_FIELD_BASE(85, 85, 7, 0x00e0, 0x10, 16, 4),
1462 + PIN_FIELD_BASE(86, 86, 7, 0x00e0, 0x10, 20, 4),
1463 + PIN_FIELD_BASE(87, 87, 7, 0x00d0, 0x10, 8, 4),
1464 + PIN_FIELD_BASE(88, 88, 7, 0x00d0, 0x10, 4, 4),
1465 + PIN_FIELD_BASE(89, 89, 2, 0x00d0, 0x10, 12, 4),
1466 + PIN_FIELD_BASE(90, 90, 3, 0x00a0, 0x10, 0, 4),
1467 + PINS_FIELD_BASE(91, 92, 2, 0x00d0, 0x10, 0, 4),
1468 + PINS_FIELD_BASE(93, 94, 2, 0x00c0, 0x10, 28, 4),
1469 + PINS_FIELD_BASE(95, 96, 2, 0x00d0, 0x10, 16, 4),
1470 + PINS_FIELD_BASE(97, 98, 2, 0x00c0, 0x10, 8, 4),
1471 + PIN_FIELD_BASE(99, 99, 2, 0x00c0, 0x10, 0, 4),
1472 + PIN_FIELD_BASE(100, 100, 2, 0x00c0, 0x10, 4, 4),
1473 + PINS_FIELD_BASE(101, 102, 2, 0x00c0, 0x10, 12, 4),
1474 + PINS_FIELD_BASE(103, 104, 2, 0x00d0, 0x10, 4, 4),
1475 + PINS_FIELD_BASE(105, 106, 2, 0x00d0, 0x10, 8, 4),
1476 + PIN_FIELD_BASE(107, 107, 1, 0x0090, 0x10, 16, 4),
1477 + PIN_FIELD_BASE(108, 108, 1, 0x0090, 0x10, 12, 4),
1478 + PIN_FIELD_BASE(109, 109, 1, 0x0090, 0x10, 20, 4),
1479 + PIN_FIELD_BASE(110, 110, 1, 0x0090, 0x10, 0, 4),
1480 + PIN_FIELD_BASE(111, 111, 1, 0x0090, 0x10, 4, 4),
1481 + PIN_FIELD_BASE(112, 112, 1, 0x0090, 0x10, 8, 4),
1482 + PIN_FIELD_BASE(113, 113, 1, 0x00a0, 0x10, 4, 4),
1483 + PIN_FIELD_BASE(114, 114, 1, 0x00a0, 0x10, 8, 4),
1484 + PIN_FIELD_BASE(115, 115, 1, 0x0090, 0x10, 24, 4),
1485 + PIN_FIELD_BASE(116, 116, 1, 0x0090, 0x10, 28, 4),
1486 + PIN_FIELD_BASE(117, 117, 1, 0x00a0, 0x10, 16, 4),
1487 + PIN_FIELD_BASE(118, 118, 1, 0x00a0, 0x10, 20, 4),
1488 + PIN_FIELD_BASE(119, 119, 1, 0x00a0, 0x10, 24, 4),
1489 + PIN_FIELD_BASE(120, 120, 1, 0x00a0, 0x10, 12, 4),
1490 + PIN_FIELD_BASE(121, 121, 1, 0x00a0, 0x10, 0, 4),
1491 + PIN_FIELD_BASE(122, 122, 4, 0x0090, 0x10, 8, 4),
1492 + PIN_FIELD_BASE(123, 123, 4, 0x0090, 0x10, 12, 4),
1493 + PIN_FIELD_BASE(124, 124, 4, 0x0090, 0x10, 4, 4),
1494 + PINS_FIELD_BASE(125, 130, 4, 0x0090, 0x10, 12, 4),
1495 + PIN_FIELD_BASE(131, 131, 4, 0x0090, 0x10, 16, 4),
1496 + PIN_FIELD_BASE(132, 132, 4, 0x0090, 0x10, 12, 4),
1497 + PIN_FIELD_BASE(133, 133, 4, 0x0090, 0x10, 20, 4),
1498 + PIN_FIELD_BASE(134, 134, 5, 0x0080, 0x10, 12, 4),
1499 + PIN_FIELD_BASE(135, 135, 5, 0x0080, 0x10, 20, 4),
1500 + PIN_FIELD_BASE(136, 136, 5, 0x0070, 0x10, 4, 4),
1501 + PIN_FIELD_BASE(137, 137, 5, 0x0070, 0x10, 28, 4),
1502 + PIN_FIELD_BASE(138, 138, 5, 0x0070, 0x10, 16, 4),
1503 + PIN_FIELD_BASE(139, 139, 5, 0x0070, 0x10, 20, 4),
1504 + PIN_FIELD_BASE(140, 140, 5, 0x0070, 0x10, 0, 4),
1505 + PIN_FIELD_BASE(141, 141, 5, 0x0070, 0x10, 24, 4),
1506 + PIN_FIELD_BASE(142, 142, 5, 0x0070, 0x10, 8, 4),
1507 + PIN_FIELD_BASE(143, 143, 5, 0x0070, 0x10, 12, 4),
1508 + PINS_FIELD_BASE(144, 147, 5, 0x0080, 0x10, 8, 4),
1509 + PINS_FIELD_BASE(148, 149, 5, 0x0080, 0x10, 16, 4),
1510 + PINS_FIELD_BASE(150, 151, 7, 0x00e0, 0x10, 4, 4),
1511 + PINS_FIELD_BASE(152, 153, 7, 0x00e0, 0x10, 8, 4),
1512 + PIN_FIELD_BASE(154, 154, 7, 0x00e0, 0x10, 12, 4),
1513 + PINS_FIELD_BASE(155, 158, 3, 0x00a0, 0x10, 12, 4),
1514 + PIN_FIELD_BASE(159, 159, 7, 0x00e0, 0x10, 12, 4),
1515 + PIN_FIELD_BASE(160, 160, 5, 0x0080, 0x10, 0, 4),
1516 + PINS_FIELD_BASE(161, 162, 1, 0x00a0, 0x10, 28, 4),
1517 + PINS_FIELD_BASE(163, 170, 4, 0x0090, 0x10, 0, 4),
1518 + PINS_FIELD_BASE(171, 179, 7, 0x00d0, 0x10, 20, 4),
1519 +};
1520 +
1521 +static const struct mtk_pin_field_calc mt6765_pin_rdsel_range[] = {
1522 + PINS_FIELD_BASE(0, 3, 2, 0x0090, 0x10, 8, 2),
1523 + PINS_FIELD_BASE(4, 7, 2, 0x0090, 0x10, 10, 2),
1524 + PIN_FIELD_BASE(8, 8, 3, 0x0060, 0x10, 6, 2),
1525 + PINS_FIELD_BASE(9, 11, 2, 0x0090, 0x10, 12, 2),
1526 + PIN_FIELD_BASE(12, 12, 5, 0x0050, 0x10, 18, 2),
1527 + PINS_FIELD_BASE(13, 16, 6, 0x00a0, 0x10, 18, 2),
1528 + PINS_FIELD_BASE(17, 20, 6, 0x00a0, 0x10, 14, 2),
1529 + PINS_FIELD_BASE(21, 24, 6, 0x00a0, 0x10, 16, 2),
1530 + PINS_FIELD_BASE(25, 28, 6, 0x00a0, 0x10, 12, 2),
1531 + PIN_FIELD_BASE(29, 29, 6, 0x0090, 0x10, 0, 6),
1532 + PIN_FIELD_BASE(30, 30, 6, 0x0090, 0x10, 6, 6),
1533 + PINS_FIELD_BASE(31, 34, 6, 0x0090, 0x10, 12, 6),
1534 + PINS_FIELD_BASE(35, 36, 6, 0x00a0, 0x10, 0, 6),
1535 + PIN_FIELD_BASE(37, 37, 6, 0x00a0, 0x10, 6, 6),
1536 + PIN_FIELD_BASE(38, 38, 6, 0x0090, 0x10, 24, 6),
1537 + PINS_FIELD_BASE(39, 40, 6, 0x0090, 0x10, 18, 6),
1538 + PINS_FIELD_BASE(41, 42, 7, 0x00a0, 0x10, 12, 2),
1539 + PIN_FIELD_BASE(43, 43, 7, 0x00a0, 0x10, 6, 2),
1540 + PIN_FIELD_BASE(44, 44, 7, 0x00a0, 0x10, 8, 2),
1541 + PIN_FIELD_BASE(45, 45, 7, 0x00a0, 0x10, 16, 2),
1542 + PINS_FIELD_BASE(46, 47, 7, 0x00a0, 0x10, 14, 2),
1543 + PINS_FIELD_BASE(48, 49, 7, 0x00a0, 0x10, 30, 2),
1544 + PINS_FIELD_BASE(50, 51, 7, 0x00a0, 0x10, 28, 2),
1545 + PINS_FIELD_BASE(52, 57, 7, 0x00a0, 0x10, 0, 2),
1546 + PINS_FIELD_BASE(58, 60, 7, 0x00a0, 0x10, 24, 2),
1547 + PINS_FIELD_BASE(61, 62, 3, 0x0060, 0x10, 10, 2),
1548 + PINS_FIELD_BASE(63, 64, 3, 0x0060, 0x10, 8, 2),
1549 + PINS_FIELD_BASE(65, 66, 3, 0x0060, 0x10, 14, 2),
1550 + PINS_FIELD_BASE(67, 68, 3, 0x0060, 0x10, 12, 2),
1551 + PINS_FIELD_BASE(69, 73, 3, 0x0060, 0x10, 2, 2),
1552 + PINS_FIELD_BASE(74, 78, 3, 0x0060, 0x10, 4, 2),
1553 + PINS_FIELD_BASE(79, 80, 3, 0x0060, 0x10, 0, 2),
1554 + PIN_FIELD_BASE(81, 81, 3, 0x0060, 0x10, 20, 2),
1555 + PINS_FIELD_BASE(82, 83, 3, 0x0060, 0x10, 18, 2),
1556 + PIN_FIELD_BASE(84, 84, 3, 0x0060, 0x10, 20, 2),
1557 + PIN_FIELD_BASE(85, 85, 7, 0x00a0, 0x10, 24, 2),
1558 + PIN_FIELD_BASE(86, 86, 7, 0x00a0, 0x10, 26, 2),
1559 + PIN_FIELD_BASE(87, 87, 7, 0x00a0, 0x10, 4, 2),
1560 + PIN_FIELD_BASE(88, 88, 7, 0x00a0, 0x10, 2, 2),
1561 + PIN_FIELD_BASE(89, 89, 2, 0x0090, 0x10, 22, 2),
1562 + PIN_FIELD_BASE(90, 90, 3, 0x0060, 0x10, 16, 2),
1563 + PINS_FIELD_BASE(91, 92, 2, 0x0090, 0x10, 16, 2),
1564 + PINS_FIELD_BASE(93, 94, 2, 0x0090, 0x10, 14, 2),
1565 + PINS_FIELD_BASE(95, 96, 2, 0x0090, 0x10, 24, 2),
1566 + PINS_FIELD_BASE(97, 98, 2, 0x0090, 0x10, 4, 2),
1567 + PIN_FIELD_BASE(99, 99, 2, 0x0090, 0x10, 0, 2),
1568 + PIN_FIELD_BASE(100, 100, 2, 0x0090, 0x10, 2, 2),
1569 + PINS_FIELD_BASE(101, 102, 2, 0x0090, 0x10, 6, 2),
1570 + PINS_FIELD_BASE(103, 104, 2, 0x0090, 0x10, 18, 2),
1571 + PINS_FIELD_BASE(105, 106, 2, 0x0090, 0x10, 20, 2),
1572 + PIN_FIELD_BASE(107, 107, 1, 0x0060, 0x10, 8, 2),
1573 + PIN_FIELD_BASE(108, 108, 1, 0x0060, 0x10, 6, 2),
1574 + PIN_FIELD_BASE(109, 109, 1, 0x0060, 0x10, 10, 2),
1575 + PIN_FIELD_BASE(110, 110, 1, 0x0060, 0x10, 0, 2),
1576 + PIN_FIELD_BASE(111, 111, 1, 0x0060, 0x10, 2, 2),
1577 + PIN_FIELD_BASE(112, 112, 1, 0x0060, 0x10, 4, 2),
1578 + PIN_FIELD_BASE(113, 113, 1, 0x0060, 0x10, 18, 2),
1579 + PIN_FIELD_BASE(114, 114, 1, 0x0060, 0x10, 20, 2),
1580 + PIN_FIELD_BASE(115, 115, 1, 0x0060, 0x10, 12, 2),
1581 + PIN_FIELD_BASE(116, 116, 1, 0x0060, 0x10, 14, 2),
1582 + PIN_FIELD_BASE(117, 117, 1, 0x0060, 0x10, 24, 2),
1583 + PIN_FIELD_BASE(118, 118, 1, 0x0060, 0x10, 26, 2),
1584 + PIN_FIELD_BASE(119, 119, 1, 0x0060, 0x10, 28, 2),
1585 + PIN_FIELD_BASE(120, 120, 1, 0x0060, 0x10, 22, 2),
1586 + PIN_FIELD_BASE(121, 121, 1, 0x0060, 0x10, 16, 2),
1587 + PIN_FIELD_BASE(122, 122, 4, 0x0070, 0x10, 8, 6),
1588 + PIN_FIELD_BASE(123, 123, 4, 0x0070, 0x10, 14, 6),
1589 + PIN_FIELD_BASE(124, 124, 4, 0x0070, 0x10, 2, 6),
1590 + PINS_FIELD_BASE(125, 130, 4, 0x0070, 0x10, 14, 6),
1591 + PIN_FIELD_BASE(131, 131, 4, 0x0070, 0x10, 20, 6),
1592 + PIN_FIELD_BASE(132, 132, 4, 0x0070, 0x10, 14, 6),
1593 + PIN_FIELD_BASE(133, 133, 4, 0x0070, 0x10, 26, 6),
1594 + PIN_FIELD_BASE(134, 134, 5, 0x0050, 0x10, 22, 2),
1595 + PIN_FIELD_BASE(135, 135, 5, 0x0050, 0x10, 30, 2),
1596 + PIN_FIELD_BASE(136, 136, 5, 0x0050, 0x10, 2, 2),
1597 + PIN_FIELD_BASE(137, 137, 5, 0x0050, 0x10, 14, 2),
1598 + PIN_FIELD_BASE(138, 138, 5, 0x0050, 0x10, 8, 2),
1599 + PIN_FIELD_BASE(139, 139, 5, 0x0050, 0x10, 10, 2),
1600 + PIN_FIELD_BASE(140, 140, 5, 0x0050, 0x10, 0, 2),
1601 + PIN_FIELD_BASE(141, 141, 5, 0x0050, 0x10, 12, 2),
1602 + PIN_FIELD_BASE(142, 142, 5, 0x0050, 0x10, 4, 2),
1603 + PIN_FIELD_BASE(143, 143, 5, 0x0050, 0x10, 6, 2),
1604 + PINS_FIELD_BASE(144, 147, 5, 0x0050, 0x10, 20, 2),
1605 + PINS_FIELD_BASE(148, 149, 5, 0x0050, 0x10, 24, 2),
1606 + PINS_FIELD_BASE(150, 151, 7, 0x00a0, 0x10, 18, 2),
1607 + PINS_FIELD_BASE(152, 153, 7, 0x00a0, 0x10, 20, 2),
1608 + PIN_FIELD_BASE(154, 154, 7, 0x00a0, 0x10, 22, 2),
1609 + PINS_FIELD_BASE(155, 158, 3, 0x0060, 0x10, 22, 2),
1610 + PIN_FIELD_BASE(159, 159, 7, 0x00a0, 0x10, 22, 2),
1611 + PIN_FIELD_BASE(160, 160, 5, 0x0050, 0x10, 16, 2),
1612 + PINS_FIELD_BASE(161, 162, 1, 0x0060, 0x10, 30, 2),
1613 + PINS_FIELD_BASE(163, 170, 4, 0x0070, 0x10, 0, 2),
1614 + PINS_FIELD_BASE(171, 179, 7, 0x00a0, 0x10, 10, 2),
1615 +};
1616 +
1617 +static const struct mtk_pin_field_calc mt6765_pin_drv_range[] = {
1618 + PINS_FIELD_BASE(0, 2, 2, 0x0000, 0x10, 12, 3),
1619 + PIN_FIELD_BASE(3, 3, 2, 0x0000, 0x10, 15, 3),
1620 + PINS_FIELD_BASE(4, 6, 2, 0x0000, 0x10, 18, 3),
1621 + PIN_FIELD_BASE(7, 7, 2, 0x0000, 0x10, 21, 3),
1622 + PIN_FIELD_BASE(8, 8, 3, 0x0000, 0x10, 9, 3),
1623 + PINS_FIELD_BASE(9, 11, 2, 0x0000, 0x10, 24, 3),
1624 + PIN_FIELD_BASE(12, 12, 5, 0x0000, 0x10, 27, 3),
1625 + PINS_FIELD_BASE(13, 15, 6, 0x0010, 0x10, 3, 3),
1626 + PIN_FIELD_BASE(16, 16, 6, 0x0010, 0x10, 6, 3),
1627 + PIN_FIELD_BASE(17, 17, 6, 0x0000, 0x10, 23, 3),
1628 + PIN_FIELD_BASE(18, 18, 6, 0x0000, 0x10, 26, 3),
1629 + PINS_FIELD_BASE(19, 20, 6, 0x0000, 0x10, 23, 3),
1630 + PINS_FIELD_BASE(21, 23, 6, 0x0000, 0x10, 29, 3),
1631 + PIN_FIELD_BASE(24, 24, 6, 0x0010, 0x10, 0, 3),
1632 + PINS_FIELD_BASE(25, 27, 6, 0x0000, 0x10, 17, 3),
1633 + PIN_FIELD_BASE(28, 28, 6, 0x0000, 0x10, 20, 3),
1634 + PIN_FIELD_BASE(29, 29, 6, 0x0000, 0x10, 0, 3),
1635 + PIN_FIELD_BASE(30, 30, 6, 0x0000, 0x10, 3, 3),
1636 + PINS_FIELD_BASE(31, 34, 6, 0x0000, 0x10, 6, 3),
1637 + PINS_FIELD_BASE(35, 36, 6, 0x0000, 0x10, 13, 2),
1638 + PIN_FIELD_BASE(37, 37, 6, 0x0000, 0x10, 15, 2),
1639 + PIN_FIELD_BASE(38, 38, 6, 0x0000, 0x10, 11, 2),
1640 + PINS_FIELD_BASE(39, 40, 6, 0x0000, 0x10, 9, 2),
1641 + PINS_FIELD_BASE(41, 42, 7, 0x0000, 0x10, 21, 3),
1642 + PIN_FIELD_BASE(43, 43, 7, 0x0000, 0x10, 9, 3),
1643 + PIN_FIELD_BASE(44, 44, 7, 0x0000, 0x10, 12, 3),
1644 + PIN_FIELD_BASE(45, 45, 7, 0x0000, 0x10, 27, 3),
1645 + PINS_FIELD_BASE(46, 47, 7, 0x0000, 0x10, 24, 3),
1646 + PINS_FIELD_BASE(48, 49, 7, 0x0010, 0x10, 18, 3),
1647 + PINS_FIELD_BASE(50, 51, 7, 0x0010, 0x10, 15, 3),
1648 + PINS_FIELD_BASE(52, 57, 7, 0x0000, 0x10, 0, 3),
1649 + PINS_FIELD_BASE(58, 60, 7, 0x0010, 0x10, 9, 3),
1650 + PINS_FIELD_BASE(61, 62, 3, 0x0000, 0x10, 15, 3),
1651 + PINS_FIELD_BASE(63, 64, 3, 0x0000, 0x10, 12, 3),
1652 + PINS_FIELD_BASE(65, 66, 3, 0x0000, 0x10, 21, 3),
1653 + PINS_FIELD_BASE(67, 68, 3, 0x0000, 0x10, 18, 3),
1654 + PINS_FIELD_BASE(69, 73, 3, 0x0000, 0x10, 3, 3),
1655 + PINS_FIELD_BASE(74, 78, 3, 0x0000, 0x10, 6, 3),
1656 + PINS_FIELD_BASE(79, 80, 3, 0x0000, 0x10, 0, 3),
1657 + PIN_FIELD_BASE(81, 81, 3, 0x0010, 0x10, 0, 3),
1658 + PINS_FIELD_BASE(82, 83, 3, 0x0000, 0x10, 27, 3),
1659 + PIN_FIELD_BASE(84, 84, 3, 0x0010, 0x10, 0, 3),
1660 + PIN_FIELD_BASE(85, 85, 7, 0x0010, 0x10, 9, 3),
1661 + PIN_FIELD_BASE(86, 86, 7, 0x0010, 0x10, 12, 3),
1662 + PIN_FIELD_BASE(87, 87, 7, 0x0000, 0x10, 6, 3),
1663 + PIN_FIELD_BASE(88, 88, 7, 0x0000, 0x10, 3, 3),
1664 + PIN_FIELD_BASE(89, 89, 2, 0x0010, 0x10, 15, 3),
1665 + PIN_FIELD_BASE(90, 90, 3, 0x0000, 0x10, 24, 3),
1666 + PIN_FIELD_BASE(91, 91, 2, 0x0010, 0x10, 6, 3),
1667 + PIN_FIELD_BASE(92, 92, 2, 0x0010, 0x10, 3, 3),
1668 + PIN_FIELD_BASE(93, 93, 2, 0x0000, 0x10, 27, 3),
1669 + PIN_FIELD_BASE(94, 94, 2, 0x0010, 0x10, 0, 3),
1670 + PINS_FIELD_BASE(95, 96, 2, 0x0010, 0x10, 18, 3),
1671 + PINS_FIELD_BASE(97, 98, 2, 0x0000, 0x10, 6, 3),
1672 + PIN_FIELD_BASE(99, 99, 2, 0x0000, 0x10, 0, 3),
1673 + PIN_FIELD_BASE(100, 100, 2, 0x0000, 0x10, 3, 3),
1674 + PINS_FIELD_BASE(101, 102, 2, 0x0000, 0x10, 9, 3),
1675 + PINS_FIELD_BASE(103, 104, 2, 0x0010, 0x10, 9, 3),
1676 + PINS_FIELD_BASE(105, 106, 2, 0x0010, 0x10, 12, 3),
1677 + PIN_FIELD_BASE(107, 107, 1, 0x0000, 0x10, 12, 3),
1678 + PIN_FIELD_BASE(108, 108, 1, 0x0000, 0x10, 9, 3),
1679 + PIN_FIELD_BASE(109, 109, 1, 0x0000, 0x10, 15, 3),
1680 + PIN_FIELD_BASE(110, 110, 1, 0x0000, 0x10, 0, 3),
1681 + PIN_FIELD_BASE(111, 111, 1, 0x0000, 0x10, 3, 3),
1682 + PIN_FIELD_BASE(112, 112, 1, 0x0000, 0x10, 6, 3),
1683 + PIN_FIELD_BASE(113, 113, 1, 0x0000, 0x10, 27, 3),
1684 + PIN_FIELD_BASE(114, 114, 1, 0x0010, 0x10, 0, 3),
1685 + PIN_FIELD_BASE(115, 115, 1, 0x0000, 0x10, 18, 3),
1686 + PIN_FIELD_BASE(116, 116, 1, 0x0000, 0x10, 21, 3),
1687 + PIN_FIELD_BASE(117, 117, 1, 0x0010, 0x10, 6, 3),
1688 + PIN_FIELD_BASE(118, 118, 1, 0x0010, 0x10, 9, 3),
1689 + PIN_FIELD_BASE(119, 119, 1, 0x0010, 0x10, 12, 3),
1690 + PIN_FIELD_BASE(120, 120, 1, 0x0010, 0x10, 3, 3),
1691 + PIN_FIELD_BASE(121, 121, 1, 0x0000, 0x10, 24, 3),
1692 + PIN_FIELD_BASE(122, 122, 4, 0x0000, 0x10, 9, 3),
1693 + PIN_FIELD_BASE(123, 123, 4, 0x0000, 0x10, 12, 3),
1694 + PIN_FIELD_BASE(124, 124, 4, 0x0000, 0x10, 6, 3),
1695 + PINS_FIELD_BASE(125, 130, 4, 0x0000, 0x10, 12, 3),
1696 + PIN_FIELD_BASE(131, 131, 4, 0x0000, 0x10, 15, 3),
1697 + PIN_FIELD_BASE(132, 132, 4, 0x0000, 0x10, 12, 3),
1698 + PIN_FIELD_BASE(133, 133, 4, 0x0000, 0x10, 18, 3),
1699 + PIN_FIELD_BASE(134, 134, 5, 0x0010, 0x10, 6, 3),
1700 + PIN_FIELD_BASE(135, 135, 5, 0x0010, 0x10, 12, 3),
1701 + PIN_FIELD_BASE(136, 136, 5, 0x0000, 0x10, 3, 3),
1702 + PIN_FIELD_BASE(137, 137, 5, 0x0000, 0x10, 21, 3),
1703 + PIN_FIELD_BASE(138, 138, 5, 0x0000, 0x10, 12, 3),
1704 + PIN_FIELD_BASE(139, 139, 5, 0x0000, 0x10, 15, 3),
1705 + PIN_FIELD_BASE(140, 140, 5, 0x0000, 0x10, 0, 3),
1706 + PIN_FIELD_BASE(141, 141, 5, 0x0000, 0x10, 18, 3),
1707 + PIN_FIELD_BASE(142, 142, 5, 0x0000, 0x10, 6, 3),
1708 + PIN_FIELD_BASE(143, 143, 5, 0x0000, 0x10, 9, 3),
1709 + PINS_FIELD_BASE(144, 146, 5, 0x0010, 0x10, 0, 3),
1710 + PIN_FIELD_BASE(147, 147, 5, 0x0010, 0x10, 3, 3),
1711 + PINS_FIELD_BASE(148, 149, 5, 0x0010, 0x10, 9, 3),
1712 + PINS_FIELD_BASE(150, 151, 7, 0x0010, 0x10, 0, 3),
1713 + PINS_FIELD_BASE(152, 153, 7, 0x0010, 0x10, 3, 3),
1714 + PIN_FIELD_BASE(154, 154, 7, 0x0010, 0x10, 6, 3),
1715 + PINS_FIELD_BASE(155, 157, 3, 0x0010, 0x10, 3, 3),
1716 + PIN_FIELD_BASE(158, 158, 3, 0x0010, 0x10, 6, 3),
1717 + PIN_FIELD_BASE(159, 159, 7, 0x0010, 0x10, 6, 3),
1718 + PIN_FIELD_BASE(160, 160, 5, 0x0000, 0x10, 24, 3),
1719 + PINS_FIELD_BASE(161, 162, 1, 0x0010, 0x10, 15, 3),
1720 + PINS_FIELD_BASE(163, 166, 4, 0x0000, 0x10, 0, 3),
1721 + PINS_FIELD_BASE(167, 170, 4, 0x0000, 0x10, 3, 3),
1722 + PINS_FIELD_BASE(171, 174, 7, 0x0000, 0x10, 18, 3),
1723 + PINS_FIELD_BASE(175, 179, 7, 0x0000, 0x10, 15, 3),
1724 +};
1725 +
1726 +static const struct mtk_pin_field_calc mt6765_pin_pupd_range[] = {
1727 + PINS_FIELD_BASE(0, 28, 0, 0x0050, 0x10, 18, 1),
1728 + PIN_FIELD_BASE(29, 29, 6, 0x0050, 0x10, 0, 1),
1729 + PIN_FIELD_BASE(30, 30, 6, 0x0050, 0x10, 1, 1),
1730 + PIN_FIELD_BASE(31, 31, 6, 0x0050, 0x10, 5, 1),
1731 + PIN_FIELD_BASE(32, 32, 6, 0x0050, 0x10, 2, 1),
1732 + PIN_FIELD_BASE(33, 33, 6, 0x0050, 0x10, 4, 1),
1733 + PIN_FIELD_BASE(34, 34, 6, 0x0050, 0x10, 3, 1),
1734 + PIN_FIELD_BASE(35, 35, 6, 0x0050, 0x10, 10, 1),
1735 + PIN_FIELD_BASE(36, 36, 6, 0x0050, 0x10, 11, 1),
1736 + PIN_FIELD_BASE(37, 37, 6, 0x0050, 0x10, 9, 1),
1737 + PIN_FIELD_BASE(38, 38, 6, 0x0050, 0x10, 6, 1),
1738 + PIN_FIELD_BASE(39, 39, 6, 0x0050, 0x10, 8, 1),
1739 + PINS_FIELD_BASE(40, 90, 6, 0x0050, 0x10, 7, 1),
1740 + PIN_FIELD_BASE(91, 91, 2, 0x0050, 0x10, 3, 1),
1741 + PIN_FIELD_BASE(92, 92, 2, 0x0050, 0x10, 2, 1),
1742 + PIN_FIELD_BASE(93, 93, 2, 0x0050, 0x10, 0, 1),
1743 + PINS_FIELD_BASE(94, 121, 2, 0x0050, 0x10, 1, 1),
1744 + PIN_FIELD_BASE(122, 122, 4, 0x0030, 0x10, 1, 1),
1745 + PIN_FIELD_BASE(123, 123, 4, 0x0030, 0x10, 2, 1),
1746 + PIN_FIELD_BASE(124, 124, 4, 0x0030, 0x10, 0, 1),
1747 + PIN_FIELD_BASE(125, 125, 4, 0x0030, 0x10, 4, 1),
1748 + PIN_FIELD_BASE(126, 126, 4, 0x0030, 0x10, 6, 1),
1749 + PIN_FIELD_BASE(127, 127, 4, 0x0030, 0x10, 8, 1),
1750 + PIN_FIELD_BASE(128, 128, 4, 0x0030, 0x10, 3, 1),
1751 + PIN_FIELD_BASE(129, 129, 4, 0x0030, 0x10, 7, 1),
1752 + PIN_FIELD_BASE(130, 130, 4, 0x0030, 0x10, 9, 1),
1753 + PIN_FIELD_BASE(131, 131, 4, 0x0030, 0x10, 10, 1),
1754 + PIN_FIELD_BASE(132, 132, 4, 0x0030, 0x10, 5, 1),
1755 + PINS_FIELD_BASE(133, 179, 4, 0x0030, 0x10, 11, 1),
1756 +};
1757 +
1758 +static const struct mtk_pin_field_calc mt6765_pin_r0_range[] = {
1759 + PINS_FIELD_BASE(0, 28, 4, 0x0030, 0x10, 11, 1),
1760 + PIN_FIELD_BASE(29, 29, 6, 0x0070, 0x10, 0, 1),
1761 + PIN_FIELD_BASE(30, 30, 6, 0x0070, 0x10, 1, 1),
1762 + PIN_FIELD_BASE(31, 31, 6, 0x0070, 0x10, 5, 1),
1763 + PIN_FIELD_BASE(32, 32, 6, 0x0070, 0x10, 2, 1),
1764 + PIN_FIELD_BASE(33, 33, 6, 0x0070, 0x10, 4, 1),
1765 + PIN_FIELD_BASE(34, 34, 6, 0x0070, 0x10, 3, 1),
1766 + PIN_FIELD_BASE(35, 35, 6, 0x0070, 0x10, 10, 1),
1767 + PIN_FIELD_BASE(36, 36, 6, 0x0070, 0x10, 11, 1),
1768 + PIN_FIELD_BASE(37, 37, 6, 0x0070, 0x10, 9, 1),
1769 + PIN_FIELD_BASE(38, 38, 6, 0x0070, 0x10, 6, 1),
1770 + PIN_FIELD_BASE(39, 39, 6, 0x0070, 0x10, 8, 1),
1771 + PINS_FIELD_BASE(40, 90, 6, 0x0070, 0x10, 7, 1),
1772 + PIN_FIELD_BASE(91, 91, 2, 0x0070, 0x10, 3, 1),
1773 + PIN_FIELD_BASE(92, 92, 2, 0x0070, 0x10, 2, 1),
1774 + PIN_FIELD_BASE(93, 93, 2, 0x0070, 0x10, 0, 1),
1775 + PINS_FIELD_BASE(94, 121, 2, 0x0070, 0x10, 1, 1),
1776 + PIN_FIELD_BASE(122, 122, 4, 0x0050, 0x10, 1, 1),
1777 + PIN_FIELD_BASE(123, 123, 4, 0x0050, 0x10, 2, 1),
1778 + PIN_FIELD_BASE(124, 124, 4, 0x0050, 0x10, 0, 1),
1779 + PIN_FIELD_BASE(125, 125, 4, 0x0050, 0x10, 4, 1),
1780 + PIN_FIELD_BASE(126, 126, 4, 0x0050, 0x10, 6, 1),
1781 + PIN_FIELD_BASE(127, 127, 4, 0x0050, 0x10, 8, 1),
1782 + PIN_FIELD_BASE(128, 128, 4, 0x0050, 0x10, 3, 1),
1783 + PIN_FIELD_BASE(129, 129, 4, 0x0050, 0x10, 7, 1),
1784 + PIN_FIELD_BASE(130, 130, 4, 0x0050, 0x10, 9, 1),
1785 + PIN_FIELD_BASE(131, 131, 4, 0x0050, 0x10, 10, 1),
1786 + PIN_FIELD_BASE(132, 132, 4, 0x0050, 0x10, 5, 1),
1787 + PINS_FIELD_BASE(133, 179, 4, 0x0050, 0x10, 11, 1),
1788 +};
1789 +
1790 +static const struct mtk_pin_field_calc mt6765_pin_r1_range[] = {
1791 + PINS_FIELD_BASE(0, 28, 4, 0x0050, 0x10, 11, 1),
1792 + PIN_FIELD_BASE(29, 29, 6, 0x0080, 0x10, 0, 1),
1793 + PIN_FIELD_BASE(30, 30, 6, 0x0080, 0x10, 1, 1),
1794 + PIN_FIELD_BASE(31, 31, 6, 0x0080, 0x10, 5, 1),
1795 + PIN_FIELD_BASE(32, 32, 6, 0x0080, 0x10, 2, 1),
1796 + PIN_FIELD_BASE(33, 33, 6, 0x0080, 0x10, 4, 1),
1797 + PIN_FIELD_BASE(34, 34, 6, 0x0080, 0x10, 3, 1),
1798 + PIN_FIELD_BASE(35, 35, 6, 0x0080, 0x10, 10, 1),
1799 + PIN_FIELD_BASE(36, 36, 6, 0x0080, 0x10, 11, 1),
1800 + PIN_FIELD_BASE(37, 37, 6, 0x0080, 0x10, 9, 1),
1801 + PIN_FIELD_BASE(38, 38, 6, 0x0080, 0x10, 6, 1),
1802 + PIN_FIELD_BASE(39, 39, 6, 0x0080, 0x10, 8, 1),
1803 + PINS_FIELD_BASE(40, 90, 6, 0x0080, 0x10, 7, 1),
1804 + PIN_FIELD_BASE(91, 91, 2, 0x0080, 0x10, 3, 1),
1805 + PIN_FIELD_BASE(92, 92, 2, 0x0080, 0x10, 2, 1),
1806 + PIN_FIELD_BASE(93, 93, 2, 0x0080, 0x10, 0, 1),
1807 + PINS_FIELD_BASE(94, 121, 2, 0x0080, 0x10, 1, 1),
1808 + PIN_FIELD_BASE(122, 122, 4, 0x0060, 0x10, 1, 1),
1809 + PIN_FIELD_BASE(123, 123, 4, 0x0060, 0x10, 2, 1),
1810 + PIN_FIELD_BASE(124, 124, 4, 0x0060, 0x10, 0, 1),
1811 + PIN_FIELD_BASE(125, 125, 4, 0x0060, 0x10, 4, 1),
1812 + PIN_FIELD_BASE(126, 126, 4, 0x0060, 0x10, 6, 1),
1813 + PIN_FIELD_BASE(127, 127, 4, 0x0060, 0x10, 8, 1),
1814 + PIN_FIELD_BASE(128, 128, 4, 0x0060, 0x10, 3, 1),
1815 + PIN_FIELD_BASE(129, 129, 4, 0x0060, 0x10, 7, 1),
1816 + PIN_FIELD_BASE(130, 130, 4, 0x0060, 0x10, 9, 1),
1817 + PIN_FIELD_BASE(131, 131, 4, 0x0060, 0x10, 10, 1),
1818 + PIN_FIELD_BASE(132, 132, 4, 0x0060, 0x10, 5, 1),
1819 + PINS_FIELD_BASE(133, 179, 4, 0x0060, 0x10, 11, 1),
1820 +};
1821 +
1822 +static const struct mtk_pin_field_calc mt6765_pin_ies_range[] = {
1823 + PIN_FIELD_BASE(0, 0, 2, 0x0030, 0x10, 6, 1),
1824 + PIN_FIELD_BASE(1, 1, 2, 0x0030, 0x10, 7, 1),
1825 + PIN_FIELD_BASE(2, 2, 2, 0x0030, 0x10, 10, 1),
1826 + PIN_FIELD_BASE(3, 3, 2, 0x0030, 0x10, 11, 1),
1827 + PIN_FIELD_BASE(4, 4, 2, 0x0030, 0x10, 12, 1),
1828 + PIN_FIELD_BASE(5, 5, 2, 0x0030, 0x10, 13, 1),
1829 + PIN_FIELD_BASE(6, 6, 2, 0x0030, 0x10, 14, 1),
1830 + PIN_FIELD_BASE(7, 7, 2, 0x0030, 0x10, 15, 1),
1831 + PIN_FIELD_BASE(8, 8, 3, 0x0030, 0x10, 12, 1),
1832 + PIN_FIELD_BASE(9, 9, 2, 0x0030, 0x10, 16, 1),
1833 + PIN_FIELD_BASE(10, 10, 2, 0x0030, 0x10, 8, 1),
1834 + PIN_FIELD_BASE(11, 11, 2, 0x0030, 0x10, 9, 1),
1835 + PIN_FIELD_BASE(12, 12, 5, 0x0020, 0x10, 9, 1),
1836 + PIN_FIELD_BASE(13, 13, 6, 0x0020, 0x10, 26, 1),
1837 + PIN_FIELD_BASE(14, 14, 6, 0x0020, 0x10, 25, 1),
1838 + PIN_FIELD_BASE(15, 15, 6, 0x0020, 0x10, 27, 1),
1839 + PIN_FIELD_BASE(16, 16, 6, 0x0020, 0x10, 24, 1),
1840 + PIN_FIELD_BASE(17, 17, 6, 0x0020, 0x10, 19, 1),
1841 + PIN_FIELD_BASE(18, 18, 6, 0x0020, 0x10, 16, 1),
1842 + PIN_FIELD_BASE(19, 19, 6, 0x0020, 0x10, 18, 1),
1843 + PIN_FIELD_BASE(20, 20, 6, 0x0020, 0x10, 17, 1),
1844 + PIN_FIELD_BASE(21, 21, 6, 0x0020, 0x10, 22, 1),
1845 + PIN_FIELD_BASE(22, 22, 6, 0x0020, 0x10, 21, 1),
1846 + PIN_FIELD_BASE(23, 23, 6, 0x0020, 0x10, 23, 1),
1847 + PIN_FIELD_BASE(24, 24, 6, 0x0020, 0x10, 20, 1),
1848 + PIN_FIELD_BASE(25, 25, 6, 0x0020, 0x10, 14, 1),
1849 + PIN_FIELD_BASE(26, 26, 6, 0x0020, 0x10, 13, 1),
1850 + PIN_FIELD_BASE(27, 27, 6, 0x0020, 0x10, 15, 1),
1851 + PIN_FIELD_BASE(28, 28, 6, 0x0020, 0x10, 12, 1),
1852 + PIN_FIELD_BASE(29, 29, 6, 0x0020, 0x10, 0, 1),
1853 + PIN_FIELD_BASE(30, 30, 6, 0x0020, 0x10, 1, 1),
1854 + PIN_FIELD_BASE(31, 31, 6, 0x0020, 0x10, 5, 1),
1855 + PIN_FIELD_BASE(32, 32, 6, 0x0020, 0x10, 2, 1),
1856 + PIN_FIELD_BASE(33, 33, 6, 0x0020, 0x10, 4, 1),
1857 + PIN_FIELD_BASE(34, 34, 6, 0x0020, 0x10, 3, 1),
1858 + PIN_FIELD_BASE(35, 35, 6, 0x0020, 0x10, 10, 1),
1859 + PIN_FIELD_BASE(36, 36, 6, 0x0020, 0x10, 11, 1),
1860 + PIN_FIELD_BASE(37, 37, 6, 0x0020, 0x10, 9, 1),
1861 + PIN_FIELD_BASE(38, 38, 6, 0x0020, 0x10, 6, 1),
1862 + PIN_FIELD_BASE(39, 39, 6, 0x0020, 0x10, 8, 1),
1863 + PIN_FIELD_BASE(40, 40, 6, 0x0020, 0x10, 7, 1),
1864 + PIN_FIELD_BASE(41, 41, 7, 0x0040, 0x10, 19, 1),
1865 + PIN_FIELD_BASE(42, 42, 7, 0x0040, 0x10, 9, 1),
1866 + PIN_FIELD_BASE(43, 43, 7, 0x0040, 0x10, 8, 1),
1867 + PIN_FIELD_BASE(44, 44, 7, 0x0040, 0x10, 10, 1),
1868 + PIN_FIELD_BASE(45, 45, 7, 0x0040, 0x10, 22, 1),
1869 + PIN_FIELD_BASE(46, 46, 7, 0x0040, 0x10, 21, 1),
1870 + PIN_FIELD_BASE(47, 47, 7, 0x0040, 0x10, 20, 1),
1871 + PIN_FIELD_BASE(48, 48, 7, 0x0050, 0x10, 3, 1),
1872 + PIN_FIELD_BASE(49, 49, 7, 0x0050, 0x10, 5, 1),
1873 + PIN_FIELD_BASE(50, 50, 7, 0x0050, 0x10, 2, 1),
1874 + PIN_FIELD_BASE(51, 51, 7, 0x0050, 0x10, 4, 1),
1875 + PIN_FIELD_BASE(52, 52, 7, 0x0040, 0x10, 1, 1),
1876 + PIN_FIELD_BASE(53, 53, 7, 0x0040, 0x10, 0, 1),
1877 + PIN_FIELD_BASE(54, 54, 7, 0x0040, 0x10, 5, 1),
1878 + PIN_FIELD_BASE(55, 55, 7, 0x0040, 0x10, 3, 1),
1879 + PIN_FIELD_BASE(56, 56, 7, 0x0040, 0x10, 4, 1),
1880 + PIN_FIELD_BASE(57, 57, 7, 0x0040, 0x10, 2, 1),
1881 + PIN_FIELD_BASE(58, 58, 7, 0x0050, 0x10, 0, 1),
1882 + PIN_FIELD_BASE(59, 59, 7, 0x0040, 0x10, 31, 1),
1883 + PIN_FIELD_BASE(60, 60, 7, 0x0040, 0x10, 30, 1),
1884 + PIN_FIELD_BASE(61, 61, 3, 0x0030, 0x10, 18, 1),
1885 + PIN_FIELD_BASE(62, 62, 3, 0x0030, 0x10, 14, 1),
1886 + PIN_FIELD_BASE(63, 63, 3, 0x0030, 0x10, 17, 1),
1887 + PIN_FIELD_BASE(64, 64, 3, 0x0030, 0x10, 13, 1),
1888 + PIN_FIELD_BASE(65, 65, 3, 0x0030, 0x10, 20, 1),
1889 + PIN_FIELD_BASE(66, 66, 3, 0x0030, 0x10, 16, 1),
1890 + PIN_FIELD_BASE(67, 67, 3, 0x0030, 0x10, 19, 1),
1891 + PIN_FIELD_BASE(68, 68, 3, 0x0030, 0x10, 15, 1),
1892 + PIN_FIELD_BASE(69, 69, 3, 0x0030, 0x10, 8, 1),
1893 + PIN_FIELD_BASE(70, 70, 3, 0x0030, 0x10, 7, 1),
1894 + PIN_FIELD_BASE(71, 71, 3, 0x0030, 0x10, 6, 1),
1895 + PIN_FIELD_BASE(72, 72, 3, 0x0030, 0x10, 5, 1),
1896 + PIN_FIELD_BASE(73, 73, 3, 0x0030, 0x10, 4, 1),
1897 + PIN_FIELD_BASE(74, 74, 3, 0x0030, 0x10, 3, 1),
1898 + PIN_FIELD_BASE(75, 75, 3, 0x0030, 0x10, 2, 1),
1899 + PIN_FIELD_BASE(76, 76, 3, 0x0030, 0x10, 1, 1),
1900 + PIN_FIELD_BASE(77, 77, 3, 0x0030, 0x10, 0, 1),
1901 + PIN_FIELD_BASE(78, 78, 3, 0x0030, 0x10, 9, 1),
1902 + PIN_FIELD_BASE(79, 79, 3, 0x0030, 0x10, 11, 1),
1903 + PIN_FIELD_BASE(80, 80, 3, 0x0030, 0x10, 10, 1),
1904 + PIN_FIELD_BASE(81, 81, 3, 0x0030, 0x10, 25, 1),
1905 + PIN_FIELD_BASE(82, 82, 3, 0x0030, 0x10, 24, 1),
1906 + PIN_FIELD_BASE(83, 83, 3, 0x0030, 0x10, 22, 1),
1907 + PIN_FIELD_BASE(84, 84, 3, 0x0030, 0x10, 23, 1),
1908 + PIN_FIELD_BASE(85, 85, 7, 0x0050, 0x10, 1, 1),
1909 + PIN_FIELD_BASE(86, 86, 7, 0x0040, 0x10, 29, 1),
1910 + PIN_FIELD_BASE(87, 87, 7, 0x0040, 0x10, 7, 1),
1911 + PIN_FIELD_BASE(88, 88, 7, 0x0040, 0x10, 6, 1),
1912 + PIN_FIELD_BASE(89, 89, 2, 0x0030, 0x10, 25, 1),
1913 + PIN_FIELD_BASE(90, 90, 3, 0x0030, 0x10, 21, 1),
1914 + PIN_FIELD_BASE(91, 91, 2, 0x0030, 0x10, 20, 1),
1915 + PIN_FIELD_BASE(92, 92, 2, 0x0030, 0x10, 19, 1),
1916 + PIN_FIELD_BASE(93, 93, 2, 0x0030, 0x10, 17, 1),
1917 + PIN_FIELD_BASE(94, 94, 2, 0x0030, 0x10, 18, 1),
1918 + PIN_FIELD_BASE(95, 95, 2, 0x0030, 0x10, 26, 1),
1919 + PIN_FIELD_BASE(96, 96, 2, 0x0030, 0x10, 27, 1),
1920 + PIN_FIELD_BASE(97, 97, 2, 0x0030, 0x10, 2, 1),
1921 + PIN_FIELD_BASE(98, 98, 2, 0x0030, 0x10, 3, 1),
1922 + PIN_FIELD_BASE(99, 99, 2, 0x0030, 0x10, 0, 1),
1923 + PIN_FIELD_BASE(100, 100, 2, 0x0030, 0x10, 1, 1),
1924 + PIN_FIELD_BASE(101, 101, 2, 0x0030, 0x10, 4, 1),
1925 + PIN_FIELD_BASE(102, 102, 2, 0x0030, 0x10, 5, 1),
1926 + PIN_FIELD_BASE(103, 103, 2, 0x0030, 0x10, 21, 1),
1927 + PIN_FIELD_BASE(104, 104, 2, 0x0030, 0x10, 23, 1),
1928 + PIN_FIELD_BASE(105, 105, 2, 0x0030, 0x10, 22, 1),
1929 + PIN_FIELD_BASE(106, 106, 2, 0x0030, 0x10, 24, 1),
1930 + PIN_FIELD_BASE(107, 107, 1, 0x0030, 0x10, 4, 1),
1931 + PIN_FIELD_BASE(108, 108, 1, 0x0030, 0x10, 3, 1),
1932 + PIN_FIELD_BASE(109, 109, 1, 0x0030, 0x10, 5, 1),
1933 + PIN_FIELD_BASE(110, 110, 1, 0x0030, 0x10, 0, 1),
1934 + PIN_FIELD_BASE(111, 111, 1, 0x0030, 0x10, 1, 1),
1935 + PIN_FIELD_BASE(112, 112, 1, 0x0030, 0x10, 2, 1),
1936 + PIN_FIELD_BASE(113, 113, 1, 0x0030, 0x10, 9, 1),
1937 + PIN_FIELD_BASE(114, 114, 1, 0x0030, 0x10, 10, 1),
1938 + PIN_FIELD_BASE(115, 115, 1, 0x0030, 0x10, 6, 1),
1939 + PIN_FIELD_BASE(116, 116, 1, 0x0030, 0x10, 7, 1),
1940 + PIN_FIELD_BASE(117, 117, 1, 0x0030, 0x10, 12, 1),
1941 + PIN_FIELD_BASE(118, 118, 1, 0x0030, 0x10, 13, 1),
1942 + PIN_FIELD_BASE(119, 119, 1, 0x0030, 0x10, 14, 1),
1943 + PIN_FIELD_BASE(120, 120, 1, 0x0030, 0x10, 11, 1),
1944 + PIN_FIELD_BASE(121, 121, 1, 0x0030, 0x10, 8, 1),
1945 + PIN_FIELD_BASE(122, 122, 4, 0x0010, 0x10, 9, 1),
1946 + PIN_FIELD_BASE(123, 123, 4, 0x0010, 0x10, 10, 1),
1947 + PIN_FIELD_BASE(124, 124, 4, 0x0010, 0x10, 8, 1),
1948 + PIN_FIELD_BASE(125, 125, 4, 0x0010, 0x10, 12, 1),
1949 + PIN_FIELD_BASE(126, 126, 4, 0x0010, 0x10, 14, 1),
1950 + PIN_FIELD_BASE(127, 127, 4, 0x0010, 0x10, 16, 1),
1951 + PIN_FIELD_BASE(128, 128, 4, 0x0010, 0x10, 11, 1),
1952 + PIN_FIELD_BASE(129, 129, 4, 0x0010, 0x10, 15, 1),
1953 + PIN_FIELD_BASE(130, 130, 4, 0x0010, 0x10, 17, 1),
1954 + PIN_FIELD_BASE(131, 131, 4, 0x0010, 0x10, 18, 1),
1955 + PIN_FIELD_BASE(132, 132, 4, 0x0010, 0x10, 13, 1),
1956 + PIN_FIELD_BASE(133, 133, 4, 0x0010, 0x10, 19, 1),
1957 + PIN_FIELD_BASE(134, 134, 5, 0x0020, 0x10, 14, 1),
1958 + PIN_FIELD_BASE(135, 135, 5, 0x0020, 0x10, 17, 1),
1959 + PIN_FIELD_BASE(136, 136, 5, 0x0020, 0x10, 1, 1),
1960 + PIN_FIELD_BASE(137, 137, 5, 0x0020, 0x10, 7, 1),
1961 + PIN_FIELD_BASE(138, 138, 5, 0x0020, 0x10, 4, 1),
1962 + PIN_FIELD_BASE(139, 139, 5, 0x0020, 0x10, 5, 1),
1963 + PIN_FIELD_BASE(140, 140, 5, 0x0020, 0x10, 0, 1),
1964 + PIN_FIELD_BASE(141, 141, 5, 0x0020, 0x10, 6, 1),
1965 + PIN_FIELD_BASE(142, 142, 5, 0x0020, 0x10, 2, 1),
1966 + PIN_FIELD_BASE(143, 143, 5, 0x0020, 0x10, 3, 1),
1967 + PIN_FIELD_BASE(144, 144, 5, 0x0020, 0x10, 12, 1),
1968 + PIN_FIELD_BASE(145, 145, 5, 0x0020, 0x10, 11, 1),
1969 + PIN_FIELD_BASE(146, 146, 5, 0x0020, 0x10, 13, 1),
1970 + PIN_FIELD_BASE(147, 147, 5, 0x0020, 0x10, 10, 1),
1971 + PIN_FIELD_BASE(148, 148, 5, 0x0020, 0x10, 15, 1),
1972 + PIN_FIELD_BASE(149, 149, 5, 0x0020, 0x10, 16, 1),
1973 + PIN_FIELD_BASE(150, 150, 7, 0x0040, 0x10, 23, 1),
1974 + PIN_FIELD_BASE(151, 151, 7, 0x0040, 0x10, 24, 1),
1975 + PIN_FIELD_BASE(152, 152, 7, 0x0040, 0x10, 25, 1),
1976 + PIN_FIELD_BASE(153, 153, 7, 0x0040, 0x10, 26, 1),
1977 + PIN_FIELD_BASE(154, 154, 7, 0x0040, 0x10, 28, 1),
1978 + PIN_FIELD_BASE(155, 155, 3, 0x0030, 0x10, 28, 1),
1979 + PIN_FIELD_BASE(156, 156, 3, 0x0030, 0x10, 27, 1),
1980 + PIN_FIELD_BASE(157, 157, 3, 0x0030, 0x10, 29, 1),
1981 + PIN_FIELD_BASE(158, 158, 3, 0x0030, 0x10, 26, 1),
1982 + PIN_FIELD_BASE(159, 159, 7, 0x0040, 0x10, 27, 1),
1983 + PIN_FIELD_BASE(160, 160, 5, 0x0020, 0x10, 8, 1),
1984 + PIN_FIELD_BASE(161, 161, 1, 0x0030, 0x10, 15, 1),
1985 + PIN_FIELD_BASE(162, 162, 1, 0x0030, 0x10, 16, 1),
1986 + PIN_FIELD_BASE(163, 163, 4, 0x0010, 0x10, 0, 1),
1987 + PIN_FIELD_BASE(164, 164, 4, 0x0010, 0x10, 1, 1),
1988 + PIN_FIELD_BASE(165, 165, 4, 0x0010, 0x10, 2, 1),
1989 + PIN_FIELD_BASE(166, 166, 4, 0x0010, 0x10, 3, 1),
1990 + PIN_FIELD_BASE(167, 167, 4, 0x0010, 0x10, 4, 1),
1991 + PIN_FIELD_BASE(168, 168, 4, 0x0010, 0x10, 5, 1),
1992 + PIN_FIELD_BASE(169, 169, 4, 0x0010, 0x10, 6, 1),
1993 + PIN_FIELD_BASE(170, 170, 4, 0x0010, 0x10, 7, 1),
1994 + PIN_FIELD_BASE(171, 171, 7, 0x0040, 0x10, 17, 1),
1995 + PIN_FIELD_BASE(172, 172, 7, 0x0040, 0x10, 18, 1),
1996 + PIN_FIELD_BASE(173, 173, 7, 0x0040, 0x10, 11, 1),
1997 + PIN_FIELD_BASE(174, 174, 7, 0x0040, 0x10, 12, 1),
1998 + PIN_FIELD_BASE(175, 175, 7, 0x0040, 0x10, 13, 1),
1999 + PIN_FIELD_BASE(176, 176, 7, 0x0040, 0x10, 14, 1),
2000 + PIN_FIELD_BASE(177, 177, 7, 0x0040, 0x10, 15, 1),
2001 + PINS_FIELD_BASE(178, 179, 7, 0x0040, 0x10, 16, 1),
2002 +};
2003 +
2004 +static const struct mtk_pin_reg_calc mt6765_reg_cals[PINCTRL_PIN_REG_MAX] = {
2005 + [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt6765_pin_mode_range),
2006 + [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt6765_pin_dir_range),
2007 + [PINCTRL_PIN_REG_DI] = MTK_RANGE(mt6765_pin_di_range),
2008 + [PINCTRL_PIN_REG_DO] = MTK_RANGE(mt6765_pin_do_range),
2009 + [PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt6765_pin_smt_range),
2010 + [PINCTRL_PIN_REG_PD] = MTK_RANGE(mt6765_pin_pd_range),
2011 + [PINCTRL_PIN_REG_PU] = MTK_RANGE(mt6765_pin_pu_range),
2012 + [PINCTRL_PIN_REG_TDSEL] = MTK_RANGE(mt6765_pin_tdsel_range),
2013 + [PINCTRL_PIN_REG_RDSEL] = MTK_RANGE(mt6765_pin_rdsel_range),
2014 + [PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt6765_pin_drv_range),
2015 + [PINCTRL_PIN_REG_PUPD] = MTK_RANGE(mt6765_pin_pupd_range),
2016 + [PINCTRL_PIN_REG_R0] = MTK_RANGE(mt6765_pin_r0_range),
2017 + [PINCTRL_PIN_REG_R1] = MTK_RANGE(mt6765_pin_r1_range),
2018 + [PINCTRL_PIN_REG_IES] = MTK_RANGE(mt6765_pin_ies_range),
2019 +};
2020 +
2021 +static const char * const mt6765_pinctrl_register_base_names[] = {
2022 + "iocfg0", "iocfg1", "iocfg2", "iocfg3", "iocfg4", "iocfg5",
2023 + "iocfg6", "iocfg7",
2024 +};
2025 +
2026 +static const struct mtk_eint_hw mt6765_eint_hw = {
2027 + .port_mask = 7,
2028 + .ports = 6,
2029 + .ap_num = 160,
2030 + .db_cnt = 13,
2031 +};
2032 +
2033 +static const struct mtk_pin_soc mt6765_data = {
2034 + .reg_cal = mt6765_reg_cals,
2035 + .pins = mtk_pins_mt6765,
2036 + .npins = ARRAY_SIZE(mtk_pins_mt6765),
2037 + .ngrps = ARRAY_SIZE(mtk_pins_mt6765),
2038 + .eint_hw = &mt6765_eint_hw,
2039 + .gpio_m = 0,
2040 + .ies_present = true,
2041 + .base_names = mt6765_pinctrl_register_base_names,
2042 + .nbase_names = ARRAY_SIZE(mt6765_pinctrl_register_base_names),
2043 + .bias_disable_set = mtk_pinconf_bias_disable_set,
2044 + .bias_disable_get = mtk_pinconf_bias_disable_get,
2045 + .bias_set = mtk_pinconf_bias_set,
2046 + .bias_get = mtk_pinconf_bias_get,
2047 + .drive_set = mtk_pinconf_drive_set_rev1,
2048 + .drive_get = mtk_pinconf_drive_get_rev1,
2049 + .adv_pull_get = mtk_pinconf_adv_pull_get,
2050 + .adv_pull_set = mtk_pinconf_adv_pull_set,
2051 +};
2052 +
2053 +static const struct of_device_id mt6765_pinctrl_of_match[] = {
2054 + { .compatible = "mediatek,mt6765-pinctrl", },
2055 + { }
2056 +};
2057 +
2058 +static int mt6765_pinctrl_probe(struct platform_device *pdev)
2059 +{
2060 + return mtk_paris_pinctrl_probe(pdev, &mt6765_data);
2061 +}
2062 +
2063 +static struct platform_driver mt6765_pinctrl_driver = {
2064 + .driver = {
2065 + .name = "mt6765-pinctrl",
2066 + .of_match_table = mt6765_pinctrl_of_match,
2067 + },
2068 + .probe = mt6765_pinctrl_probe,
2069 +};
2070 +
2071 +static int __init mt6765_pinctrl_init(void)
2072 +{
2073 + return platform_driver_register(&mt6765_pinctrl_driver);
2074 +}
2075 +arch_initcall(mt6765_pinctrl_init);
2076 --- /dev/null
2077 +++ b/drivers/pinctrl/mediatek/pinctrl-mt6797.c
2078 @@ -0,0 +1,82 @@
2079 +// SPDX-License-Identifier: GPL-2.0
2080 +/*
2081 + * Based on pinctrl-mt6765.c
2082 + *
2083 + * Copyright (C) 2018 MediaTek Inc.
2084 + *
2085 + * Author: ZH Chen <zh.chen@mediatek.com>
2086 + *
2087 + * Copyright (C) Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
2088 + *
2089 + */
2090 +
2091 +#include "pinctrl-mtk-mt6797.h"
2092 +#include "pinctrl-paris.h"
2093 +
2094 +/*
2095 + * MT6797 have multiple bases to program pin configuration listed as the below:
2096 + * gpio:0x10005000, iocfg[l]:0x10002000, iocfg[b]:0x10002400,
2097 + * iocfg[r]:0x10002800, iocfg[t]:0x10002C00.
2098 + * _i_base could be used to indicate what base the pin should be mapped into.
2099 + */
2100 +
2101 +static const struct mtk_pin_field_calc mt6797_pin_mode_range[] = {
2102 + PIN_FIELD(0, 261, 0x300, 0x10, 0, 4),
2103 +};
2104 +
2105 +static const struct mtk_pin_field_calc mt6797_pin_dir_range[] = {
2106 + PIN_FIELD(0, 261, 0x0, 0x10, 0, 1),
2107 +};
2108 +
2109 +static const struct mtk_pin_field_calc mt6797_pin_di_range[] = {
2110 + PIN_FIELD(0, 261, 0x200, 0x10, 0, 1),
2111 +};
2112 +
2113 +static const struct mtk_pin_field_calc mt6797_pin_do_range[] = {
2114 + PIN_FIELD(0, 261, 0x100, 0x10, 0, 1),
2115 +};
2116 +
2117 +static const struct mtk_pin_reg_calc mt6797_reg_cals[PINCTRL_PIN_REG_MAX] = {
2118 + [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt6797_pin_mode_range),
2119 + [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt6797_pin_dir_range),
2120 + [PINCTRL_PIN_REG_DI] = MTK_RANGE(mt6797_pin_di_range),
2121 + [PINCTRL_PIN_REG_DO] = MTK_RANGE(mt6797_pin_do_range),
2122 +};
2123 +
2124 +static const char * const mt6797_pinctrl_register_base_names[] = {
2125 + "gpio", "iocfgl", "iocfgb", "iocfgr", "iocfgt",
2126 +};
2127 +
2128 +static const struct mtk_pin_soc mt6797_data = {
2129 + .reg_cal = mt6797_reg_cals,
2130 + .pins = mtk_pins_mt6797,
2131 + .npins = ARRAY_SIZE(mtk_pins_mt6797),
2132 + .ngrps = ARRAY_SIZE(mtk_pins_mt6797),
2133 + .gpio_m = 0,
2134 + .base_names = mt6797_pinctrl_register_base_names,
2135 + .nbase_names = ARRAY_SIZE(mt6797_pinctrl_register_base_names),
2136 +};
2137 +
2138 +static const struct of_device_id mt6797_pinctrl_of_match[] = {
2139 + { .compatible = "mediatek,mt6797-pinctrl", },
2140 + { }
2141 +};
2142 +
2143 +static int mt6797_pinctrl_probe(struct platform_device *pdev)
2144 +{
2145 + return mtk_paris_pinctrl_probe(pdev, &mt6797_data);
2146 +}
2147 +
2148 +static struct platform_driver mt6797_pinctrl_driver = {
2149 + .driver = {
2150 + .name = "mt6797-pinctrl",
2151 + .of_match_table = mt6797_pinctrl_of_match,
2152 + },
2153 + .probe = mt6797_pinctrl_probe,
2154 +};
2155 +
2156 +static int __init mt6797_pinctrl_init(void)
2157 +{
2158 + return platform_driver_register(&mt6797_pinctrl_driver);
2159 +}
2160 +arch_initcall(mt6797_pinctrl_init);
2161 --- a/drivers/pinctrl/mediatek/pinctrl-mt7622.c
2162 +++ b/drivers/pinctrl/mediatek/pinctrl-mt7622.c
2163 @@ -1,297 +1,140 @@
2164 +// SPDX-License-Identifier: GPL-2.0
2165 /*
2166 - * MediaTek MT7622 Pinctrl Driver
2167 + * Copyright (C) 2017-2018 MediaTek Inc.
2168 *
2169 - * Copyright (C) 2017 Sean Wang <sean.wang@mediatek.com>
2170 + * Author: Sean Wang <sean.wang@mediatek.com>
2171 *
2172 - * This program is free software; you can redistribute it and/or modify
2173 - * it under the terms of the GNU General Public License version 2 as
2174 - * published by the Free Software Foundation.
2175 - *
2176 - * This program is distributed in the hope that it will be useful,
2177 - * but WITHOUT ANY WARRANTY; without even the implied warranty of
2178 - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2179 - * GNU General Public License for more details.
2180 - */
2181 -
2182 -#include <linux/gpio.h>
2183 -#include <linux/gpio/driver.h>
2184 -#include <linux/io.h>
2185 -#include <linux/init.h>
2186 -#include <linux/mfd/syscon.h>
2187 -#include <linux/of.h>
2188 -#include <linux/of_irq.h>
2189 -#include <linux/of_platform.h>
2190 -#include <linux/platform_device.h>
2191 -#include <linux/pinctrl/pinctrl.h>
2192 -#include <linux/pinctrl/pinmux.h>
2193 -#include <linux/pinctrl/pinconf.h>
2194 -#include <linux/pinctrl/pinconf-generic.h>
2195 -#include <linux/regmap.h>
2196 -
2197 -#include "../core.h"
2198 -#include "../pinconf.h"
2199 -#include "../pinmux.h"
2200 -#include "mtk-eint.h"
2201 -
2202 -#define PINCTRL_PINCTRL_DEV KBUILD_MODNAME
2203 -#define MTK_RANGE(_a) { .range = (_a), .nranges = ARRAY_SIZE(_a), }
2204 -#define PINCTRL_PIN_GROUP(name, id) \
2205 - { \
2206 - name, \
2207 - id##_pins, \
2208 - ARRAY_SIZE(id##_pins), \
2209 - id##_funcs, \
2210 - }
2211 -
2212 -#define MTK_GPIO_MODE 1
2213 -#define MTK_INPUT 0
2214 -#define MTK_OUTPUT 1
2215 -#define MTK_DISABLE 0
2216 -#define MTK_ENABLE 1
2217 -
2218 -/* Custom pinconf parameters */
2219 -#define MTK_PIN_CONFIG_TDSEL (PIN_CONFIG_END + 1)
2220 -#define MTK_PIN_CONFIG_RDSEL (PIN_CONFIG_END + 2)
2221 -
2222 -/* List these attributes which could be modified for the pin */
2223 -enum {
2224 - PINCTRL_PIN_REG_MODE,
2225 - PINCTRL_PIN_REG_DIR,
2226 - PINCTRL_PIN_REG_DI,
2227 - PINCTRL_PIN_REG_DO,
2228 - PINCTRL_PIN_REG_SR,
2229 - PINCTRL_PIN_REG_SMT,
2230 - PINCTRL_PIN_REG_PD,
2231 - PINCTRL_PIN_REG_PU,
2232 - PINCTRL_PIN_REG_E4,
2233 - PINCTRL_PIN_REG_E8,
2234 - PINCTRL_PIN_REG_TDSEL,
2235 - PINCTRL_PIN_REG_RDSEL,
2236 - PINCTRL_PIN_REG_MAX,
2237 -};
2238 -
2239 -/* struct mtk_pin_field - the structure that holds the information of the field
2240 - * used to describe the attribute for the pin
2241 - * @offset: the register offset relative to the base address
2242 - * @mask: the mask used to filter out the field from the register
2243 - * @bitpos: the start bit relative to the register
2244 - * @next: the indication that the field would be extended to the
2245 - next register
2246 - */
2247 -struct mtk_pin_field {
2248 - u32 offset;
2249 - u32 mask;
2250 - u8 bitpos;
2251 - u8 next;
2252 -};
2253 -
2254 -/* struct mtk_pin_field_calc - the structure that holds the range providing
2255 - * the guide used to look up the relevant field
2256 - * @s_pin: the start pin within the range
2257 - * @e_pin: the end pin within the range
2258 - * @s_addr: the start address for the range
2259 - * @x_addrs: the address distance between two consecutive registers
2260 - * within the range
2261 - * @s_bit: the start bit for the first register within the range
2262 - * @x_bits: the bit distance between two consecutive pins within
2263 - * the range
2264 - */
2265 -struct mtk_pin_field_calc {
2266 - u16 s_pin;
2267 - u16 e_pin;
2268 - u32 s_addr;
2269 - u8 x_addrs;
2270 - u8 s_bit;
2271 - u8 x_bits;
2272 -};
2273 -
2274 -/* struct mtk_pin_reg_calc - the structure that holds all ranges used to
2275 - * determine which register the pin would make use of
2276 - * for certain pin attribute.
2277 - * @range: the start address for the range
2278 - * @nranges: the number of items in the range
2279 */
2280 -struct mtk_pin_reg_calc {
2281 - const struct mtk_pin_field_calc *range;
2282 - unsigned int nranges;
2283 -};
2284
2285 -/* struct mtk_pin_soc - the structure that holds SoC-specific data */
2286 -struct mtk_pin_soc {
2287 - const struct mtk_pin_reg_calc *reg_cal;
2288 - const struct pinctrl_pin_desc *pins;
2289 - unsigned int npins;
2290 - const struct group_desc *grps;
2291 - unsigned int ngrps;
2292 - const struct function_desc *funcs;
2293 - unsigned int nfuncs;
2294 - const struct mtk_eint_regs *eint_regs;
2295 - const struct mtk_eint_hw *eint_hw;
2296 -};
2297 +#include "pinctrl-moore.h"
2298
2299 -struct mtk_pinctrl {
2300 - struct pinctrl_dev *pctrl;
2301 - void __iomem *base;
2302 - struct device *dev;
2303 - struct gpio_chip chip;
2304 - const struct mtk_pin_soc *soc;
2305 - struct mtk_eint *eint;
2306 -};
2307 +#define MT7622_PIN(_number, _name) \
2308 + MTK_PIN(_number, _name, 1, _number, DRV_GRP0)
2309
2310 static const struct mtk_pin_field_calc mt7622_pin_mode_range[] = {
2311 - {0, 0, 0x320, 0x10, 16, 4},
2312 - {1, 4, 0x3a0, 0x10, 16, 4},
2313 - {5, 5, 0x320, 0x10, 0, 4},
2314 - {6, 6, 0x300, 0x10, 4, 4},
2315 - {7, 7, 0x300, 0x10, 4, 4},
2316 - {8, 9, 0x350, 0x10, 20, 4},
2317 - {10, 10, 0x300, 0x10, 8, 4},
2318 - {11, 11, 0x300, 0x10, 8, 4},
2319 - {12, 12, 0x300, 0x10, 8, 4},
2320 - {13, 13, 0x300, 0x10, 8, 4},
2321 - {14, 15, 0x320, 0x10, 4, 4},
2322 - {16, 17, 0x320, 0x10, 20, 4},
2323 - {18, 21, 0x310, 0x10, 16, 4},
2324 - {22, 22, 0x380, 0x10, 16, 4},
2325 - {23, 23, 0x300, 0x10, 24, 4},
2326 - {24, 24, 0x300, 0x10, 24, 4},
2327 - {25, 25, 0x300, 0x10, 12, 4},
2328 - {25, 25, 0x300, 0x10, 12, 4},
2329 - {26, 26, 0x300, 0x10, 12, 4},
2330 - {27, 27, 0x300, 0x10, 12, 4},
2331 - {28, 28, 0x300, 0x10, 12, 4},
2332 - {29, 29, 0x300, 0x10, 12, 4},
2333 - {30, 30, 0x300, 0x10, 12, 4},
2334 - {31, 31, 0x300, 0x10, 12, 4},
2335 - {32, 32, 0x300, 0x10, 12, 4},
2336 - {33, 33, 0x300, 0x10, 12, 4},
2337 - {34, 34, 0x300, 0x10, 12, 4},
2338 - {35, 35, 0x300, 0x10, 12, 4},
2339 - {36, 36, 0x300, 0x10, 12, 4},
2340 - {37, 37, 0x300, 0x10, 20, 4},
2341 - {38, 38, 0x300, 0x10, 20, 4},
2342 - {39, 39, 0x300, 0x10, 20, 4},
2343 - {40, 40, 0x300, 0x10, 20, 4},
2344 - {41, 41, 0x300, 0x10, 20, 4},
2345 - {42, 42, 0x300, 0x10, 20, 4},
2346 - {43, 43, 0x300, 0x10, 20, 4},
2347 - {44, 44, 0x300, 0x10, 20, 4},
2348 - {45, 46, 0x300, 0x10, 20, 4},
2349 - {47, 47, 0x300, 0x10, 20, 4},
2350 - {48, 48, 0x300, 0x10, 20, 4},
2351 - {49, 49, 0x300, 0x10, 20, 4},
2352 - {50, 50, 0x300, 0x10, 20, 4},
2353 - {51, 70, 0x330, 0x10, 4, 4},
2354 - {71, 71, 0x300, 0x10, 16, 4},
2355 - {72, 72, 0x300, 0x10, 16, 4},
2356 - {73, 76, 0x310, 0x10, 0, 4},
2357 - {77, 77, 0x320, 0x10, 28, 4},
2358 - {78, 78, 0x320, 0x10, 12, 4},
2359 - {79, 82, 0x3a0, 0x10, 0, 4},
2360 - {83, 83, 0x350, 0x10, 28, 4},
2361 - {84, 84, 0x330, 0x10, 0, 4},
2362 - {85, 90, 0x360, 0x10, 4, 4},
2363 - {91, 94, 0x390, 0x10, 16, 4},
2364 - {95, 97, 0x380, 0x10, 20, 4},
2365 - {98, 101, 0x390, 0x10, 0, 4},
2366 - {102, 102, 0x360, 0x10, 0, 4},
2367 + PIN_FIELD(0, 0, 0x320, 0x10, 16, 4),
2368 + PIN_FIELD(1, 4, 0x3a0, 0x10, 16, 4),
2369 + PIN_FIELD(5, 5, 0x320, 0x10, 0, 4),
2370 + PINS_FIELD(6, 7, 0x300, 0x10, 4, 4),
2371 + PIN_FIELD(8, 9, 0x350, 0x10, 20, 4),
2372 + PINS_FIELD(10, 13, 0x300, 0x10, 8, 4),
2373 + PIN_FIELD(14, 15, 0x320, 0x10, 4, 4),
2374 + PIN_FIELD(16, 17, 0x320, 0x10, 20, 4),
2375 + PIN_FIELD(18, 21, 0x310, 0x10, 16, 4),
2376 + PIN_FIELD(22, 22, 0x380, 0x10, 16, 4),
2377 + PINS_FIELD(23, 24, 0x300, 0x10, 24, 4),
2378 + PINS_FIELD(25, 36, 0x300, 0x10, 12, 4),
2379 + PINS_FIELD(37, 50, 0x300, 0x10, 20, 4),
2380 + PIN_FIELD(51, 70, 0x330, 0x10, 4, 4),
2381 + PINS_FIELD(71, 72, 0x300, 0x10, 16, 4),
2382 + PIN_FIELD(73, 76, 0x310, 0x10, 0, 4),
2383 + PIN_FIELD(77, 77, 0x320, 0x10, 28, 4),
2384 + PIN_FIELD(78, 78, 0x320, 0x10, 12, 4),
2385 + PIN_FIELD(79, 82, 0x3a0, 0x10, 0, 4),
2386 + PIN_FIELD(83, 83, 0x350, 0x10, 28, 4),
2387 + PIN_FIELD(84, 84, 0x330, 0x10, 0, 4),
2388 + PIN_FIELD(85, 90, 0x360, 0x10, 4, 4),
2389 + PIN_FIELD(91, 94, 0x390, 0x10, 16, 4),
2390 + PIN_FIELD(95, 97, 0x380, 0x10, 20, 4),
2391 + PIN_FIELD(98, 101, 0x390, 0x10, 0, 4),
2392 + PIN_FIELD(102, 102, 0x360, 0x10, 0, 4),
2393 };
2394
2395 static const struct mtk_pin_field_calc mt7622_pin_dir_range[] = {
2396 - {0, 102, 0x0, 0x10, 0, 1},
2397 + PIN_FIELD(0, 102, 0x0, 0x10, 0, 1),
2398 };
2399
2400 static const struct mtk_pin_field_calc mt7622_pin_di_range[] = {
2401 - {0, 102, 0x200, 0x10, 0, 1},
2402 + PIN_FIELD(0, 102, 0x200, 0x10, 0, 1),
2403 };
2404
2405 static const struct mtk_pin_field_calc mt7622_pin_do_range[] = {
2406 - {0, 102, 0x100, 0x10, 0, 1},
2407 + PIN_FIELD(0, 102, 0x100, 0x10, 0, 1),
2408 };
2409
2410 static const struct mtk_pin_field_calc mt7622_pin_sr_range[] = {
2411 - {0, 31, 0x910, 0x10, 0, 1},
2412 - {32, 50, 0xa10, 0x10, 0, 1},
2413 - {51, 70, 0x810, 0x10, 0, 1},
2414 - {71, 72, 0xb10, 0x10, 0, 1},
2415 - {73, 86, 0xb10, 0x10, 4, 1},
2416 - {87, 90, 0xc10, 0x10, 0, 1},
2417 - {91, 102, 0xb10, 0x10, 18, 1},
2418 + PIN_FIELD(0, 31, 0x910, 0x10, 0, 1),
2419 + PIN_FIELD(32, 50, 0xa10, 0x10, 0, 1),
2420 + PIN_FIELD(51, 70, 0x810, 0x10, 0, 1),
2421 + PIN_FIELD(71, 72, 0xb10, 0x10, 0, 1),
2422 + PIN_FIELD(73, 86, 0xb10, 0x10, 4, 1),
2423 + PIN_FIELD(87, 90, 0xc10, 0x10, 0, 1),
2424 + PIN_FIELD(91, 102, 0xb10, 0x10, 18, 1),
2425 };
2426
2427 static const struct mtk_pin_field_calc mt7622_pin_smt_range[] = {
2428 - {0, 31, 0x920, 0x10, 0, 1},
2429 - {32, 50, 0xa20, 0x10, 0, 1},
2430 - {51, 70, 0x820, 0x10, 0, 1},
2431 - {71, 72, 0xb20, 0x10, 0, 1},
2432 - {73, 86, 0xb20, 0x10, 4, 1},
2433 - {87, 90, 0xc20, 0x10, 0, 1},
2434 - {91, 102, 0xb20, 0x10, 18, 1},
2435 + PIN_FIELD(0, 31, 0x920, 0x10, 0, 1),
2436 + PIN_FIELD(32, 50, 0xa20, 0x10, 0, 1),
2437 + PIN_FIELD(51, 70, 0x820, 0x10, 0, 1),
2438 + PIN_FIELD(71, 72, 0xb20, 0x10, 0, 1),
2439 + PIN_FIELD(73, 86, 0xb20, 0x10, 4, 1),
2440 + PIN_FIELD(87, 90, 0xc20, 0x10, 0, 1),
2441 + PIN_FIELD(91, 102, 0xb20, 0x10, 18, 1),
2442 };
2443
2444 static const struct mtk_pin_field_calc mt7622_pin_pu_range[] = {
2445 - {0, 31, 0x930, 0x10, 0, 1},
2446 - {32, 50, 0xa30, 0x10, 0, 1},
2447 - {51, 70, 0x830, 0x10, 0, 1},
2448 - {71, 72, 0xb30, 0x10, 0, 1},
2449 - {73, 86, 0xb30, 0x10, 4, 1},
2450 - {87, 90, 0xc30, 0x10, 0, 1},
2451 - {91, 102, 0xb30, 0x10, 18, 1},
2452 + PIN_FIELD(0, 31, 0x930, 0x10, 0, 1),
2453 + PIN_FIELD(32, 50, 0xa30, 0x10, 0, 1),
2454 + PIN_FIELD(51, 70, 0x830, 0x10, 0, 1),
2455 + PIN_FIELD(71, 72, 0xb30, 0x10, 0, 1),
2456 + PIN_FIELD(73, 86, 0xb30, 0x10, 4, 1),
2457 + PIN_FIELD(87, 90, 0xc30, 0x10, 0, 1),
2458 + PIN_FIELD(91, 102, 0xb30, 0x10, 18, 1),
2459 };
2460
2461 static const struct mtk_pin_field_calc mt7622_pin_pd_range[] = {
2462 - {0, 31, 0x940, 0x10, 0, 1},
2463 - {32, 50, 0xa40, 0x10, 0, 1},
2464 - {51, 70, 0x840, 0x10, 0, 1},
2465 - {71, 72, 0xb40, 0x10, 0, 1},
2466 - {73, 86, 0xb40, 0x10, 4, 1},
2467 - {87, 90, 0xc40, 0x10, 0, 1},
2468 - {91, 102, 0xb40, 0x10, 18, 1},
2469 + PIN_FIELD(0, 31, 0x940, 0x10, 0, 1),
2470 + PIN_FIELD(32, 50, 0xa40, 0x10, 0, 1),
2471 + PIN_FIELD(51, 70, 0x840, 0x10, 0, 1),
2472 + PIN_FIELD(71, 72, 0xb40, 0x10, 0, 1),
2473 + PIN_FIELD(73, 86, 0xb40, 0x10, 4, 1),
2474 + PIN_FIELD(87, 90, 0xc40, 0x10, 0, 1),
2475 + PIN_FIELD(91, 102, 0xb40, 0x10, 18, 1),
2476 };
2477
2478 static const struct mtk_pin_field_calc mt7622_pin_e4_range[] = {
2479 - {0, 31, 0x960, 0x10, 0, 1},
2480 - {32, 50, 0xa60, 0x10, 0, 1},
2481 - {51, 70, 0x860, 0x10, 0, 1},
2482 - {71, 72, 0xb60, 0x10, 0, 1},
2483 - {73, 86, 0xb60, 0x10, 4, 1},
2484 - {87, 90, 0xc60, 0x10, 0, 1},
2485 - {91, 102, 0xb60, 0x10, 18, 1},
2486 + PIN_FIELD(0, 31, 0x960, 0x10, 0, 1),
2487 + PIN_FIELD(32, 50, 0xa60, 0x10, 0, 1),
2488 + PIN_FIELD(51, 70, 0x860, 0x10, 0, 1),
2489 + PIN_FIELD(71, 72, 0xb60, 0x10, 0, 1),
2490 + PIN_FIELD(73, 86, 0xb60, 0x10, 4, 1),
2491 + PIN_FIELD(87, 90, 0xc60, 0x10, 0, 1),
2492 + PIN_FIELD(91, 102, 0xb60, 0x10, 18, 1),
2493 };
2494
2495 static const struct mtk_pin_field_calc mt7622_pin_e8_range[] = {
2496 - {0, 31, 0x970, 0x10, 0, 1},
2497 - {32, 50, 0xa70, 0x10, 0, 1},
2498 - {51, 70, 0x870, 0x10, 0, 1},
2499 - {71, 72, 0xb70, 0x10, 0, 1},
2500 - {73, 86, 0xb70, 0x10, 4, 1},
2501 - {87, 90, 0xc70, 0x10, 0, 1},
2502 - {91, 102, 0xb70, 0x10, 18, 1},
2503 + PIN_FIELD(0, 31, 0x970, 0x10, 0, 1),
2504 + PIN_FIELD(32, 50, 0xa70, 0x10, 0, 1),
2505 + PIN_FIELD(51, 70, 0x870, 0x10, 0, 1),
2506 + PIN_FIELD(71, 72, 0xb70, 0x10, 0, 1),
2507 + PIN_FIELD(73, 86, 0xb70, 0x10, 4, 1),
2508 + PIN_FIELD(87, 90, 0xc70, 0x10, 0, 1),
2509 + PIN_FIELD(91, 102, 0xb70, 0x10, 18, 1),
2510 };
2511
2512 static const struct mtk_pin_field_calc mt7622_pin_tdsel_range[] = {
2513 - {0, 31, 0x980, 0x4, 0, 4},
2514 - {32, 50, 0xa80, 0x4, 0, 4},
2515 - {51, 70, 0x880, 0x4, 0, 4},
2516 - {71, 72, 0xb80, 0x4, 0, 4},
2517 - {73, 86, 0xb80, 0x4, 16, 4},
2518 - {87, 90, 0xc80, 0x4, 0, 4},
2519 - {91, 102, 0xb88, 0x4, 8, 4},
2520 + PIN_FIELD(0, 31, 0x980, 0x4, 0, 4),
2521 + PIN_FIELD(32, 50, 0xa80, 0x4, 0, 4),
2522 + PIN_FIELD(51, 70, 0x880, 0x4, 0, 4),
2523 + PIN_FIELD(71, 72, 0xb80, 0x4, 0, 4),
2524 + PIN_FIELD(73, 86, 0xb80, 0x4, 16, 4),
2525 + PIN_FIELD(87, 90, 0xc80, 0x4, 0, 4),
2526 + PIN_FIELD(91, 102, 0xb88, 0x4, 8, 4),
2527 };
2528
2529 static const struct mtk_pin_field_calc mt7622_pin_rdsel_range[] = {
2530 - {0, 31, 0x990, 0x4, 0, 6},
2531 - {32, 50, 0xa90, 0x4, 0, 6},
2532 - {51, 58, 0x890, 0x4, 0, 6},
2533 - {59, 60, 0x894, 0x4, 28, 6},
2534 - {61, 62, 0x894, 0x4, 16, 6},
2535 - {63, 66, 0x898, 0x4, 8, 6},
2536 - {67, 68, 0x89c, 0x4, 12, 6},
2537 - {69, 70, 0x89c, 0x4, 0, 6},
2538 - {71, 72, 0xb90, 0x4, 0, 6},
2539 - {73, 86, 0xb90, 0x4, 24, 6},
2540 - {87, 90, 0xc90, 0x4, 0, 6},
2541 - {91, 102, 0xb9c, 0x4, 12, 6},
2542 + PIN_FIELD(0, 31, 0x990, 0x4, 0, 6),
2543 + PIN_FIELD(32, 50, 0xa90, 0x4, 0, 6),
2544 + PIN_FIELD(51, 58, 0x890, 0x4, 0, 6),
2545 + PIN_FIELD(59, 60, 0x894, 0x4, 28, 6),
2546 + PIN_FIELD(61, 62, 0x894, 0x4, 16, 6),
2547 + PIN_FIELD(63, 66, 0x898, 0x4, 8, 6),
2548 + PIN_FIELD(67, 68, 0x89c, 0x4, 12, 6),
2549 + PIN_FIELD(69, 70, 0x89c, 0x4, 0, 6),
2550 + PIN_FIELD(71, 72, 0xb90, 0x4, 0, 6),
2551 + PIN_FIELD(73, 86, 0xb90, 0x4, 24, 6),
2552 + PIN_FIELD(87, 90, 0xc90, 0x4, 0, 6),
2553 + PIN_FIELD(91, 102, 0xb9c, 0x4, 12, 6),
2554 };
2555
2556 static const struct mtk_pin_reg_calc mt7622_reg_cals[PINCTRL_PIN_REG_MAX] = {
2557 @@ -309,110 +152,110 @@ static const struct mtk_pin_reg_calc mt7
2558 [PINCTRL_PIN_REG_RDSEL] = MTK_RANGE(mt7622_pin_rdsel_range),
2559 };
2560
2561 -static const struct pinctrl_pin_desc mt7622_pins[] = {
2562 - PINCTRL_PIN(0, "GPIO_A"),
2563 - PINCTRL_PIN(1, "I2S1_IN"),
2564 - PINCTRL_PIN(2, "I2S1_OUT"),
2565 - PINCTRL_PIN(3, "I2S_BCLK"),
2566 - PINCTRL_PIN(4, "I2S_WS"),
2567 - PINCTRL_PIN(5, "I2S_MCLK"),
2568 - PINCTRL_PIN(6, "TXD0"),
2569 - PINCTRL_PIN(7, "RXD0"),
2570 - PINCTRL_PIN(8, "SPI_WP"),
2571 - PINCTRL_PIN(9, "SPI_HOLD"),
2572 - PINCTRL_PIN(10, "SPI_CLK"),
2573 - PINCTRL_PIN(11, "SPI_MOSI"),
2574 - PINCTRL_PIN(12, "SPI_MISO"),
2575 - PINCTRL_PIN(13, "SPI_CS"),
2576 - PINCTRL_PIN(14, "I2C_SDA"),
2577 - PINCTRL_PIN(15, "I2C_SCL"),
2578 - PINCTRL_PIN(16, "I2S2_IN"),
2579 - PINCTRL_PIN(17, "I2S3_IN"),
2580 - PINCTRL_PIN(18, "I2S4_IN"),
2581 - PINCTRL_PIN(19, "I2S2_OUT"),
2582 - PINCTRL_PIN(20, "I2S3_OUT"),
2583 - PINCTRL_PIN(21, "I2S4_OUT"),
2584 - PINCTRL_PIN(22, "GPIO_B"),
2585 - PINCTRL_PIN(23, "MDC"),
2586 - PINCTRL_PIN(24, "MDIO"),
2587 - PINCTRL_PIN(25, "G2_TXD0"),
2588 - PINCTRL_PIN(26, "G2_TXD1"),
2589 - PINCTRL_PIN(27, "G2_TXD2"),
2590 - PINCTRL_PIN(28, "G2_TXD3"),
2591 - PINCTRL_PIN(29, "G2_TXEN"),
2592 - PINCTRL_PIN(30, "G2_TXC"),
2593 - PINCTRL_PIN(31, "G2_RXD0"),
2594 - PINCTRL_PIN(32, "G2_RXD1"),
2595 - PINCTRL_PIN(33, "G2_RXD2"),
2596 - PINCTRL_PIN(34, "G2_RXD3"),
2597 - PINCTRL_PIN(35, "G2_RXDV"),
2598 - PINCTRL_PIN(36, "G2_RXC"),
2599 - PINCTRL_PIN(37, "NCEB"),
2600 - PINCTRL_PIN(38, "NWEB"),
2601 - PINCTRL_PIN(39, "NREB"),
2602 - PINCTRL_PIN(40, "NDL4"),
2603 - PINCTRL_PIN(41, "NDL5"),
2604 - PINCTRL_PIN(42, "NDL6"),
2605 - PINCTRL_PIN(43, "NDL7"),
2606 - PINCTRL_PIN(44, "NRB"),
2607 - PINCTRL_PIN(45, "NCLE"),
2608 - PINCTRL_PIN(46, "NALE"),
2609 - PINCTRL_PIN(47, "NDL0"),
2610 - PINCTRL_PIN(48, "NDL1"),
2611 - PINCTRL_PIN(49, "NDL2"),
2612 - PINCTRL_PIN(50, "NDL3"),
2613 - PINCTRL_PIN(51, "MDI_TP_P0"),
2614 - PINCTRL_PIN(52, "MDI_TN_P0"),
2615 - PINCTRL_PIN(53, "MDI_RP_P0"),
2616 - PINCTRL_PIN(54, "MDI_RN_P0"),
2617 - PINCTRL_PIN(55, "MDI_TP_P1"),
2618 - PINCTRL_PIN(56, "MDI_TN_P1"),
2619 - PINCTRL_PIN(57, "MDI_RP_P1"),
2620 - PINCTRL_PIN(58, "MDI_RN_P1"),
2621 - PINCTRL_PIN(59, "MDI_RP_P2"),
2622 - PINCTRL_PIN(60, "MDI_RN_P2"),
2623 - PINCTRL_PIN(61, "MDI_TP_P2"),
2624 - PINCTRL_PIN(62, "MDI_TN_P2"),
2625 - PINCTRL_PIN(63, "MDI_TP_P3"),
2626 - PINCTRL_PIN(64, "MDI_TN_P3"),
2627 - PINCTRL_PIN(65, "MDI_RP_P3"),
2628 - PINCTRL_PIN(66, "MDI_RN_P3"),
2629 - PINCTRL_PIN(67, "MDI_RP_P4"),
2630 - PINCTRL_PIN(68, "MDI_RN_P4"),
2631 - PINCTRL_PIN(69, "MDI_TP_P4"),
2632 - PINCTRL_PIN(70, "MDI_TN_P4"),
2633 - PINCTRL_PIN(71, "PMIC_SCL"),
2634 - PINCTRL_PIN(72, "PMIC_SDA"),
2635 - PINCTRL_PIN(73, "SPIC1_CLK"),
2636 - PINCTRL_PIN(74, "SPIC1_MOSI"),
2637 - PINCTRL_PIN(75, "SPIC1_MISO"),
2638 - PINCTRL_PIN(76, "SPIC1_CS"),
2639 - PINCTRL_PIN(77, "GPIO_D"),
2640 - PINCTRL_PIN(78, "WATCHDOG"),
2641 - PINCTRL_PIN(79, "RTS3_N"),
2642 - PINCTRL_PIN(80, "CTS3_N"),
2643 - PINCTRL_PIN(81, "TXD3"),
2644 - PINCTRL_PIN(82, "RXD3"),
2645 - PINCTRL_PIN(83, "PERST0_N"),
2646 - PINCTRL_PIN(84, "PERST1_N"),
2647 - PINCTRL_PIN(85, "WLED_N"),
2648 - PINCTRL_PIN(86, "EPHY_LED0_N"),
2649 - PINCTRL_PIN(87, "AUXIN0"),
2650 - PINCTRL_PIN(88, "AUXIN1"),
2651 - PINCTRL_PIN(89, "AUXIN2"),
2652 - PINCTRL_PIN(90, "AUXIN3"),
2653 - PINCTRL_PIN(91, "TXD4"),
2654 - PINCTRL_PIN(92, "RXD4"),
2655 - PINCTRL_PIN(93, "RTS4_N"),
2656 - PINCTRL_PIN(94, "CTS4_N"),
2657 - PINCTRL_PIN(95, "PWM1"),
2658 - PINCTRL_PIN(96, "PWM2"),
2659 - PINCTRL_PIN(97, "PWM3"),
2660 - PINCTRL_PIN(98, "PWM4"),
2661 - PINCTRL_PIN(99, "PWM5"),
2662 - PINCTRL_PIN(100, "PWM6"),
2663 - PINCTRL_PIN(101, "PWM7"),
2664 - PINCTRL_PIN(102, "GPIO_E"),
2665 +static const struct mtk_pin_desc mt7622_pins[] = {
2666 + MT7622_PIN(0, "GPIO_A"),
2667 + MT7622_PIN(1, "I2S1_IN"),
2668 + MT7622_PIN(2, "I2S1_OUT"),
2669 + MT7622_PIN(3, "I2S_BCLK"),
2670 + MT7622_PIN(4, "I2S_WS"),
2671 + MT7622_PIN(5, "I2S_MCLK"),
2672 + MT7622_PIN(6, "TXD0"),
2673 + MT7622_PIN(7, "RXD0"),
2674 + MT7622_PIN(8, "SPI_WP"),
2675 + MT7622_PIN(9, "SPI_HOLD"),
2676 + MT7622_PIN(10, "SPI_CLK"),
2677 + MT7622_PIN(11, "SPI_MOSI"),
2678 + MT7622_PIN(12, "SPI_MISO"),
2679 + MT7622_PIN(13, "SPI_CS"),
2680 + MT7622_PIN(14, "I2C_SDA"),
2681 + MT7622_PIN(15, "I2C_SCL"),
2682 + MT7622_PIN(16, "I2S2_IN"),
2683 + MT7622_PIN(17, "I2S3_IN"),
2684 + MT7622_PIN(18, "I2S4_IN"),
2685 + MT7622_PIN(19, "I2S2_OUT"),
2686 + MT7622_PIN(20, "I2S3_OUT"),
2687 + MT7622_PIN(21, "I2S4_OUT"),
2688 + MT7622_PIN(22, "GPIO_B"),
2689 + MT7622_PIN(23, "MDC"),
2690 + MT7622_PIN(24, "MDIO"),
2691 + MT7622_PIN(25, "G2_TXD0"),
2692 + MT7622_PIN(26, "G2_TXD1"),
2693 + MT7622_PIN(27, "G2_TXD2"),
2694 + MT7622_PIN(28, "G2_TXD3"),
2695 + MT7622_PIN(29, "G2_TXEN"),
2696 + MT7622_PIN(30, "G2_TXC"),
2697 + MT7622_PIN(31, "G2_RXD0"),
2698 + MT7622_PIN(32, "G2_RXD1"),
2699 + MT7622_PIN(33, "G2_RXD2"),
2700 + MT7622_PIN(34, "G2_RXD3"),
2701 + MT7622_PIN(35, "G2_RXDV"),
2702 + MT7622_PIN(36, "G2_RXC"),
2703 + MT7622_PIN(37, "NCEB"),
2704 + MT7622_PIN(38, "NWEB"),
2705 + MT7622_PIN(39, "NREB"),
2706 + MT7622_PIN(40, "NDL4"),
2707 + MT7622_PIN(41, "NDL5"),
2708 + MT7622_PIN(42, "NDL6"),
2709 + MT7622_PIN(43, "NDL7"),
2710 + MT7622_PIN(44, "NRB"),
2711 + MT7622_PIN(45, "NCLE"),
2712 + MT7622_PIN(46, "NALE"),
2713 + MT7622_PIN(47, "NDL0"),
2714 + MT7622_PIN(48, "NDL1"),
2715 + MT7622_PIN(49, "NDL2"),
2716 + MT7622_PIN(50, "NDL3"),
2717 + MT7622_PIN(51, "MDI_TP_P0"),
2718 + MT7622_PIN(52, "MDI_TN_P0"),
2719 + MT7622_PIN(53, "MDI_RP_P0"),
2720 + MT7622_PIN(54, "MDI_RN_P0"),
2721 + MT7622_PIN(55, "MDI_TP_P1"),
2722 + MT7622_PIN(56, "MDI_TN_P1"),
2723 + MT7622_PIN(57, "MDI_RP_P1"),
2724 + MT7622_PIN(58, "MDI_RN_P1"),
2725 + MT7622_PIN(59, "MDI_RP_P2"),
2726 + MT7622_PIN(60, "MDI_RN_P2"),
2727 + MT7622_PIN(61, "MDI_TP_P2"),
2728 + MT7622_PIN(62, "MDI_TN_P2"),
2729 + MT7622_PIN(63, "MDI_TP_P3"),
2730 + MT7622_PIN(64, "MDI_TN_P3"),
2731 + MT7622_PIN(65, "MDI_RP_P3"),
2732 + MT7622_PIN(66, "MDI_RN_P3"),
2733 + MT7622_PIN(67, "MDI_RP_P4"),
2734 + MT7622_PIN(68, "MDI_RN_P4"),
2735 + MT7622_PIN(69, "MDI_TP_P4"),
2736 + MT7622_PIN(70, "MDI_TN_P4"),
2737 + MT7622_PIN(71, "PMIC_SCL"),
2738 + MT7622_PIN(72, "PMIC_SDA"),
2739 + MT7622_PIN(73, "SPIC1_CLK"),
2740 + MT7622_PIN(74, "SPIC1_MOSI"),
2741 + MT7622_PIN(75, "SPIC1_MISO"),
2742 + MT7622_PIN(76, "SPIC1_CS"),
2743 + MT7622_PIN(77, "GPIO_D"),
2744 + MT7622_PIN(78, "WATCHDOG"),
2745 + MT7622_PIN(79, "RTS3_N"),
2746 + MT7622_PIN(80, "CTS3_N"),
2747 + MT7622_PIN(81, "TXD3"),
2748 + MT7622_PIN(82, "RXD3"),
2749 + MT7622_PIN(83, "PERST0_N"),
2750 + MT7622_PIN(84, "PERST1_N"),
2751 + MT7622_PIN(85, "WLED_N"),
2752 + MT7622_PIN(86, "EPHY_LED0_N"),
2753 + MT7622_PIN(87, "AUXIN0"),
2754 + MT7622_PIN(88, "AUXIN1"),
2755 + MT7622_PIN(89, "AUXIN2"),
2756 + MT7622_PIN(90, "AUXIN3"),
2757 + MT7622_PIN(91, "TXD4"),
2758 + MT7622_PIN(92, "RXD4"),
2759 + MT7622_PIN(93, "RTS4_N"),
2760 + MT7622_PIN(94, "CTS4_N"),
2761 + MT7622_PIN(95, "PWM1"),
2762 + MT7622_PIN(96, "PWM2"),
2763 + MT7622_PIN(97, "PWM3"),
2764 + MT7622_PIN(98, "PWM4"),
2765 + MT7622_PIN(99, "PWM5"),
2766 + MT7622_PIN(100, "PWM6"),
2767 + MT7622_PIN(101, "PWM7"),
2768 + MT7622_PIN(102, "GPIO_E"),
2769 };
2770
2771 /* List all groups consisting of these pins dedicated to the enablement of
2772 @@ -906,18 +749,6 @@ static const struct function_desc mt7622
2773 {"watchdog", mt7622_wdt_groups, ARRAY_SIZE(mt7622_wdt_groups)},
2774 };
2775
2776 -static const struct pinconf_generic_params mtk_custom_bindings[] = {
2777 - {"mediatek,tdsel", MTK_PIN_CONFIG_TDSEL, 0},
2778 - {"mediatek,rdsel", MTK_PIN_CONFIG_RDSEL, 0},
2779 -};
2780 -
2781 -#ifdef CONFIG_DEBUG_FS
2782 -static const struct pin_config_item mtk_conf_items[] = {
2783 - PCONFDUMP(MTK_PIN_CONFIG_TDSEL, "tdsel", NULL, true),
2784 - PCONFDUMP(MTK_PIN_CONFIG_RDSEL, "rdsel", NULL, true),
2785 -};
2786 -#endif
2787 -
2788 static const struct mtk_eint_hw mt7622_eint_hw = {
2789 .port_mask = 7,
2790 .ports = 7,
2791 @@ -934,830 +765,38 @@ static const struct mtk_pin_soc mt7622_d
2792 .funcs = mt7622_functions,
2793 .nfuncs = ARRAY_SIZE(mt7622_functions),
2794 .eint_hw = &mt7622_eint_hw,
2795 + .gpio_m = 1,
2796 + .ies_present = false,
2797 + .base_names = mtk_default_register_base_names,
2798 + .nbase_names = ARRAY_SIZE(mtk_default_register_base_names),
2799 + .bias_disable_set = mtk_pinconf_bias_disable_set,
2800 + .bias_disable_get = mtk_pinconf_bias_disable_get,
2801 + .bias_set = mtk_pinconf_bias_set,
2802 + .bias_get = mtk_pinconf_bias_get,
2803 + .drive_set = mtk_pinconf_drive_set,
2804 + .drive_get = mtk_pinconf_drive_get,
2805 };
2806
2807 -static void mtk_w32(struct mtk_pinctrl *pctl, u32 reg, u32 val)
2808 -{
2809 - writel_relaxed(val, pctl->base + reg);
2810 -}
2811 -
2812 -static u32 mtk_r32(struct mtk_pinctrl *pctl, u32 reg)
2813 -{
2814 - return readl_relaxed(pctl->base + reg);
2815 -}
2816 -
2817 -static void mtk_rmw(struct mtk_pinctrl *pctl, u32 reg, u32 mask, u32 set)
2818 -{
2819 - u32 val;
2820 -
2821 - val = mtk_r32(pctl, reg);
2822 - val &= ~mask;
2823 - val |= set;
2824 - mtk_w32(pctl, reg, val);
2825 -}
2826 -
2827 -static int mtk_hw_pin_field_lookup(struct mtk_pinctrl *hw, int pin,
2828 - const struct mtk_pin_reg_calc *rc,
2829 - struct mtk_pin_field *pfd)
2830 -{
2831 - const struct mtk_pin_field_calc *c, *e;
2832 - u32 bits;
2833 -
2834 - c = rc->range;
2835 - e = c + rc->nranges;
2836 -
2837 - while (c < e) {
2838 - if (pin >= c->s_pin && pin <= c->e_pin)
2839 - break;
2840 - c++;
2841 - }
2842 -
2843 - if (c >= e) {
2844 - dev_err(hw->dev, "Out of range for pin = %d\n", pin);
2845 - return -EINVAL;
2846 - }
2847 -
2848 - /* Caculated bits as the overall offset the pin is located at */
2849 - bits = c->s_bit + (pin - c->s_pin) * (c->x_bits);
2850 -
2851 - /* Fill pfd from bits and 32-bit register applied is assumed */
2852 - pfd->offset = c->s_addr + c->x_addrs * (bits / 32);
2853 - pfd->bitpos = bits % 32;
2854 - pfd->mask = (1 << c->x_bits) - 1;
2855 -
2856 - /* pfd->next is used for indicating that bit wrapping-around happens
2857 - * which requires the manipulation for bit 0 starting in the next
2858 - * register to form the complete field read/write.
2859 - */
2860 - pfd->next = pfd->bitpos + c->x_bits - 1 > 31 ? c->x_addrs : 0;
2861 -
2862 - return 0;
2863 -}
2864 -
2865 -static int mtk_hw_pin_field_get(struct mtk_pinctrl *hw, int pin,
2866 - int field, struct mtk_pin_field *pfd)
2867 -{
2868 - const struct mtk_pin_reg_calc *rc;
2869 -
2870 - if (field < 0 || field >= PINCTRL_PIN_REG_MAX) {
2871 - dev_err(hw->dev, "Invalid Field %d\n", field);
2872 - return -EINVAL;
2873 - }
2874 -
2875 - if (hw->soc->reg_cal && hw->soc->reg_cal[field].range) {
2876 - rc = &hw->soc->reg_cal[field];
2877 - } else {
2878 - dev_err(hw->dev, "Undefined range for field %d\n", field);
2879 - return -EINVAL;
2880 - }
2881 -
2882 - return mtk_hw_pin_field_lookup(hw, pin, rc, pfd);
2883 -}
2884 -
2885 -static void mtk_hw_bits_part(struct mtk_pin_field *pf, int *h, int *l)
2886 -{
2887 - *l = 32 - pf->bitpos;
2888 - *h = get_count_order(pf->mask) - *l;
2889 -}
2890 -
2891 -static void mtk_hw_write_cross_field(struct mtk_pinctrl *hw,
2892 - struct mtk_pin_field *pf, int value)
2893 -{
2894 - int nbits_l, nbits_h;
2895 -
2896 - mtk_hw_bits_part(pf, &nbits_h, &nbits_l);
2897 -
2898 - mtk_rmw(hw, pf->offset, pf->mask << pf->bitpos,
2899 - (value & pf->mask) << pf->bitpos);
2900 -
2901 - mtk_rmw(hw, pf->offset + pf->next, BIT(nbits_h) - 1,
2902 - (value & pf->mask) >> nbits_l);
2903 -}
2904 -
2905 -static void mtk_hw_read_cross_field(struct mtk_pinctrl *hw,
2906 - struct mtk_pin_field *pf, int *value)
2907 -{
2908 - int nbits_l, nbits_h, h, l;
2909 -
2910 - mtk_hw_bits_part(pf, &nbits_h, &nbits_l);
2911 -
2912 - l = (mtk_r32(hw, pf->offset) >> pf->bitpos) & (BIT(nbits_l) - 1);
2913 - h = (mtk_r32(hw, pf->offset + pf->next)) & (BIT(nbits_h) - 1);
2914 -
2915 - *value = (h << nbits_l) | l;
2916 -}
2917 -
2918 -static int mtk_hw_set_value(struct mtk_pinctrl *hw, int pin, int field,
2919 - int value)
2920 -{
2921 - struct mtk_pin_field pf;
2922 - int err;
2923 -
2924 - err = mtk_hw_pin_field_get(hw, pin, field, &pf);
2925 - if (err)
2926 - return err;
2927 -
2928 - if (!pf.next)
2929 - mtk_rmw(hw, pf.offset, pf.mask << pf.bitpos,
2930 - (value & pf.mask) << pf.bitpos);
2931 - else
2932 - mtk_hw_write_cross_field(hw, &pf, value);
2933 -
2934 - return 0;
2935 -}
2936 -
2937 -static int mtk_hw_get_value(struct mtk_pinctrl *hw, int pin, int field,
2938 - int *value)
2939 -{
2940 - struct mtk_pin_field pf;
2941 - int err;
2942 -
2943 - err = mtk_hw_pin_field_get(hw, pin, field, &pf);
2944 - if (err)
2945 - return err;
2946 -
2947 - if (!pf.next)
2948 - *value = (mtk_r32(hw, pf.offset) >> pf.bitpos) & pf.mask;
2949 - else
2950 - mtk_hw_read_cross_field(hw, &pf, value);
2951 -
2952 - return 0;
2953 -}
2954 -
2955 -static int mtk_pinmux_set_mux(struct pinctrl_dev *pctldev,
2956 - unsigned int selector, unsigned int group)
2957 -{
2958 - struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
2959 - struct function_desc *func;
2960 - struct group_desc *grp;
2961 - int i;
2962 -
2963 - func = pinmux_generic_get_function(pctldev, selector);
2964 - if (!func)
2965 - return -EINVAL;
2966 -
2967 - grp = pinctrl_generic_get_group(pctldev, group);
2968 - if (!grp)
2969 - return -EINVAL;
2970 -
2971 - dev_dbg(pctldev->dev, "enable function %s group %s\n",
2972 - func->name, grp->name);
2973 -
2974 - for (i = 0; i < grp->num_pins; i++) {
2975 - int *pin_modes = grp->data;
2976 -
2977 - mtk_hw_set_value(hw, grp->pins[i], PINCTRL_PIN_REG_MODE,
2978 - pin_modes[i]);
2979 - }
2980 -
2981 - return 0;
2982 -}
2983 -
2984 -static int mtk_pinmux_gpio_request_enable(struct pinctrl_dev *pctldev,
2985 - struct pinctrl_gpio_range *range,
2986 - unsigned int pin)
2987 -{
2988 - struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
2989 -
2990 - return mtk_hw_set_value(hw, pin, PINCTRL_PIN_REG_MODE, MTK_GPIO_MODE);
2991 -}
2992 -
2993 -static int mtk_pinmux_gpio_set_direction(struct pinctrl_dev *pctldev,
2994 - struct pinctrl_gpio_range *range,
2995 - unsigned int pin, bool input)
2996 -{
2997 - struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
2998 -
2999 - /* hardware would take 0 as input direction */
3000 - return mtk_hw_set_value(hw, pin, PINCTRL_PIN_REG_DIR, !input);
3001 -}
3002 -
3003 -static int mtk_pinconf_get(struct pinctrl_dev *pctldev,
3004 - unsigned int pin, unsigned long *config)
3005 -{
3006 - struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
3007 - u32 param = pinconf_to_config_param(*config);
3008 - int val, val2, err, reg, ret = 1;
3009 -
3010 - switch (param) {
3011 - case PIN_CONFIG_BIAS_DISABLE:
3012 - err = mtk_hw_get_value(hw, pin, PINCTRL_PIN_REG_PU, &val);
3013 - if (err)
3014 - return err;
3015 -
3016 - err = mtk_hw_get_value(hw, pin, PINCTRL_PIN_REG_PD, &val2);
3017 - if (err)
3018 - return err;
3019 -
3020 - if (val || val2)
3021 - return -EINVAL;
3022 -
3023 - break;
3024 - case PIN_CONFIG_BIAS_PULL_UP:
3025 - case PIN_CONFIG_BIAS_PULL_DOWN:
3026 - case PIN_CONFIG_SLEW_RATE:
3027 - reg = (param == PIN_CONFIG_BIAS_PULL_UP) ?
3028 - PINCTRL_PIN_REG_PU :
3029 - (param == PIN_CONFIG_BIAS_PULL_DOWN) ?
3030 - PINCTRL_PIN_REG_PD : PINCTRL_PIN_REG_SR;
3031 -
3032 - err = mtk_hw_get_value(hw, pin, reg, &val);
3033 - if (err)
3034 - return err;
3035 -
3036 - if (!val)
3037 - return -EINVAL;
3038 -
3039 - break;
3040 - case PIN_CONFIG_INPUT_ENABLE:
3041 - case PIN_CONFIG_OUTPUT_ENABLE:
3042 - err = mtk_hw_get_value(hw, pin, PINCTRL_PIN_REG_DIR, &val);
3043 - if (err)
3044 - return err;
3045 -
3046 - /* HW takes input mode as zero; output mode as non-zero */
3047 - if ((val && param == PIN_CONFIG_INPUT_ENABLE) ||
3048 - (!val && param == PIN_CONFIG_OUTPUT_ENABLE))
3049 - return -EINVAL;
3050 -
3051 - break;
3052 - case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
3053 - err = mtk_hw_get_value(hw, pin, PINCTRL_PIN_REG_DIR, &val);
3054 - if (err)
3055 - return err;
3056 -
3057 - err = mtk_hw_get_value(hw, pin, PINCTRL_PIN_REG_SMT, &val2);
3058 - if (err)
3059 - return err;
3060 -
3061 - if (val || !val2)
3062 - return -EINVAL;
3063 -
3064 - break;
3065 - case PIN_CONFIG_DRIVE_STRENGTH:
3066 - err = mtk_hw_get_value(hw, pin, PINCTRL_PIN_REG_E4, &val);
3067 - if (err)
3068 - return err;
3069 -
3070 - err = mtk_hw_get_value(hw, pin, PINCTRL_PIN_REG_E8, &val2);
3071 - if (err)
3072 - return err;
3073 -
3074 - /* 4mA when (e8, e4) = (0, 0); 8mA when (e8, e4) = (0, 1)
3075 - * 12mA when (e8, e4) = (1, 0); 16mA when (e8, e4) = (1, 1)
3076 - */
3077 - ret = ((val2 << 1) + val + 1) * 4;
3078 -
3079 - break;
3080 - case MTK_PIN_CONFIG_TDSEL:
3081 - case MTK_PIN_CONFIG_RDSEL:
3082 - reg = (param == MTK_PIN_CONFIG_TDSEL) ?
3083 - PINCTRL_PIN_REG_TDSEL : PINCTRL_PIN_REG_RDSEL;
3084 -
3085 - err = mtk_hw_get_value(hw, pin, reg, &val);
3086 - if (err)
3087 - return err;
3088 -
3089 - ret = val;
3090 -
3091 - break;
3092 - default:
3093 - return -ENOTSUPP;
3094 - }
3095 -
3096 - *config = pinconf_to_config_packed(param, ret);
3097 -
3098 - return 0;
3099 -}
3100 -
3101 -static int mtk_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
3102 - unsigned long *configs, unsigned int num_configs)
3103 -{
3104 - struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
3105 - u32 reg, param, arg;
3106 - int cfg, err = 0;
3107 -
3108 - for (cfg = 0; cfg < num_configs; cfg++) {
3109 - param = pinconf_to_config_param(configs[cfg]);
3110 - arg = pinconf_to_config_argument(configs[cfg]);
3111 -
3112 - switch (param) {
3113 - case PIN_CONFIG_BIAS_DISABLE:
3114 - case PIN_CONFIG_BIAS_PULL_UP:
3115 - case PIN_CONFIG_BIAS_PULL_DOWN:
3116 - arg = (param == PIN_CONFIG_BIAS_DISABLE) ? 0 :
3117 - (param == PIN_CONFIG_BIAS_PULL_UP) ? 1 : 2;
3118 -
3119 - err = mtk_hw_set_value(hw, pin, PINCTRL_PIN_REG_PU,
3120 - arg & 1);
3121 - if (err)
3122 - goto err;
3123 -
3124 - err = mtk_hw_set_value(hw, pin, PINCTRL_PIN_REG_PD,
3125 - !!(arg & 2));
3126 - if (err)
3127 - goto err;
3128 - break;
3129 - case PIN_CONFIG_OUTPUT_ENABLE:
3130 - err = mtk_hw_set_value(hw, pin, PINCTRL_PIN_REG_SMT,
3131 - MTK_DISABLE);
3132 - if (err)
3133 - goto err;
3134 - /* else: fall through */
3135 - case PIN_CONFIG_INPUT_ENABLE:
3136 - case PIN_CONFIG_SLEW_RATE:
3137 - reg = (param == PIN_CONFIG_SLEW_RATE) ?
3138 - PINCTRL_PIN_REG_SR : PINCTRL_PIN_REG_DIR;
3139 -
3140 - arg = (param == PIN_CONFIG_INPUT_ENABLE) ? 0 :
3141 - (param == PIN_CONFIG_OUTPUT_ENABLE) ? 1 : arg;
3142 - err = mtk_hw_set_value(hw, pin, reg, arg);
3143 - if (err)
3144 - goto err;
3145 -
3146 - break;
3147 - case PIN_CONFIG_OUTPUT:
3148 - err = mtk_hw_set_value(hw, pin, PINCTRL_PIN_REG_DIR,
3149 - MTK_OUTPUT);
3150 - if (err)
3151 - goto err;
3152 -
3153 - err = mtk_hw_set_value(hw, pin, PINCTRL_PIN_REG_DO,
3154 - arg);
3155 - if (err)
3156 - goto err;
3157 - break;
3158 - case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
3159 - /* arg = 1: Input mode & SMT enable ;
3160 - * arg = 0: Output mode & SMT disable
3161 - */
3162 - arg = arg ? 2 : 1;
3163 - err = mtk_hw_set_value(hw, pin, PINCTRL_PIN_REG_DIR,
3164 - arg & 1);
3165 - if (err)
3166 - goto err;
3167 -
3168 - err = mtk_hw_set_value(hw, pin, PINCTRL_PIN_REG_SMT,
3169 - !!(arg & 2));
3170 - if (err)
3171 - goto err;
3172 - break;
3173 - case PIN_CONFIG_DRIVE_STRENGTH:
3174 - /* 4mA when (e8, e4) = (0, 0);
3175 - * 8mA when (e8, e4) = (0, 1);
3176 - * 12mA when (e8, e4) = (1, 0);
3177 - * 16mA when (e8, e4) = (1, 1)
3178 - */
3179 - if (!(arg % 4) && (arg >= 4 && arg <= 16)) {
3180 - arg = arg / 4 - 1;
3181 - err = mtk_hw_set_value(hw, pin,
3182 - PINCTRL_PIN_REG_E4,
3183 - arg & 0x1);
3184 - if (err)
3185 - goto err;
3186 -
3187 - err = mtk_hw_set_value(hw, pin,
3188 - PINCTRL_PIN_REG_E8,
3189 - (arg & 0x2) >> 1);
3190 - if (err)
3191 - goto err;
3192 - } else {
3193 - err = -ENOTSUPP;
3194 - }
3195 - break;
3196 - case MTK_PIN_CONFIG_TDSEL:
3197 - case MTK_PIN_CONFIG_RDSEL:
3198 - reg = (param == MTK_PIN_CONFIG_TDSEL) ?
3199 - PINCTRL_PIN_REG_TDSEL : PINCTRL_PIN_REG_RDSEL;
3200 -
3201 - err = mtk_hw_set_value(hw, pin, reg, arg);
3202 - if (err)
3203 - goto err;
3204 - break;
3205 - default:
3206 - err = -ENOTSUPP;
3207 - }
3208 - }
3209 -err:
3210 - return err;
3211 -}
3212 -
3213 -static int mtk_pinconf_group_get(struct pinctrl_dev *pctldev,
3214 - unsigned int group, unsigned long *config)
3215 -{
3216 - const unsigned int *pins;
3217 - unsigned int i, npins, old = 0;
3218 - int ret;
3219 -
3220 - ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins);
3221 - if (ret)
3222 - return ret;
3223 -
3224 - for (i = 0; i < npins; i++) {
3225 - if (mtk_pinconf_get(pctldev, pins[i], config))
3226 - return -ENOTSUPP;
3227 -
3228 - /* configs do not match between two pins */
3229 - if (i && old != *config)
3230 - return -ENOTSUPP;
3231 -
3232 - old = *config;
3233 - }
3234 -
3235 - return 0;
3236 -}
3237 -
3238 -static int mtk_pinconf_group_set(struct pinctrl_dev *pctldev,
3239 - unsigned int group, unsigned long *configs,
3240 - unsigned int num_configs)
3241 -{
3242 - const unsigned int *pins;
3243 - unsigned int i, npins;
3244 - int ret;
3245 -
3246 - ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins);
3247 - if (ret)
3248 - return ret;
3249 -
3250 - for (i = 0; i < npins; i++) {
3251 - ret = mtk_pinconf_set(pctldev, pins[i], configs, num_configs);
3252 - if (ret)
3253 - return ret;
3254 - }
3255 -
3256 - return 0;
3257 -}
3258 -
3259 -static const struct pinctrl_ops mtk_pctlops = {
3260 - .get_groups_count = pinctrl_generic_get_group_count,
3261 - .get_group_name = pinctrl_generic_get_group_name,
3262 - .get_group_pins = pinctrl_generic_get_group_pins,
3263 - .dt_node_to_map = pinconf_generic_dt_node_to_map_all,
3264 - .dt_free_map = pinconf_generic_dt_free_map,
3265 -};
3266 -
3267 -static const struct pinmux_ops mtk_pmxops = {
3268 - .get_functions_count = pinmux_generic_get_function_count,
3269 - .get_function_name = pinmux_generic_get_function_name,
3270 - .get_function_groups = pinmux_generic_get_function_groups,
3271 - .set_mux = mtk_pinmux_set_mux,
3272 - .gpio_request_enable = mtk_pinmux_gpio_request_enable,
3273 - .gpio_set_direction = mtk_pinmux_gpio_set_direction,
3274 - .strict = true,
3275 -};
3276 -
3277 -static const struct pinconf_ops mtk_confops = {
3278 - .is_generic = true,
3279 - .pin_config_get = mtk_pinconf_get,
3280 - .pin_config_set = mtk_pinconf_set,
3281 - .pin_config_group_get = mtk_pinconf_group_get,
3282 - .pin_config_group_set = mtk_pinconf_group_set,
3283 - .pin_config_config_dbg_show = pinconf_generic_dump_config,
3284 -};
3285 -
3286 -static struct pinctrl_desc mtk_desc = {
3287 - .name = PINCTRL_PINCTRL_DEV,
3288 - .pctlops = &mtk_pctlops,
3289 - .pmxops = &mtk_pmxops,
3290 - .confops = &mtk_confops,
3291 - .owner = THIS_MODULE,
3292 -};
3293 -
3294 -static int mtk_gpio_get(struct gpio_chip *chip, unsigned int gpio)
3295 -{
3296 - struct mtk_pinctrl *hw = gpiochip_get_data(chip);
3297 - int value, err;
3298 -
3299 - err = mtk_hw_get_value(hw, gpio, PINCTRL_PIN_REG_DI, &value);
3300 - if (err)
3301 - return err;
3302 -
3303 - return !!value;
3304 -}
3305 -
3306 -static void mtk_gpio_set(struct gpio_chip *chip, unsigned int gpio, int value)
3307 -{
3308 - struct mtk_pinctrl *hw = gpiochip_get_data(chip);
3309 -
3310 - mtk_hw_set_value(hw, gpio, PINCTRL_PIN_REG_DO, !!value);
3311 -}
3312 -
3313 -static int mtk_gpio_direction_input(struct gpio_chip *chip, unsigned int gpio)
3314 -{
3315 - return pinctrl_gpio_direction_input(chip->base + gpio);
3316 -}
3317 -
3318 -static int mtk_gpio_direction_output(struct gpio_chip *chip, unsigned int gpio,
3319 - int value)
3320 -{
3321 - mtk_gpio_set(chip, gpio, value);
3322 -
3323 - return pinctrl_gpio_direction_output(chip->base + gpio);
3324 -}
3325 -
3326 -static int mtk_gpio_to_irq(struct gpio_chip *chip, unsigned int offset)
3327 -{
3328 - struct mtk_pinctrl *hw = gpiochip_get_data(chip);
3329 - unsigned long eint_n;
3330 -
3331 - if (!hw->eint)
3332 - return -ENOTSUPP;
3333 -
3334 - eint_n = offset;
3335 -
3336 - return mtk_eint_find_irq(hw->eint, eint_n);
3337 -}
3338 -
3339 -static int mtk_gpio_set_config(struct gpio_chip *chip, unsigned int offset,
3340 - unsigned long config)
3341 -{
3342 - struct mtk_pinctrl *hw = gpiochip_get_data(chip);
3343 - unsigned long eint_n;
3344 - u32 debounce;
3345 -
3346 - if (!hw->eint ||
3347 - pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE)
3348 - return -ENOTSUPP;
3349 -
3350 - debounce = pinconf_to_config_argument(config);
3351 - eint_n = offset;
3352 -
3353 - return mtk_eint_set_debounce(hw->eint, eint_n, debounce);
3354 -}
3355 -
3356 -static int mtk_build_gpiochip(struct mtk_pinctrl *hw, struct device_node *np)
3357 -{
3358 - struct gpio_chip *chip = &hw->chip;
3359 - int ret;
3360 -
3361 - chip->label = PINCTRL_PINCTRL_DEV;
3362 - chip->parent = hw->dev;
3363 - chip->request = gpiochip_generic_request;
3364 - chip->free = gpiochip_generic_free;
3365 - chip->direction_input = mtk_gpio_direction_input;
3366 - chip->direction_output = mtk_gpio_direction_output;
3367 - chip->get = mtk_gpio_get;
3368 - chip->set = mtk_gpio_set;
3369 - chip->to_irq = mtk_gpio_to_irq,
3370 - chip->set_config = mtk_gpio_set_config,
3371 - chip->base = -1;
3372 - chip->ngpio = hw->soc->npins;
3373 - chip->of_node = np;
3374 - chip->of_gpio_n_cells = 2;
3375 -
3376 - ret = gpiochip_add_data(chip, hw);
3377 - if (ret < 0)
3378 - return ret;
3379 -
3380 - /* Just for backward compatible for these old pinctrl nodes without
3381 - * "gpio-ranges" property. Otherwise, called directly from a
3382 - * DeviceTree-supported pinctrl driver is DEPRECATED.
3383 - * Please see Section 2.1 of
3384 - * Documentation/devicetree/bindings/gpio/gpio.txt on how to
3385 - * bind pinctrl and gpio drivers via the "gpio-ranges" property.
3386 - */
3387 - if (!of_find_property(np, "gpio-ranges", NULL)) {
3388 - ret = gpiochip_add_pin_range(chip, dev_name(hw->dev), 0, 0,
3389 - chip->ngpio);
3390 - if (ret < 0) {
3391 - gpiochip_remove(chip);
3392 - return ret;
3393 - }
3394 - }
3395 -
3396 - return 0;
3397 -}
3398 -
3399 -static int mtk_build_groups(struct mtk_pinctrl *hw)
3400 -{
3401 - int err, i;
3402 -
3403 - for (i = 0; i < hw->soc->ngrps; i++) {
3404 - const struct group_desc *group = hw->soc->grps + i;
3405 -
3406 - err = pinctrl_generic_add_group(hw->pctrl, group->name,
3407 - group->pins, group->num_pins,
3408 - group->data);
3409 - if (err < 0) {
3410 - dev_err(hw->dev, "Failed to register group %s\n",
3411 - group->name);
3412 - return err;
3413 - }
3414 - }
3415 -
3416 - return 0;
3417 -}
3418 -
3419 -static int mtk_build_functions(struct mtk_pinctrl *hw)
3420 -{
3421 - int i, err;
3422 -
3423 - for (i = 0; i < hw->soc->nfuncs ; i++) {
3424 - const struct function_desc *func = hw->soc->funcs + i;
3425 -
3426 - err = pinmux_generic_add_function(hw->pctrl, func->name,
3427 - func->group_names,
3428 - func->num_group_names,
3429 - func->data);
3430 - if (err < 0) {
3431 - dev_err(hw->dev, "Failed to register function %s\n",
3432 - func->name);
3433 - return err;
3434 - }
3435 - }
3436 -
3437 - return 0;
3438 -}
3439 -
3440 -static int mtk_xt_get_gpio_n(void *data, unsigned long eint_n,
3441 - unsigned int *gpio_n,
3442 - struct gpio_chip **gpio_chip)
3443 -{
3444 - struct mtk_pinctrl *hw = (struct mtk_pinctrl *)data;
3445 -
3446 - *gpio_chip = &hw->chip;
3447 - *gpio_n = eint_n;
3448 -
3449 - return 0;
3450 -}
3451 -
3452 -static int mtk_xt_get_gpio_state(void *data, unsigned long eint_n)
3453 -{
3454 - struct mtk_pinctrl *hw = (struct mtk_pinctrl *)data;
3455 - struct gpio_chip *gpio_chip;
3456 - unsigned int gpio_n;
3457 - int err;
3458 -
3459 - err = mtk_xt_get_gpio_n(hw, eint_n, &gpio_n, &gpio_chip);
3460 - if (err)
3461 - return err;
3462 -
3463 - return mtk_gpio_get(gpio_chip, gpio_n);
3464 -}
3465 -
3466 -static int mtk_xt_set_gpio_as_eint(void *data, unsigned long eint_n)
3467 -{
3468 - struct mtk_pinctrl *hw = (struct mtk_pinctrl *)data;
3469 - struct gpio_chip *gpio_chip;
3470 - unsigned int gpio_n;
3471 - int err;
3472 -
3473 - err = mtk_xt_get_gpio_n(hw, eint_n, &gpio_n, &gpio_chip);
3474 - if (err)
3475 - return err;
3476 -
3477 - err = mtk_hw_set_value(hw, gpio_n, PINCTRL_PIN_REG_MODE,
3478 - MTK_GPIO_MODE);
3479 - if (err)
3480 - return err;
3481 -
3482 - err = mtk_hw_set_value(hw, gpio_n, PINCTRL_PIN_REG_DIR, MTK_INPUT);
3483 - if (err)
3484 - return err;
3485 -
3486 - err = mtk_hw_set_value(hw, gpio_n, PINCTRL_PIN_REG_SMT, MTK_ENABLE);
3487 - if (err)
3488 - return err;
3489 -
3490 - return 0;
3491 -}
3492 -
3493 -static const struct mtk_eint_xt mtk_eint_xt = {
3494 - .get_gpio_n = mtk_xt_get_gpio_n,
3495 - .get_gpio_state = mtk_xt_get_gpio_state,
3496 - .set_gpio_as_eint = mtk_xt_set_gpio_as_eint,
3497 -};
3498 -
3499 -static int
3500 -mtk_build_eint(struct mtk_pinctrl *hw, struct platform_device *pdev)
3501 -{
3502 - struct device_node *np = pdev->dev.of_node;
3503 - struct resource *res;
3504 -
3505 - if (!IS_ENABLED(CONFIG_EINT_MTK))
3506 - return 0;
3507 -
3508 - if (!of_property_read_bool(np, "interrupt-controller"))
3509 - return -ENODEV;
3510 -
3511 - hw->eint = devm_kzalloc(hw->dev, sizeof(*hw->eint), GFP_KERNEL);
3512 - if (!hw->eint)
3513 - return -ENOMEM;
3514 -
3515 - res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "eint");
3516 - if (!res) {
3517 - dev_err(&pdev->dev, "Unable to get eint resource\n");
3518 - return -ENODEV;
3519 - }
3520 -
3521 - hw->eint->base = devm_ioremap_resource(&pdev->dev, res);
3522 - if (IS_ERR(hw->eint->base))
3523 - return PTR_ERR(hw->eint->base);
3524 -
3525 - hw->eint->irq = irq_of_parse_and_map(np, 0);
3526 - if (!hw->eint->irq)
3527 - return -EINVAL;
3528 -
3529 - hw->eint->dev = &pdev->dev;
3530 - hw->eint->hw = hw->soc->eint_hw;
3531 - hw->eint->pctl = hw;
3532 - hw->eint->gpio_xlate = &mtk_eint_xt;
3533 -
3534 - return mtk_eint_do_init(hw->eint);
3535 -}
3536 -
3537 -static const struct of_device_id mtk_pinctrl_of_match[] = {
3538 - { .compatible = "mediatek,mt7622-pinctrl", .data = &mt7622_data},
3539 +static const struct of_device_id mt7622_pinctrl_of_match[] = {
3540 + { .compatible = "mediatek,mt7622-pinctrl", },
3541 { }
3542 };
3543
3544 -static int mtk_pinctrl_probe(struct platform_device *pdev)
3545 +static int mt7622_pinctrl_probe(struct platform_device *pdev)
3546 {
3547 - struct resource *res;
3548 - struct mtk_pinctrl *hw;
3549 - const struct of_device_id *of_id =
3550 - of_match_device(mtk_pinctrl_of_match, &pdev->dev);
3551 - int err;
3552 -
3553 - hw = devm_kzalloc(&pdev->dev, sizeof(*hw), GFP_KERNEL);
3554 - if (!hw)
3555 - return -ENOMEM;
3556 -
3557 - hw->soc = of_id->data;
3558 -
3559 - res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3560 - if (!res) {
3561 - dev_err(&pdev->dev, "missing IO resource\n");
3562 - return -ENXIO;
3563 - }
3564 -
3565 - hw->dev = &pdev->dev;
3566 - hw->base = devm_ioremap_resource(&pdev->dev, res);
3567 - if (IS_ERR(hw->base))
3568 - return PTR_ERR(hw->base);
3569 -
3570 - /* Setup pins descriptions per SoC types */
3571 - mtk_desc.pins = hw->soc->pins;
3572 - mtk_desc.npins = hw->soc->npins;
3573 - mtk_desc.num_custom_params = ARRAY_SIZE(mtk_custom_bindings);
3574 - mtk_desc.custom_params = mtk_custom_bindings;
3575 -#ifdef CONFIG_DEBUG_FS
3576 - mtk_desc.custom_conf_items = mtk_conf_items;
3577 -#endif
3578 -
3579 - err = devm_pinctrl_register_and_init(&pdev->dev, &mtk_desc, hw,
3580 - &hw->pctrl);
3581 - if (err)
3582 - return err;
3583 -
3584 - /* Setup groups descriptions per SoC types */
3585 - err = mtk_build_groups(hw);
3586 - if (err) {
3587 - dev_err(&pdev->dev, "Failed to build groups\n");
3588 - return err;
3589 - }
3590 -
3591 - /* Setup functions descriptions per SoC types */
3592 - err = mtk_build_functions(hw);
3593 - if (err) {
3594 - dev_err(&pdev->dev, "Failed to build functions\n");
3595 - return err;
3596 - }
3597 -
3598 - /* For able to make pinctrl_claim_hogs, we must not enable pinctrl
3599 - * until all groups and functions are being added one.
3600 - */
3601 - err = pinctrl_enable(hw->pctrl);
3602 - if (err)
3603 - return err;
3604 -
3605 - err = mtk_build_eint(hw, pdev);
3606 - if (err)
3607 - dev_warn(&pdev->dev,
3608 - "Failed to add EINT, but pinctrl still can work\n");
3609 -
3610 - /* Build gpiochip should be after pinctrl_enable is done */
3611 - err = mtk_build_gpiochip(hw, pdev->dev.of_node);
3612 - if (err) {
3613 - dev_err(&pdev->dev, "Failed to add gpio_chip\n");
3614 - return err;
3615 - }
3616 -
3617 - platform_set_drvdata(pdev, hw);
3618 -
3619 - return 0;
3620 + return mtk_moore_pinctrl_probe(pdev, &mt7622_data);
3621 }
3622
3623 -static struct platform_driver mtk_pinctrl_driver = {
3624 +static struct platform_driver mt7622_pinctrl_driver = {
3625 .driver = {
3626 - .name = "mtk-pinctrl",
3627 - .of_match_table = mtk_pinctrl_of_match,
3628 + .name = "mt7622-pinctrl",
3629 + .of_match_table = mt7622_pinctrl_of_match,
3630 },
3631 - .probe = mtk_pinctrl_probe,
3632 + .probe = mt7622_pinctrl_probe,
3633 };
3634
3635 -static int __init mtk_pinctrl_init(void)
3636 +static int __init mt7622_pinctrl_init(void)
3637 {
3638 - return platform_driver_register(&mtk_pinctrl_driver);
3639 + return platform_driver_register(&mt7622_pinctrl_driver);
3640 }
3641 -arch_initcall(mtk_pinctrl_init);
3642 +arch_initcall(mt7622_pinctrl_init);
3643 --- /dev/null
3644 +++ b/drivers/pinctrl/mediatek/pinctrl-mt7623.c
3645 @@ -0,0 +1,1441 @@
3646 +// SPDX-License-Identifier: GPL-2.0
3647 +/*
3648 + * The MT7623 driver based on Linux generic pinctrl binding.
3649 + *
3650 + * Copyright (C) 2015 - 2018 MediaTek Inc.
3651 + * Author: Biao Huang <biao.huang@mediatek.com>
3652 + * Ryder Lee <ryder.lee@mediatek.com>
3653 + * Sean Wang <sean.wang@mediatek.com>
3654 + */
3655 +
3656 +#include "pinctrl-moore.h"
3657 +
3658 +#define PIN_BOND_REG0 0xb10
3659 +#define PIN_BOND_REG1 0xf20
3660 +#define PIN_BOND_REG2 0xef0
3661 +#define BOND_PCIE_CLR (0x77 << 3)
3662 +#define BOND_I2S_CLR 0x3
3663 +#define BOND_MSDC0E_CLR 0x1
3664 +
3665 +#define PIN_FIELD15(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits) \
3666 + PIN_FIELD_CALC(_s_pin, _e_pin, 0, _s_addr, _x_addrs, _s_bit, \
3667 + _x_bits, 15, false)
3668 +
3669 +#define PIN_FIELD16(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits) \
3670 + PIN_FIELD_CALC(_s_pin, _e_pin, 0, _s_addr, _x_addrs, _s_bit, \
3671 + _x_bits, 16, 0)
3672 +
3673 +#define PINS_FIELD16(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits) \
3674 + PIN_FIELD_CALC(_s_pin, _e_pin, 0, _s_addr, _x_addrs, _s_bit, \
3675 + _x_bits, 16, 1)
3676 +
3677 +#define MT7623_PIN(_number, _name, _eint_n, _drv_grp) \
3678 + MTK_PIN(_number, _name, 0, _eint_n, _drv_grp)
3679 +
3680 +static const struct mtk_pin_field_calc mt7623_pin_mode_range[] = {
3681 + PIN_FIELD15(0, 278, 0x760, 0x10, 0, 3),
3682 +};
3683 +
3684 +static const struct mtk_pin_field_calc mt7623_pin_dir_range[] = {
3685 + PIN_FIELD16(0, 175, 0x0, 0x10, 0, 1),
3686 + PIN_FIELD16(176, 278, 0xc0, 0x10, 0, 1),
3687 +};
3688 +
3689 +static const struct mtk_pin_field_calc mt7623_pin_di_range[] = {
3690 + PIN_FIELD16(0, 278, 0x630, 0x10, 0, 1),
3691 +};
3692 +
3693 +static const struct mtk_pin_field_calc mt7623_pin_do_range[] = {
3694 + PIN_FIELD16(0, 278, 0x500, 0x10, 0, 1),
3695 +};
3696 +
3697 +static const struct mtk_pin_field_calc mt7623_pin_ies_range[] = {
3698 + PINS_FIELD16(0, 6, 0xb20, 0x10, 0, 1),
3699 + PINS_FIELD16(7, 9, 0xb20, 0x10, 1, 1),
3700 + PINS_FIELD16(10, 13, 0xb30, 0x10, 3, 1),
3701 + PINS_FIELD16(14, 15, 0xb30, 0x10, 13, 1),
3702 + PINS_FIELD16(16, 17, 0xb40, 0x10, 7, 1),
3703 + PINS_FIELD16(18, 29, 0xb40, 0x10, 13, 1),
3704 + PINS_FIELD16(30, 32, 0xb40, 0x10, 7, 1),
3705 + PINS_FIELD16(33, 37, 0xb40, 0x10, 13, 1),
3706 + PIN_FIELD16(38, 38, 0xb20, 0x10, 13, 1),
3707 + PINS_FIELD16(39, 42, 0xb40, 0x10, 13, 1),
3708 + PINS_FIELD16(43, 45, 0xb20, 0x10, 10, 1),
3709 + PINS_FIELD16(47, 48, 0xb20, 0x10, 11, 1),
3710 + PIN_FIELD16(49, 49, 0xb20, 0x10, 12, 1),
3711 + PINS_FIELD16(50, 52, 0xb20, 0x10, 13, 1),
3712 + PINS_FIELD16(53, 56, 0xb20, 0x10, 14, 1),
3713 + PINS_FIELD16(57, 58, 0xb20, 0x10, 15, 1),
3714 + PIN_FIELD16(59, 59, 0xb30, 0x10, 10, 1),
3715 + PINS_FIELD16(60, 62, 0xb30, 0x10, 0, 1),
3716 + PINS_FIELD16(63, 65, 0xb30, 0x10, 1, 1),
3717 + PINS_FIELD16(66, 71, 0xb30, 0x10, 2, 1),
3718 + PINS_FIELD16(72, 74, 0xb20, 0x10, 12, 1),
3719 + PINS_FIELD16(75, 76, 0xb30, 0x10, 3, 1),
3720 + PINS_FIELD16(77, 78, 0xb30, 0x10, 4, 1),
3721 + PINS_FIELD16(79, 82, 0xb30, 0x10, 5, 1),
3722 + PINS_FIELD16(83, 84, 0xb30, 0x10, 2, 1),
3723 + PIN_FIELD16(85, 85, 0xda0, 0x10, 4, 1),
3724 + PIN_FIELD16(86, 86, 0xd90, 0x10, 4, 1),
3725 + PINS_FIELD16(87, 90, 0xdb0, 0x10, 4, 1),
3726 + PINS_FIELD16(101, 104, 0xb30, 0x10, 6, 1),
3727 + PIN_FIELD16(105, 105, 0xd40, 0x10, 4, 1),
3728 + PIN_FIELD16(106, 106, 0xd30, 0x10, 4, 1),
3729 + PINS_FIELD16(107, 110, 0xd50, 0x10, 4, 1),
3730 + PINS_FIELD16(111, 115, 0xce0, 0x10, 4, 1),
3731 + PIN_FIELD16(116, 116, 0xcd0, 0x10, 4, 1),
3732 + PIN_FIELD16(117, 117, 0xcc0, 0x10, 4, 1),
3733 + PINS_FIELD16(118, 121, 0xce0, 0x10, 4, 1),
3734 + PINS_FIELD16(122, 125, 0xb30, 0x10, 7, 1),
3735 + PIN_FIELD16(126, 126, 0xb20, 0x10, 12, 1),
3736 + PINS_FIELD16(127, 142, 0xb30, 0x10, 9, 1),
3737 + PINS_FIELD16(143, 160, 0xb30, 0x10, 10, 1),
3738 + PINS_FIELD16(161, 168, 0xb30, 0x10, 12, 1),
3739 + PINS_FIELD16(169, 183, 0xb30, 0x10, 10, 1),
3740 + PINS_FIELD16(184, 186, 0xb30, 0x10, 9, 1),
3741 + PIN_FIELD16(187, 187, 0xb30, 0x10, 14, 1),
3742 + PIN_FIELD16(188, 188, 0xb20, 0x10, 13, 1),
3743 + PINS_FIELD16(189, 193, 0xb30, 0x10, 15, 1),
3744 + PINS_FIELD16(194, 198, 0xb40, 0x10, 0, 1),
3745 + PIN_FIELD16(199, 199, 0xb20, 0x10, 1, 1),
3746 + PINS_FIELD16(200, 202, 0xb40, 0x10, 1, 1),
3747 + PINS_FIELD16(203, 207, 0xb40, 0x10, 2, 1),
3748 + PINS_FIELD16(208, 209, 0xb40, 0x10, 3, 1),
3749 + PIN_FIELD16(210, 210, 0xb40, 0x10, 4, 1),
3750 + PINS_FIELD16(211, 235, 0xb40, 0x10, 5, 1),
3751 + PINS_FIELD16(236, 241, 0xb40, 0x10, 6, 1),
3752 + PINS_FIELD16(242, 243, 0xb40, 0x10, 7, 1),
3753 + PINS_FIELD16(244, 247, 0xb40, 0x10, 8, 1),
3754 + PIN_FIELD16(248, 248, 0xb40, 0x10, 9, 1),
3755 + PINS_FIELD16(249, 257, 0xfc0, 0x10, 4, 1),
3756 + PIN_FIELD16(258, 258, 0xcb0, 0x10, 4, 1),
3757 + PIN_FIELD16(259, 259, 0xc90, 0x10, 4, 1),
3758 + PIN_FIELD16(260, 260, 0x3a0, 0x10, 4, 1),
3759 + PIN_FIELD16(261, 261, 0xd50, 0x10, 4, 1),
3760 + PINS_FIELD16(262, 277, 0xb40, 0x10, 12, 1),
3761 + PIN_FIELD16(278, 278, 0xb40, 0x10, 13, 1),
3762 +};
3763 +
3764 +static const struct mtk_pin_field_calc mt7623_pin_smt_range[] = {
3765 + PINS_FIELD16(0, 6, 0xb50, 0x10, 0, 1),
3766 + PINS_FIELD16(7, 9, 0xb50, 0x10, 1, 1),
3767 + PINS_FIELD16(10, 13, 0xb60, 0x10, 3, 1),
3768 + PINS_FIELD16(14, 15, 0xb60, 0x10, 13, 1),
3769 + PINS_FIELD16(16, 17, 0xb70, 0x10, 7, 1),
3770 + PINS_FIELD16(18, 29, 0xb70, 0x10, 13, 1),
3771 + PINS_FIELD16(30, 32, 0xb70, 0x10, 7, 1),
3772 + PINS_FIELD16(33, 37, 0xb70, 0x10, 13, 1),
3773 + PIN_FIELD16(38, 38, 0xb50, 0x10, 13, 1),
3774 + PINS_FIELD16(39, 42, 0xb70, 0x10, 13, 1),
3775 + PINS_FIELD16(43, 45, 0xb50, 0x10, 10, 1),
3776 + PINS_FIELD16(47, 48, 0xb50, 0x10, 11, 1),
3777 + PIN_FIELD16(49, 49, 0xb50, 0x10, 12, 1),
3778 + PINS_FIELD16(50, 52, 0xb50, 0x10, 13, 1),
3779 + PINS_FIELD16(53, 56, 0xb50, 0x10, 14, 1),
3780 + PINS_FIELD16(57, 58, 0xb50, 0x10, 15, 1),
3781 + PIN_FIELD16(59, 59, 0xb60, 0x10, 10, 1),
3782 + PINS_FIELD16(60, 62, 0xb60, 0x10, 0, 1),
3783 + PINS_FIELD16(63, 65, 0xb60, 0x10, 1, 1),
3784 + PINS_FIELD16(66, 71, 0xb60, 0x10, 2, 1),
3785 + PINS_FIELD16(72, 74, 0xb50, 0x10, 12, 1),
3786 + PINS_FIELD16(75, 76, 0xb60, 0x10, 3, 1),
3787 + PINS_FIELD16(77, 78, 0xb60, 0x10, 4, 1),
3788 + PINS_FIELD16(79, 82, 0xb60, 0x10, 5, 1),
3789 + PINS_FIELD16(83, 84, 0xb60, 0x10, 2, 1),
3790 + PIN_FIELD16(85, 85, 0xda0, 0x10, 11, 1),
3791 + PIN_FIELD16(86, 86, 0xd90, 0x10, 11, 1),
3792 + PIN_FIELD16(87, 87, 0xdc0, 0x10, 3, 1),
3793 + PIN_FIELD16(88, 88, 0xdc0, 0x10, 7, 1),
3794 + PIN_FIELD16(89, 89, 0xdc0, 0x10, 11, 1),
3795 + PIN_FIELD16(90, 90, 0xdc0, 0x10, 15, 1),
3796 + PINS_FIELD16(101, 104, 0xb60, 0x10, 6, 1),
3797 + PIN_FIELD16(105, 105, 0xd40, 0x10, 11, 1),
3798 + PIN_FIELD16(106, 106, 0xd30, 0x10, 11, 1),
3799 + PIN_FIELD16(107, 107, 0xd60, 0x10, 3, 1),
3800 + PIN_FIELD16(108, 108, 0xd60, 0x10, 7, 1),
3801 + PIN_FIELD16(109, 109, 0xd60, 0x10, 11, 1),
3802 + PIN_FIELD16(110, 110, 0xd60, 0x10, 15, 1),
3803 + PIN_FIELD16(111, 111, 0xd00, 0x10, 15, 1),
3804 + PIN_FIELD16(112, 112, 0xd00, 0x10, 11, 1),
3805 + PIN_FIELD16(113, 113, 0xd00, 0x10, 7, 1),
3806 + PIN_FIELD16(114, 114, 0xd00, 0x10, 3, 1),
3807 + PIN_FIELD16(115, 115, 0xd10, 0x10, 3, 1),
3808 + PIN_FIELD16(116, 116, 0xcd0, 0x10, 11, 1),
3809 + PIN_FIELD16(117, 117, 0xcc0, 0x10, 11, 1),
3810 + PIN_FIELD16(118, 118, 0xcf0, 0x10, 15, 1),
3811 + PIN_FIELD16(119, 119, 0xcf0, 0x10, 7, 1),
3812 + PIN_FIELD16(120, 120, 0xcf0, 0x10, 3, 1),
3813 + PIN_FIELD16(121, 121, 0xcf0, 0x10, 7, 1),
3814 + PINS_FIELD16(122, 125, 0xb60, 0x10, 7, 1),
3815 + PIN_FIELD16(126, 126, 0xb50, 0x10, 12, 1),
3816 + PINS_FIELD16(127, 142, 0xb60, 0x10, 9, 1),
3817 + PINS_FIELD16(143, 160, 0xb60, 0x10, 10, 1),
3818 + PINS_FIELD16(161, 168, 0xb60, 0x10, 12, 1),
3819 + PINS_FIELD16(169, 183, 0xb60, 0x10, 10, 1),
3820 + PINS_FIELD16(184, 186, 0xb60, 0x10, 9, 1),
3821 + PIN_FIELD16(187, 187, 0xb60, 0x10, 14, 1),
3822 + PIN_FIELD16(188, 188, 0xb50, 0x10, 13, 1),
3823 + PINS_FIELD16(189, 193, 0xb60, 0x10, 15, 1),
3824 + PINS_FIELD16(194, 198, 0xb70, 0x10, 0, 1),
3825 + PIN_FIELD16(199, 199, 0xb50, 0x10, 1, 1),
3826 + PINS_FIELD16(200, 202, 0xb70, 0x10, 1, 1),
3827 + PINS_FIELD16(203, 207, 0xb70, 0x10, 2, 1),
3828 + PINS_FIELD16(208, 209, 0xb70, 0x10, 3, 1),
3829 + PIN_FIELD16(210, 210, 0xb70, 0x10, 4, 1),
3830 + PINS_FIELD16(211, 235, 0xb70, 0x10, 5, 1),
3831 + PINS_FIELD16(236, 241, 0xb70, 0x10, 6, 1),
3832 + PINS_FIELD16(242, 243, 0xb70, 0x10, 7, 1),
3833 + PINS_FIELD16(244, 247, 0xb70, 0x10, 8, 1),
3834 + PIN_FIELD16(248, 248, 0xb70, 0x10, 9, 10),
3835 + PIN_FIELD16(249, 249, 0x140, 0x10, 3, 1),
3836 + PIN_FIELD16(250, 250, 0x130, 0x10, 15, 1),
3837 + PIN_FIELD16(251, 251, 0x130, 0x10, 11, 1),
3838 + PIN_FIELD16(252, 252, 0x130, 0x10, 7, 1),
3839 + PIN_FIELD16(253, 253, 0x130, 0x10, 3, 1),
3840 + PIN_FIELD16(254, 254, 0xf40, 0x10, 15, 1),
3841 + PIN_FIELD16(255, 255, 0xf40, 0x10, 11, 1),
3842 + PIN_FIELD16(256, 256, 0xf40, 0x10, 7, 1),
3843 + PIN_FIELD16(257, 257, 0xf40, 0x10, 3, 1),
3844 + PIN_FIELD16(258, 258, 0xcb0, 0x10, 11, 1),
3845 + PIN_FIELD16(259, 259, 0xc90, 0x10, 11, 1),
3846 + PIN_FIELD16(260, 260, 0x3a0, 0x10, 11, 1),
3847 + PIN_FIELD16(261, 261, 0x0b0, 0x10, 3, 1),
3848 + PINS_FIELD16(262, 277, 0xb70, 0x10, 12, 1),
3849 + PIN_FIELD16(278, 278, 0xb70, 0x10, 13, 1),
3850 +};
3851 +
3852 +static const struct mtk_pin_field_calc mt7623_pin_pullen_range[] = {
3853 + PIN_FIELD16(0, 278, 0x150, 0x10, 0, 1),
3854 +};
3855 +
3856 +static const struct mtk_pin_field_calc mt7623_pin_pullsel_range[] = {
3857 + PIN_FIELD16(0, 278, 0x280, 0x10, 0, 1),
3858 +};
3859 +
3860 +static const struct mtk_pin_field_calc mt7623_pin_drv_range[] = {
3861 + PINS_FIELD16(0, 6, 0xf50, 0x10, 0, 4),
3862 + PINS_FIELD16(7, 9, 0xf50, 0x10, 4, 4),
3863 + PINS_FIELD16(10, 13, 0xf50, 0x10, 4, 4),
3864 + PINS_FIELD16(14, 15, 0xf50, 0x10, 12, 4),
3865 + PINS_FIELD16(16, 17, 0xf60, 0x10, 0, 4),
3866 + PINS_FIELD16(18, 21, 0xf60, 0x10, 0, 4),
3867 + PINS_FIELD16(22, 26, 0xf60, 0x10, 8, 4),
3868 + PINS_FIELD16(27, 29, 0xf60, 0x10, 12, 4),
3869 + PINS_FIELD16(30, 32, 0xf60, 0x10, 0, 4),
3870 + PINS_FIELD16(33, 37, 0xf70, 0x10, 0, 4),
3871 + PIN_FIELD16(38, 38, 0xf70, 0x10, 4, 4),
3872 + PINS_FIELD16(39, 42, 0xf70, 0x10, 8, 4),
3873 + PINS_FIELD16(43, 45, 0xf70, 0x10, 12, 4),
3874 + PINS_FIELD16(47, 48, 0xf80, 0x10, 0, 4),
3875 + PIN_FIELD16(49, 49, 0xf80, 0x10, 4, 4),
3876 + PINS_FIELD16(50, 52, 0xf70, 0x10, 4, 4),
3877 + PINS_FIELD16(53, 56, 0xf80, 0x10, 12, 4),
3878 + PINS_FIELD16(60, 62, 0xf90, 0x10, 8, 4),
3879 + PINS_FIELD16(63, 65, 0xf90, 0x10, 12, 4),
3880 + PINS_FIELD16(66, 71, 0xfa0, 0x10, 0, 4),
3881 + PINS_FIELD16(72, 74, 0xf80, 0x10, 4, 4),
3882 + PIN_FIELD16(85, 85, 0xda0, 0x10, 0, 4),
3883 + PIN_FIELD16(86, 86, 0xd90, 0x10, 0, 4),
3884 + PINS_FIELD16(87, 90, 0xdb0, 0x10, 0, 4),
3885 + PIN_FIELD16(105, 105, 0xd40, 0x10, 0, 4),
3886 + PIN_FIELD16(106, 106, 0xd30, 0x10, 0, 4),
3887 + PINS_FIELD16(107, 110, 0xd50, 0x10, 0, 4),
3888 + PINS_FIELD16(111, 115, 0xce0, 0x10, 0, 4),
3889 + PIN_FIELD16(116, 116, 0xcd0, 0x10, 0, 4),
3890 + PIN_FIELD16(117, 117, 0xcc0, 0x10, 0, 4),
3891 + PINS_FIELD16(118, 121, 0xce0, 0x10, 0, 4),
3892 + PIN_FIELD16(126, 126, 0xf80, 0x10, 4, 4),
3893 + PIN_FIELD16(188, 188, 0xf70, 0x10, 4, 4),
3894 + PINS_FIELD16(189, 193, 0xfe0, 0x10, 8, 4),
3895 + PINS_FIELD16(194, 198, 0xfe0, 0x10, 12, 4),
3896 + PIN_FIELD16(199, 199, 0xf50, 0x10, 4, 4),
3897 + PINS_FIELD16(200, 202, 0xfd0, 0x10, 0, 4),
3898 + PINS_FIELD16(203, 207, 0xfd0, 0x10, 4, 4),
3899 + PINS_FIELD16(208, 209, 0xfd0, 0x10, 8, 4),
3900 + PIN_FIELD16(210, 210, 0xfd0, 0x10, 12, 4),
3901 + PINS_FIELD16(211, 235, 0xff0, 0x10, 0, 4),
3902 + PINS_FIELD16(236, 241, 0xff0, 0x10, 4, 4),
3903 + PINS_FIELD16(242, 243, 0xff0, 0x10, 8, 4),
3904 + PIN_FIELD16(248, 248, 0xf00, 0x10, 0, 4),
3905 + PINS_FIELD16(249, 256, 0xfc0, 0x10, 0, 4),
3906 + PIN_FIELD16(257, 257, 0xce0, 0x10, 0, 4),
3907 + PIN_FIELD16(258, 258, 0xcb0, 0x10, 0, 4),
3908 + PIN_FIELD16(259, 259, 0xc90, 0x10, 0, 4),
3909 + PIN_FIELD16(260, 260, 0x3a0, 0x10, 0, 4),
3910 + PIN_FIELD16(261, 261, 0xd50, 0x10, 0, 4),
3911 + PINS_FIELD16(262, 277, 0xf00, 0x10, 8, 4),
3912 + PIN_FIELD16(278, 278, 0xf70, 0x10, 8, 4),
3913 +};
3914 +
3915 +static const struct mtk_pin_field_calc mt7623_pin_tdsel_range[] = {
3916 + PINS_FIELD16(262, 276, 0x4c0, 0x10, 0, 4),
3917 +};
3918 +
3919 +static const struct mtk_pin_field_calc mt7623_pin_pupd_range[] = {
3920 + /* MSDC0 */
3921 + PIN_FIELD16(111, 111, 0xd00, 0x10, 12, 1),
3922 + PIN_FIELD16(112, 112, 0xd00, 0x10, 8, 1),
3923 + PIN_FIELD16(113, 113, 0xd00, 0x10, 4, 1),
3924 + PIN_FIELD16(114, 114, 0xd00, 0x10, 0, 1),
3925 + PIN_FIELD16(115, 115, 0xd10, 0x10, 0, 1),
3926 + PIN_FIELD16(116, 116, 0xcd0, 0x10, 8, 1),
3927 + PIN_FIELD16(117, 117, 0xcc0, 0x10, 8, 1),
3928 + PIN_FIELD16(118, 118, 0xcf0, 0x10, 12, 1),
3929 + PIN_FIELD16(119, 119, 0xcf0, 0x10, 8, 1),
3930 + PIN_FIELD16(120, 120, 0xcf0, 0x10, 4, 1),
3931 + PIN_FIELD16(121, 121, 0xcf0, 0x10, 0, 1),
3932 + /* MSDC1 */
3933 + PIN_FIELD16(105, 105, 0xd40, 0x10, 8, 1),
3934 + PIN_FIELD16(106, 106, 0xd30, 0x10, 8, 1),
3935 + PIN_FIELD16(107, 107, 0xd60, 0x10, 0, 1),
3936 + PIN_FIELD16(108, 108, 0xd60, 0x10, 10, 1),
3937 + PIN_FIELD16(109, 109, 0xd60, 0x10, 4, 1),
3938 + PIN_FIELD16(110, 110, 0xc60, 0x10, 12, 1),
3939 + /* MSDC1 */
3940 + PIN_FIELD16(85, 85, 0xda0, 0x10, 8, 1),
3941 + PIN_FIELD16(86, 86, 0xd90, 0x10, 8, 1),
3942 + PIN_FIELD16(87, 87, 0xdc0, 0x10, 0, 1),
3943 + PIN_FIELD16(88, 88, 0xdc0, 0x10, 10, 1),
3944 + PIN_FIELD16(89, 89, 0xdc0, 0x10, 4, 1),
3945 + PIN_FIELD16(90, 90, 0xdc0, 0x10, 12, 1),
3946 + /* MSDC0E */
3947 + PIN_FIELD16(249, 249, 0x140, 0x10, 0, 1),
3948 + PIN_FIELD16(250, 250, 0x130, 0x10, 12, 1),
3949 + PIN_FIELD16(251, 251, 0x130, 0x10, 8, 1),
3950 + PIN_FIELD16(252, 252, 0x130, 0x10, 4, 1),
3951 + PIN_FIELD16(253, 253, 0x130, 0x10, 0, 1),
3952 + PIN_FIELD16(254, 254, 0xf40, 0x10, 12, 1),
3953 + PIN_FIELD16(255, 255, 0xf40, 0x10, 8, 1),
3954 + PIN_FIELD16(256, 256, 0xf40, 0x10, 4, 1),
3955 + PIN_FIELD16(257, 257, 0xf40, 0x10, 0, 1),
3956 + PIN_FIELD16(258, 258, 0xcb0, 0x10, 8, 1),
3957 + PIN_FIELD16(259, 259, 0xc90, 0x10, 8, 1),
3958 + PIN_FIELD16(261, 261, 0x140, 0x10, 8, 1),
3959 +};
3960 +
3961 +static const struct mtk_pin_field_calc mt7623_pin_r1_range[] = {
3962 + /* MSDC0 */
3963 + PIN_FIELD16(111, 111, 0xd00, 0x10, 13, 1),
3964 + PIN_FIELD16(112, 112, 0xd00, 0x10, 9, 1),
3965 + PIN_FIELD16(113, 113, 0xd00, 0x10, 5, 1),
3966 + PIN_FIELD16(114, 114, 0xd00, 0x10, 1, 1),
3967 + PIN_FIELD16(115, 115, 0xd10, 0x10, 1, 1),
3968 + PIN_FIELD16(116, 116, 0xcd0, 0x10, 9, 1),
3969 + PIN_FIELD16(117, 117, 0xcc0, 0x10, 9, 1),
3970 + PIN_FIELD16(118, 118, 0xcf0, 0x10, 13, 1),
3971 + PIN_FIELD16(119, 119, 0xcf0, 0x10, 9, 1),
3972 + PIN_FIELD16(120, 120, 0xcf0, 0x10, 5, 1),
3973 + PIN_FIELD16(121, 121, 0xcf0, 0x10, 1, 1),
3974 + /* MSDC1 */
3975 + PIN_FIELD16(105, 105, 0xd40, 0x10, 9, 1),
3976 + PIN_FIELD16(106, 106, 0xd30, 0x10, 9, 1),
3977 + PIN_FIELD16(107, 107, 0xd60, 0x10, 1, 1),
3978 + PIN_FIELD16(108, 108, 0xd60, 0x10, 9, 1),
3979 + PIN_FIELD16(109, 109, 0xd60, 0x10, 5, 1),
3980 + PIN_FIELD16(110, 110, 0xc60, 0x10, 13, 1),
3981 + /* MSDC2 */
3982 + PIN_FIELD16(85, 85, 0xda0, 0x10, 9, 1),
3983 + PIN_FIELD16(86, 86, 0xd90, 0x10, 9, 1),
3984 + PIN_FIELD16(87, 87, 0xdc0, 0x10, 1, 1),
3985 + PIN_FIELD16(88, 88, 0xdc0, 0x10, 9, 1),
3986 + PIN_FIELD16(89, 89, 0xdc0, 0x10, 5, 1),
3987 + PIN_FIELD16(90, 90, 0xdc0, 0x10, 13, 1),
3988 + /* MSDC0E */
3989 + PIN_FIELD16(249, 249, 0x140, 0x10, 1, 1),
3990 + PIN_FIELD16(250, 250, 0x130, 0x10, 13, 1),
3991 + PIN_FIELD16(251, 251, 0x130, 0x10, 9, 1),
3992 + PIN_FIELD16(252, 252, 0x130, 0x10, 5, 1),
3993 + PIN_FIELD16(253, 253, 0x130, 0x10, 1, 1),
3994 + PIN_FIELD16(254, 254, 0xf40, 0x10, 13, 1),
3995 + PIN_FIELD16(255, 255, 0xf40, 0x10, 9, 1),
3996 + PIN_FIELD16(256, 256, 0xf40, 0x10, 5, 1),
3997 + PIN_FIELD16(257, 257, 0xf40, 0x10, 1, 1),
3998 + PIN_FIELD16(258, 258, 0xcb0, 0x10, 9, 1),
3999 + PIN_FIELD16(259, 259, 0xc90, 0x10, 9, 1),
4000 + PIN_FIELD16(261, 261, 0x140, 0x10, 9, 1),
4001 +};
4002 +
4003 +static const struct mtk_pin_field_calc mt7623_pin_r0_range[] = {
4004 + /* MSDC0 */
4005 + PIN_FIELD16(111, 111, 0xd00, 0x10, 14, 1),
4006 + PIN_FIELD16(112, 112, 0xd00, 0x10, 10, 1),
4007 + PIN_FIELD16(113, 113, 0xd00, 0x10, 6, 1),
4008 + PIN_FIELD16(114, 114, 0xd00, 0x10, 2, 1),
4009 + PIN_FIELD16(115, 115, 0xd10, 0x10, 2, 1),
4010 + PIN_FIELD16(116, 116, 0xcd0, 0x10, 10, 1),
4011 + PIN_FIELD16(117, 117, 0xcc0, 0x10, 10, 1),
4012 + PIN_FIELD16(118, 118, 0xcf0, 0x10, 14, 1),
4013 + PIN_FIELD16(119, 119, 0xcf0, 0x10, 10, 1),
4014 + PIN_FIELD16(120, 120, 0xcf0, 0x10, 6, 1),
4015 + PIN_FIELD16(121, 121, 0xcf0, 0x10, 2, 1),
4016 + /* MSDC1 */
4017 + PIN_FIELD16(105, 105, 0xd40, 0x10, 10, 1),
4018 + PIN_FIELD16(106, 106, 0xd30, 0x10, 10, 1),
4019 + PIN_FIELD16(107, 107, 0xd60, 0x10, 2, 1),
4020 + PIN_FIELD16(108, 108, 0xd60, 0x10, 8, 1),
4021 + PIN_FIELD16(109, 109, 0xd60, 0x10, 6, 1),
4022 + PIN_FIELD16(110, 110, 0xc60, 0x10, 14, 1),
4023 + /* MSDC2 */
4024 + PIN_FIELD16(85, 85, 0xda0, 0x10, 10, 1),
4025 + PIN_FIELD16(86, 86, 0xd90, 0x10, 10, 1),
4026 + PIN_FIELD16(87, 87, 0xdc0, 0x10, 2, 1),
4027 + PIN_FIELD16(88, 88, 0xdc0, 0x10, 8, 1),
4028 + PIN_FIELD16(89, 89, 0xdc0, 0x10, 6, 1),
4029 + PIN_FIELD16(90, 90, 0xdc0, 0x10, 14, 1),
4030 + /* MSDC0E */
4031 + PIN_FIELD16(249, 249, 0x140, 0x10, 2, 1),
4032 + PIN_FIELD16(250, 250, 0x130, 0x10, 14, 1),
4033 + PIN_FIELD16(251, 251, 0x130, 0x10, 10, 1),
4034 + PIN_FIELD16(252, 252, 0x130, 0x10, 6, 1),
4035 + PIN_FIELD16(253, 253, 0x130, 0x10, 2, 1),
4036 + PIN_FIELD16(254, 254, 0xf40, 0x10, 14, 1),
4037 + PIN_FIELD16(255, 255, 0xf40, 0x10, 10, 1),
4038 + PIN_FIELD16(256, 256, 0xf40, 0x10, 6, 1),
4039 + PIN_FIELD16(257, 257, 0xf40, 0x10, 5, 1),
4040 + PIN_FIELD16(258, 258, 0xcb0, 0x10, 10, 1),
4041 + PIN_FIELD16(259, 259, 0xc90, 0x10, 10, 1),
4042 + PIN_FIELD16(261, 261, 0x140, 0x10, 10, 1),
4043 +};
4044 +
4045 +static const struct mtk_pin_reg_calc mt7623_reg_cals[] = {
4046 + [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt7623_pin_mode_range),
4047 + [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt7623_pin_dir_range),
4048 + [PINCTRL_PIN_REG_DI] = MTK_RANGE(mt7623_pin_di_range),
4049 + [PINCTRL_PIN_REG_DO] = MTK_RANGE(mt7623_pin_do_range),
4050 + [PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt7623_pin_smt_range),
4051 + [PINCTRL_PIN_REG_PULLSEL] = MTK_RANGE(mt7623_pin_pullsel_range),
4052 + [PINCTRL_PIN_REG_PULLEN] = MTK_RANGE(mt7623_pin_pullen_range),
4053 + [PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt7623_pin_drv_range),
4054 + [PINCTRL_PIN_REG_TDSEL] = MTK_RANGE(mt7623_pin_tdsel_range),
4055 + [PINCTRL_PIN_REG_IES] = MTK_RANGE(mt7623_pin_ies_range),
4056 + [PINCTRL_PIN_REG_PUPD] = MTK_RANGE(mt7623_pin_pupd_range),
4057 + [PINCTRL_PIN_REG_R0] = MTK_RANGE(mt7623_pin_r0_range),
4058 + [PINCTRL_PIN_REG_R1] = MTK_RANGE(mt7623_pin_r1_range),
4059 +};
4060 +
4061 +static const struct mtk_pin_desc mt7623_pins[] = {
4062 + MT7623_PIN(0, "PWRAP_SPI0_MI", 148, DRV_GRP3),
4063 + MT7623_PIN(1, "PWRAP_SPI0_MO", 149, DRV_GRP3),
4064 + MT7623_PIN(2, "PWRAP_INT", 150, DRV_GRP3),
4065 + MT7623_PIN(3, "PWRAP_SPI0_CK", 151, DRV_GRP3),
4066 + MT7623_PIN(4, "PWRAP_SPI0_CSN", 152, DRV_GRP3),
4067 + MT7623_PIN(5, "PWRAP_SPI0_CK2", 153, DRV_GRP3),
4068 + MT7623_PIN(6, "PWRAP_SPI0_CSN2", 154, DRV_GRP3),
4069 + MT7623_PIN(7, "SPI1_CSN", 155, DRV_GRP3),
4070 + MT7623_PIN(8, "SPI1_MI", 156, DRV_GRP3),
4071 + MT7623_PIN(9, "SPI1_MO", 157, DRV_GRP3),
4072 + MT7623_PIN(10, "RTC32K_CK", 158, DRV_GRP3),
4073 + MT7623_PIN(11, "WATCHDOG", 159, DRV_GRP3),
4074 + MT7623_PIN(12, "SRCLKENA", 160, DRV_GRP3),
4075 + MT7623_PIN(13, "SRCLKENAI", 161, DRV_GRP3),
4076 + MT7623_PIN(14, "URXD2", 162, DRV_GRP1),
4077 + MT7623_PIN(15, "UTXD2", 163, DRV_GRP1),
4078 + MT7623_PIN(16, "I2S5_DATA_IN", 164, DRV_GRP1),
4079 + MT7623_PIN(17, "I2S5_BCK", 165, DRV_GRP1),
4080 + MT7623_PIN(18, "PCM_CLK", 166, DRV_GRP1),
4081 + MT7623_PIN(19, "PCM_SYNC", 167, DRV_GRP1),
4082 + MT7623_PIN(20, "PCM_RX", EINT_NA, DRV_GRP1),
4083 + MT7623_PIN(21, "PCM_TX", EINT_NA, DRV_GRP1),
4084 + MT7623_PIN(22, "EINT0", 0, DRV_GRP1),
4085 + MT7623_PIN(23, "EINT1", 1, DRV_GRP1),
4086 + MT7623_PIN(24, "EINT2", 2, DRV_GRP1),
4087 + MT7623_PIN(25, "EINT3", 3, DRV_GRP1),
4088 + MT7623_PIN(26, "EINT4", 4, DRV_GRP1),
4089 + MT7623_PIN(27, "EINT5", 5, DRV_GRP1),
4090 + MT7623_PIN(28, "EINT6", 6, DRV_GRP1),
4091 + MT7623_PIN(29, "EINT7", 7, DRV_GRP1),
4092 + MT7623_PIN(30, "I2S5_LRCK", 12, DRV_GRP1),
4093 + MT7623_PIN(31, "I2S5_MCLK", 13, DRV_GRP1),
4094 + MT7623_PIN(32, "I2S5_DATA", 14, DRV_GRP1),
4095 + MT7623_PIN(33, "I2S1_DATA", 15, DRV_GRP1),
4096 + MT7623_PIN(34, "I2S1_DATA_IN", 16, DRV_GRP1),
4097 + MT7623_PIN(35, "I2S1_BCK", 17, DRV_GRP1),
4098 + MT7623_PIN(36, "I2S1_LRCK", 18, DRV_GRP1),
4099 + MT7623_PIN(37, "I2S1_MCLK", 19, DRV_GRP1),
4100 + MT7623_PIN(38, "I2S2_DATA", 20, DRV_GRP1),
4101 + MT7623_PIN(39, "JTMS", 21, DRV_GRP3),
4102 + MT7623_PIN(40, "JTCK", 22, DRV_GRP3),
4103 + MT7623_PIN(41, "JTDI", 23, DRV_GRP3),
4104 + MT7623_PIN(42, "JTDO", 24, DRV_GRP3),
4105 + MT7623_PIN(43, "NCLE", 25, DRV_GRP1),
4106 + MT7623_PIN(44, "NCEB1", 26, DRV_GRP1),
4107 + MT7623_PIN(45, "NCEB0", 27, DRV_GRP1),
4108 + MT7623_PIN(46, "IR", 28, DRV_FIXED),
4109 + MT7623_PIN(47, "NREB", 29, DRV_GRP1),
4110 + MT7623_PIN(48, "NRNB", 30, DRV_GRP1),
4111 + MT7623_PIN(49, "I2S0_DATA", 31, DRV_GRP1),
4112 + MT7623_PIN(50, "I2S2_BCK", 32, DRV_GRP1),
4113 + MT7623_PIN(51, "I2S2_DATA_IN", 33, DRV_GRP1),
4114 + MT7623_PIN(52, "I2S2_LRCK", 34, DRV_GRP1),
4115 + MT7623_PIN(53, "SPI0_CSN", 35, DRV_GRP1),
4116 + MT7623_PIN(54, "SPI0_CK", 36, DRV_GRP1),
4117 + MT7623_PIN(55, "SPI0_MI", 37, DRV_GRP1),
4118 + MT7623_PIN(56, "SPI0_MO", 38, DRV_GRP1),
4119 + MT7623_PIN(57, "SDA1", 39, DRV_FIXED),
4120 + MT7623_PIN(58, "SCL1", 40, DRV_FIXED),
4121 + MT7623_PIN(59, "RAMBUF_I_CLK", EINT_NA, DRV_FIXED),
4122 + MT7623_PIN(60, "WB_RSTB", 41, DRV_GRP3),
4123 + MT7623_PIN(61, "F2W_DATA", 42, DRV_GRP3),
4124 + MT7623_PIN(62, "F2W_CLK", 43, DRV_GRP3),
4125 + MT7623_PIN(63, "WB_SCLK", 44, DRV_GRP3),
4126 + MT7623_PIN(64, "WB_SDATA", 45, DRV_GRP3),
4127 + MT7623_PIN(65, "WB_SEN", 46, DRV_GRP3),
4128 + MT7623_PIN(66, "WB_CRTL0", 47, DRV_GRP3),
4129 + MT7623_PIN(67, "WB_CRTL1", 48, DRV_GRP3),
4130 + MT7623_PIN(68, "WB_CRTL2", 49, DRV_GRP3),
4131 + MT7623_PIN(69, "WB_CRTL3", 50, DRV_GRP3),
4132 + MT7623_PIN(70, "WB_CRTL4", 51, DRV_GRP3),
4133 + MT7623_PIN(71, "WB_CRTL5", 52, DRV_GRP3),
4134 + MT7623_PIN(72, "I2S0_DATA_IN", 53, DRV_GRP1),
4135 + MT7623_PIN(73, "I2S0_LRCK", 54, DRV_GRP1),
4136 + MT7623_PIN(74, "I2S0_BCK", 55, DRV_GRP1),
4137 + MT7623_PIN(75, "SDA0", 56, DRV_FIXED),
4138 + MT7623_PIN(76, "SCL0", 57, DRV_FIXED),
4139 + MT7623_PIN(77, "SDA2", 58, DRV_FIXED),
4140 + MT7623_PIN(78, "SCL2", 59, DRV_FIXED),
4141 + MT7623_PIN(79, "URXD0", 60, DRV_FIXED),
4142 + MT7623_PIN(80, "UTXD0", 61, DRV_FIXED),
4143 + MT7623_PIN(81, "URXD1", 62, DRV_FIXED),
4144 + MT7623_PIN(82, "UTXD1", 63, DRV_FIXED),
4145 + MT7623_PIN(83, "LCM_RST", 64, DRV_FIXED),
4146 + MT7623_PIN(84, "DSI_TE", 65, DRV_FIXED),
4147 + MT7623_PIN(85, "MSDC2_CMD", 66, DRV_GRP4),
4148 + MT7623_PIN(86, "MSDC2_CLK", 67, DRV_GRP4),
4149 + MT7623_PIN(87, "MSDC2_DAT0", 68, DRV_GRP4),
4150 + MT7623_PIN(88, "MSDC2_DAT1", 69, DRV_GRP4),
4151 + MT7623_PIN(89, "MSDC2_DAT2", 70, DRV_GRP4),
4152 + MT7623_PIN(90, "MSDC2_DAT3", 71, DRV_GRP4),
4153 + MT7623_PIN(91, "TDN3", EINT_NA, DRV_FIXED),
4154 + MT7623_PIN(92, "TDP3", EINT_NA, DRV_FIXED),
4155 + MT7623_PIN(93, "TDN2", EINT_NA, DRV_FIXED),
4156 + MT7623_PIN(94, "TDP2", EINT_NA, DRV_FIXED),
4157 + MT7623_PIN(95, "TCN", EINT_NA, DRV_FIXED),
4158 + MT7623_PIN(96, "TCP", EINT_NA, DRV_FIXED),
4159 + MT7623_PIN(97, "TDN1", EINT_NA, DRV_FIXED),
4160 + MT7623_PIN(98, "TDP1", EINT_NA, DRV_FIXED),
4161 + MT7623_PIN(99, "TDN0", EINT_NA, DRV_FIXED),
4162 + MT7623_PIN(100, "TDP0", EINT_NA, DRV_FIXED),
4163 + MT7623_PIN(101, "SPI2_CSN", 74, DRV_FIXED),
4164 + MT7623_PIN(102, "SPI2_MI", 75, DRV_FIXED),
4165 + MT7623_PIN(103, "SPI2_MO", 76, DRV_FIXED),
4166 + MT7623_PIN(104, "SPI2_CLK", 77, DRV_FIXED),
4167 + MT7623_PIN(105, "MSDC1_CMD", 78, DRV_GRP4),
4168 + MT7623_PIN(106, "MSDC1_CLK", 79, DRV_GRP4),
4169 + MT7623_PIN(107, "MSDC1_DAT0", 80, DRV_GRP4),
4170 + MT7623_PIN(108, "MSDC1_DAT1", 81, DRV_GRP4),
4171 + MT7623_PIN(109, "MSDC1_DAT2", 82, DRV_GRP4),
4172 + MT7623_PIN(110, "MSDC1_DAT3", 83, DRV_GRP4),
4173 + MT7623_PIN(111, "MSDC0_DAT7", 84, DRV_GRP4),
4174 + MT7623_PIN(112, "MSDC0_DAT6", 85, DRV_GRP4),
4175 + MT7623_PIN(113, "MSDC0_DAT5", 86, DRV_GRP4),
4176 + MT7623_PIN(114, "MSDC0_DAT4", 87, DRV_GRP4),
4177 + MT7623_PIN(115, "MSDC0_RSTB", 88, DRV_GRP4),
4178 + MT7623_PIN(116, "MSDC0_CMD", 89, DRV_GRP4),
4179 + MT7623_PIN(117, "MSDC0_CLK", 90, DRV_GRP4),
4180 + MT7623_PIN(118, "MSDC0_DAT3", 91, DRV_GRP4),
4181 + MT7623_PIN(119, "MSDC0_DAT2", 92, DRV_GRP4),
4182 + MT7623_PIN(120, "MSDC0_DAT1", 93, DRV_GRP4),
4183 + MT7623_PIN(121, "MSDC0_DAT0", 94, DRV_GRP4),
4184 + MT7623_PIN(122, "CEC", 95, DRV_FIXED),
4185 + MT7623_PIN(123, "HTPLG", 96, DRV_FIXED),
4186 + MT7623_PIN(124, "HDMISCK", 97, DRV_FIXED),
4187 + MT7623_PIN(125, "HDMISD", 98, DRV_FIXED),
4188 + MT7623_PIN(126, "I2S0_MCLK", 99, DRV_GRP1),
4189 + MT7623_PIN(127, "RAMBUF_IDATA0", EINT_NA, DRV_FIXED),
4190 + MT7623_PIN(128, "RAMBUF_IDATA1", EINT_NA, DRV_FIXED),
4191 + MT7623_PIN(129, "RAMBUF_IDATA2", EINT_NA, DRV_FIXED),
4192 + MT7623_PIN(130, "RAMBUF_IDATA3", EINT_NA, DRV_FIXED),
4193 + MT7623_PIN(131, "RAMBUF_IDATA4", EINT_NA, DRV_FIXED),
4194 + MT7623_PIN(132, "RAMBUF_IDATA5", EINT_NA, DRV_FIXED),
4195 + MT7623_PIN(133, "RAMBUF_IDATA6", EINT_NA, DRV_FIXED),
4196 + MT7623_PIN(134, "RAMBUF_IDATA7", EINT_NA, DRV_FIXED),
4197 + MT7623_PIN(135, "RAMBUF_IDATA8", EINT_NA, DRV_FIXED),
4198 + MT7623_PIN(136, "RAMBUF_IDATA9", EINT_NA, DRV_FIXED),
4199 + MT7623_PIN(137, "RAMBUF_IDATA10", EINT_NA, DRV_FIXED),
4200 + MT7623_PIN(138, "RAMBUF_IDATA11", EINT_NA, DRV_FIXED),
4201 + MT7623_PIN(139, "RAMBUF_IDATA12", EINT_NA, DRV_FIXED),
4202 + MT7623_PIN(140, "RAMBUF_IDATA13", EINT_NA, DRV_FIXED),
4203 + MT7623_PIN(141, "RAMBUF_IDATA14", EINT_NA, DRV_FIXED),
4204 + MT7623_PIN(142, "RAMBUF_IDATA15", EINT_NA, DRV_FIXED),
4205 + MT7623_PIN(143, "RAMBUF_ODATA0", EINT_NA, DRV_FIXED),
4206 + MT7623_PIN(144, "RAMBUF_ODATA1", EINT_NA, DRV_FIXED),
4207 + MT7623_PIN(145, "RAMBUF_ODATA2", EINT_NA, DRV_FIXED),
4208 + MT7623_PIN(146, "RAMBUF_ODATA3", EINT_NA, DRV_FIXED),
4209 + MT7623_PIN(147, "RAMBUF_ODATA4", EINT_NA, DRV_FIXED),
4210 + MT7623_PIN(148, "RAMBUF_ODATA5", EINT_NA, DRV_FIXED),
4211 + MT7623_PIN(149, "RAMBUF_ODATA6", EINT_NA, DRV_FIXED),
4212 + MT7623_PIN(150, "RAMBUF_ODATA7", EINT_NA, DRV_FIXED),
4213 + MT7623_PIN(151, "RAMBUF_ODATA8", EINT_NA, DRV_FIXED),
4214 + MT7623_PIN(152, "RAMBUF_ODATA9", EINT_NA, DRV_FIXED),
4215 + MT7623_PIN(153, "RAMBUF_ODATA10", EINT_NA, DRV_FIXED),
4216 + MT7623_PIN(154, "RAMBUF_ODATA11", EINT_NA, DRV_FIXED),
4217 + MT7623_PIN(155, "RAMBUF_ODATA12", EINT_NA, DRV_FIXED),
4218 + MT7623_PIN(156, "RAMBUF_ODATA13", EINT_NA, DRV_FIXED),
4219 + MT7623_PIN(157, "RAMBUF_ODATA14", EINT_NA, DRV_FIXED),
4220 + MT7623_PIN(158, "RAMBUF_ODATA15", EINT_NA, DRV_FIXED),
4221 + MT7623_PIN(159, "RAMBUF_BE0", EINT_NA, DRV_FIXED),
4222 + MT7623_PIN(160, "RAMBUF_BE1", EINT_NA, DRV_FIXED),
4223 + MT7623_PIN(161, "AP2PT_INT", EINT_NA, DRV_FIXED),
4224 + MT7623_PIN(162, "AP2PT_INT_CLR", EINT_NA, DRV_FIXED),
4225 + MT7623_PIN(163, "PT2AP_INT", EINT_NA, DRV_FIXED),
4226 + MT7623_PIN(164, "PT2AP_INT_CLR", EINT_NA, DRV_FIXED),
4227 + MT7623_PIN(165, "AP2UP_INT", EINT_NA, DRV_FIXED),
4228 + MT7623_PIN(166, "AP2UP_INT_CLR", EINT_NA, DRV_FIXED),
4229 + MT7623_PIN(167, "UP2AP_INT", EINT_NA, DRV_FIXED),
4230 + MT7623_PIN(168, "UP2AP_INT_CLR", EINT_NA, DRV_FIXED),
4231 + MT7623_PIN(169, "RAMBUF_ADDR0", EINT_NA, DRV_FIXED),
4232 + MT7623_PIN(170, "RAMBUF_ADDR1", EINT_NA, DRV_FIXED),
4233 + MT7623_PIN(171, "RAMBUF_ADDR2", EINT_NA, DRV_FIXED),
4234 + MT7623_PIN(172, "RAMBUF_ADDR3", EINT_NA, DRV_FIXED),
4235 + MT7623_PIN(173, "RAMBUF_ADDR4", EINT_NA, DRV_FIXED),
4236 + MT7623_PIN(174, "RAMBUF_ADDR5", EINT_NA, DRV_FIXED),
4237 + MT7623_PIN(175, "RAMBUF_ADDR6", EINT_NA, DRV_FIXED),
4238 + MT7623_PIN(176, "RAMBUF_ADDR7", EINT_NA, DRV_FIXED),
4239 + MT7623_PIN(177, "RAMBUF_ADDR8", EINT_NA, DRV_FIXED),
4240 + MT7623_PIN(178, "RAMBUF_ADDR9", EINT_NA, DRV_FIXED),
4241 + MT7623_PIN(179, "RAMBUF_ADDR10", EINT_NA, DRV_FIXED),
4242 + MT7623_PIN(180, "RAMBUF_RW", EINT_NA, DRV_FIXED),
4243 + MT7623_PIN(181, "RAMBUF_LAST", EINT_NA, DRV_FIXED),
4244 + MT7623_PIN(182, "RAMBUF_HP", EINT_NA, DRV_FIXED),
4245 + MT7623_PIN(183, "RAMBUF_REQ", EINT_NA, DRV_FIXED),
4246 + MT7623_PIN(184, "RAMBUF_ALE", EINT_NA, DRV_FIXED),
4247 + MT7623_PIN(185, "RAMBUF_DLE", EINT_NA, DRV_FIXED),
4248 + MT7623_PIN(186, "RAMBUF_WDLE", EINT_NA, DRV_FIXED),
4249 + MT7623_PIN(187, "RAMBUF_O_CLK", EINT_NA, DRV_FIXED),
4250 + MT7623_PIN(188, "I2S2_MCLK", 100, DRV_GRP1),
4251 + MT7623_PIN(189, "I2S3_DATA", 101, DRV_GRP1),
4252 + MT7623_PIN(190, "I2S3_DATA_IN", 102, DRV_GRP1),
4253 + MT7623_PIN(191, "I2S3_BCK", 103, DRV_GRP1),
4254 + MT7623_PIN(192, "I2S3_LRCK", 104, DRV_GRP1),
4255 + MT7623_PIN(193, "I2S3_MCLK", 105, DRV_GRP1),
4256 + MT7623_PIN(194, "I2S4_DATA", 106, DRV_GRP1),
4257 + MT7623_PIN(195, "I2S4_DATA_IN", 107, DRV_GRP1),
4258 + MT7623_PIN(196, "I2S4_BCK", 108, DRV_GRP1),
4259 + MT7623_PIN(197, "I2S4_LRCK", 109, DRV_GRP1),
4260 + MT7623_PIN(198, "I2S4_MCLK", 110, DRV_GRP1),
4261 + MT7623_PIN(199, "SPI1_CLK", 111, DRV_GRP3),
4262 + MT7623_PIN(200, "SPDIF_OUT", 112, DRV_GRP1),
4263 + MT7623_PIN(201, "SPDIF_IN0", 113, DRV_GRP1),
4264 + MT7623_PIN(202, "SPDIF_IN1", 114, DRV_GRP1),
4265 + MT7623_PIN(203, "PWM0", 115, DRV_GRP1),
4266 + MT7623_PIN(204, "PWM1", 116, DRV_GRP1),
4267 + MT7623_PIN(205, "PWM2", 117, DRV_GRP1),
4268 + MT7623_PIN(206, "PWM3", 118, DRV_GRP1),
4269 + MT7623_PIN(207, "PWM4", 119, DRV_GRP1),
4270 + MT7623_PIN(208, "AUD_EXT_CK1", 120, DRV_GRP1),
4271 + MT7623_PIN(209, "AUD_EXT_CK2", 121, DRV_GRP1),
4272 + MT7623_PIN(210, "AUD_CLOCK", EINT_NA, DRV_GRP3),
4273 + MT7623_PIN(211, "DVP_RESET", EINT_NA, DRV_GRP3),
4274 + MT7623_PIN(212, "DVP_CLOCK", EINT_NA, DRV_GRP3),
4275 + MT7623_PIN(213, "DVP_CS", EINT_NA, DRV_GRP3),
4276 + MT7623_PIN(214, "DVP_CK", EINT_NA, DRV_GRP3),
4277 + MT7623_PIN(215, "DVP_DI", EINT_NA, DRV_GRP3),
4278 + MT7623_PIN(216, "DVP_DO", EINT_NA, DRV_GRP3),
4279 + MT7623_PIN(217, "AP_CS", EINT_NA, DRV_GRP3),
4280 + MT7623_PIN(218, "AP_CK", EINT_NA, DRV_GRP3),
4281 + MT7623_PIN(219, "AP_DI", EINT_NA, DRV_GRP3),
4282 + MT7623_PIN(220, "AP_DO", EINT_NA, DRV_GRP3),
4283 + MT7623_PIN(221, "DVD_BCLK", EINT_NA, DRV_GRP3),
4284 + MT7623_PIN(222, "T8032_CLK", EINT_NA, DRV_GRP3),
4285 + MT7623_PIN(223, "AP_BCLK", EINT_NA, DRV_GRP3),
4286 + MT7623_PIN(224, "HOST_CS", EINT_NA, DRV_GRP3),
4287 + MT7623_PIN(225, "HOST_CK", EINT_NA, DRV_GRP3),
4288 + MT7623_PIN(226, "HOST_DO0", EINT_NA, DRV_GRP3),
4289 + MT7623_PIN(227, "HOST_DO1", EINT_NA, DRV_GRP3),
4290 + MT7623_PIN(228, "SLV_CS", EINT_NA, DRV_GRP3),
4291 + MT7623_PIN(229, "SLV_CK", EINT_NA, DRV_GRP3),
4292 + MT7623_PIN(230, "SLV_DI0", EINT_NA, DRV_GRP3),
4293 + MT7623_PIN(231, "SLV_DI1", EINT_NA, DRV_GRP3),
4294 + MT7623_PIN(232, "AP2DSP_INT", EINT_NA, DRV_GRP3),
4295 + MT7623_PIN(233, "AP2DSP_INT_CLR", EINT_NA, DRV_GRP3),
4296 + MT7623_PIN(234, "DSP2AP_INT", EINT_NA, DRV_GRP3),
4297 + MT7623_PIN(235, "DSP2AP_INT_CLR", EINT_NA, DRV_GRP3),
4298 + MT7623_PIN(236, "EXT_SDIO3", 122, DRV_GRP1),
4299 + MT7623_PIN(237, "EXT_SDIO2", 123, DRV_GRP1),
4300 + MT7623_PIN(238, "EXT_SDIO1", 124, DRV_GRP1),
4301 + MT7623_PIN(239, "EXT_SDIO0", 125, DRV_GRP1),
4302 + MT7623_PIN(240, "EXT_XCS", 126, DRV_GRP1),
4303 + MT7623_PIN(241, "EXT_SCK", 127, DRV_GRP1),
4304 + MT7623_PIN(242, "URTS2", 128, DRV_GRP1),
4305 + MT7623_PIN(243, "UCTS2", 129, DRV_GRP1),
4306 + MT7623_PIN(244, "HDMI_SDA_RX", 130, DRV_FIXED),
4307 + MT7623_PIN(245, "HDMI_SCL_RX", 131, DRV_FIXED),
4308 + MT7623_PIN(246, "MHL_SENCE", 132, DRV_FIXED),
4309 + MT7623_PIN(247, "HDMI_HPD_CBUS_RX", 69, DRV_FIXED),
4310 + MT7623_PIN(248, "HDMI_TESTOUTP_RX", 133, DRV_GRP1),
4311 + MT7623_PIN(249, "MSDC0E_RSTB", 134, DRV_GRP4),
4312 + MT7623_PIN(250, "MSDC0E_DAT7", 135, DRV_GRP4),
4313 + MT7623_PIN(251, "MSDC0E_DAT6", 136, DRV_GRP4),
4314 + MT7623_PIN(252, "MSDC0E_DAT5", 137, DRV_GRP4),
4315 + MT7623_PIN(253, "MSDC0E_DAT4", 138, DRV_GRP4),
4316 + MT7623_PIN(254, "MSDC0E_DAT3", 139, DRV_GRP4),
4317 + MT7623_PIN(255, "MSDC0E_DAT2", 140, DRV_GRP4),
4318 + MT7623_PIN(256, "MSDC0E_DAT1", 141, DRV_GRP4),
4319 + MT7623_PIN(257, "MSDC0E_DAT0", 142, DRV_GRP4),
4320 + MT7623_PIN(258, "MSDC0E_CMD", 143, DRV_GRP4),
4321 + MT7623_PIN(259, "MSDC0E_CLK", 144, DRV_GRP4),
4322 + MT7623_PIN(260, "MSDC0E_DSL", 145, DRV_GRP4),
4323 + MT7623_PIN(261, "MSDC1_INS", 146, DRV_GRP4),
4324 + MT7623_PIN(262, "G2_TXEN", 8, DRV_GRP1),
4325 + MT7623_PIN(263, "G2_TXD3", 9, DRV_GRP1),
4326 + MT7623_PIN(264, "G2_TXD2", 10, DRV_GRP1),
4327 + MT7623_PIN(265, "G2_TXD1", 11, DRV_GRP1),
4328 + MT7623_PIN(266, "G2_TXD0", EINT_NA, DRV_GRP1),
4329 + MT7623_PIN(267, "G2_TXC", EINT_NA, DRV_GRP1),
4330 + MT7623_PIN(268, "G2_RXC", EINT_NA, DRV_GRP1),
4331 + MT7623_PIN(269, "G2_RXD0", EINT_NA, DRV_GRP1),
4332 + MT7623_PIN(270, "G2_RXD1", EINT_NA, DRV_GRP1),
4333 + MT7623_PIN(271, "G2_RXD2", EINT_NA, DRV_GRP1),
4334 + MT7623_PIN(272, "G2_RXD3", EINT_NA, DRV_GRP1),
4335 + MT7623_PIN(273, "ESW_INT", 168, DRV_GRP1),
4336 + MT7623_PIN(274, "G2_RXDV", EINT_NA, DRV_GRP1),
4337 + MT7623_PIN(275, "MDC", EINT_NA, DRV_GRP1),
4338 + MT7623_PIN(276, "MDIO", EINT_NA, DRV_GRP1),
4339 + MT7623_PIN(277, "ESW_RST", EINT_NA, DRV_GRP1),
4340 + MT7623_PIN(278, "JTAG_RESET", 147, DRV_GRP3),
4341 + MT7623_PIN(279, "USB3_RES_BOND", EINT_NA, DRV_GRP1),
4342 +};
4343 +
4344 +/* List all groups consisting of these pins dedicated to the enablement of
4345 + * certain hardware block and the corresponding mode for all of the pins.
4346 + * The hardware probably has multiple combinations of these pinouts.
4347 + */
4348 +
4349 +/* AUDIO EXT CLK */
4350 +static int mt7623_aud_ext_clk0_pins[] = { 208, };
4351 +static int mt7623_aud_ext_clk0_funcs[] = { 1, };
4352 +static int mt7623_aud_ext_clk1_pins[] = { 209, };
4353 +static int mt7623_aud_ext_clk1_funcs[] = { 1, };
4354 +
4355 +/* DISP PWM */
4356 +static int mt7623_disp_pwm_0_pins[] = { 72, };
4357 +static int mt7623_disp_pwm_0_funcs[] = { 5, };
4358 +static int mt7623_disp_pwm_1_pins[] = { 203, };
4359 +static int mt7623_disp_pwm_1_funcs[] = { 2, };
4360 +static int mt7623_disp_pwm_2_pins[] = { 208, };
4361 +static int mt7623_disp_pwm_2_funcs[] = { 5, };
4362 +
4363 +/* ESW */
4364 +static int mt7623_esw_int_pins[] = { 273, };
4365 +static int mt7623_esw_int_funcs[] = { 1, };
4366 +static int mt7623_esw_rst_pins[] = { 277, };
4367 +static int mt7623_esw_rst_funcs[] = { 1, };
4368 +
4369 +/* EPHY */
4370 +static int mt7623_ephy_pins[] = { 262, 263, 264, 265, 266, 267, 268,
4371 + 269, 270, 271, 272, 274, };
4372 +static int mt7623_ephy_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
4373 +
4374 +/* EXT_SDIO */
4375 +static int mt7623_ext_sdio_pins[] = { 236, 237, 238, 239, 240, 241, };
4376 +static int mt7623_ext_sdio_funcs[] = { 1, 1, 1, 1, 1, 1, };
4377 +
4378 +/* HDMI RX */
4379 +static int mt7623_hdmi_rx_pins[] = { 247, 248, };
4380 +static int mt7623_hdmi_rx_funcs[] = { 1, 1 };
4381 +static int mt7623_hdmi_rx_i2c_pins[] = { 244, 245, };
4382 +static int mt7623_hdmi_rx_i2c_funcs[] = { 1, 1 };
4383 +
4384 +/* HDMI TX */
4385 +static int mt7623_hdmi_cec_pins[] = { 122, };
4386 +static int mt7623_hdmi_cec_funcs[] = { 1, };
4387 +static int mt7623_hdmi_htplg_pins[] = { 123, };
4388 +static int mt7623_hdmi_htplg_funcs[] = { 1, };
4389 +static int mt7623_hdmi_i2c_pins[] = { 124, 125, };
4390 +static int mt7623_hdmi_i2c_funcs[] = { 1, 1 };
4391 +
4392 +/* I2C */
4393 +static int mt7623_i2c0_pins[] = { 75, 76, };
4394 +static int mt7623_i2c0_funcs[] = { 1, 1, };
4395 +static int mt7623_i2c1_0_pins[] = { 57, 58, };
4396 +static int mt7623_i2c1_0_funcs[] = { 1, 1, };
4397 +static int mt7623_i2c1_1_pins[] = { 242, 243, };
4398 +static int mt7623_i2c1_1_funcs[] = { 4, 4, };
4399 +static int mt7623_i2c1_2_pins[] = { 85, 86, };
4400 +static int mt7623_i2c1_2_funcs[] = { 3, 3, };
4401 +static int mt7623_i2c1_3_pins[] = { 105, 106, };
4402 +static int mt7623_i2c1_3_funcs[] = { 3, 3, };
4403 +static int mt7623_i2c1_4_pins[] = { 124, 125, };
4404 +static int mt7623_i2c1_4_funcs[] = { 4, 4, };
4405 +static int mt7623_i2c2_0_pins[] = { 77, 78, };
4406 +static int mt7623_i2c2_0_funcs[] = { 1, 1, };
4407 +static int mt7623_i2c2_1_pins[] = { 89, 90, };
4408 +static int mt7623_i2c2_1_funcs[] = { 3, 3, };
4409 +static int mt7623_i2c2_2_pins[] = { 109, 110, };
4410 +static int mt7623_i2c2_2_funcs[] = { 3, 3, };
4411 +static int mt7623_i2c2_3_pins[] = { 122, 123, };
4412 +static int mt7623_i2c2_3_funcs[] = { 4, 4, };
4413 +
4414 +/* I2S */
4415 +static int mt7623_i2s0_pins[] = { 49, 72, 73, 74, 126, };
4416 +static int mt7623_i2s0_funcs[] = { 1, 1, 1, 1, 1, };
4417 +static int mt7623_i2s1_pins[] = { 33, 34, 35, 36, 37, };
4418 +static int mt7623_i2s1_funcs[] = { 1, 1, 1, 1, 1, };
4419 +static int mt7623_i2s2_bclk_lrclk_mclk_pins[] = { 50, 52, 188, };
4420 +static int mt7623_i2s2_bclk_lrclk_mclk_funcs[] = { 1, 1, 1, };
4421 +static int mt7623_i2s2_data_in_pins[] = { 51, };
4422 +static int mt7623_i2s2_data_in_funcs[] = { 1, };
4423 +static int mt7623_i2s2_data_0_pins[] = { 203, };
4424 +static int mt7623_i2s2_data_0_funcs[] = { 9, };
4425 +static int mt7623_i2s2_data_1_pins[] = { 38, };
4426 +static int mt7623_i2s2_data_1_funcs[] = { 4, };
4427 +static int mt7623_i2s3_bclk_lrclk_mclk_pins[] = { 191, 192, 193, };
4428 +static int mt7623_i2s3_bclk_lrclk_mclk_funcs[] = { 1, 1, 1, };
4429 +static int mt7623_i2s3_data_in_pins[] = { 190, };
4430 +static int mt7623_i2s3_data_in_funcs[] = { 1, };
4431 +static int mt7623_i2s3_data_0_pins[] = { 204, };
4432 +static int mt7623_i2s3_data_0_funcs[] = { 9, };
4433 +static int mt7623_i2s3_data_1_pins[] = { 2, };
4434 +static int mt7623_i2s3_data_1_funcs[] = { 0, };
4435 +static int mt7623_i2s4_pins[] = { 194, 195, 196, 197, 198, };
4436 +static int mt7623_i2s4_funcs[] = { 1, 1, 1, 1, 1, };
4437 +static int mt7623_i2s5_pins[] = { 16, 17, 30, 31, 32, };
4438 +static int mt7623_i2s5_funcs[] = { 1, 1, 1, 1, 1, };
4439 +
4440 +/* IR */
4441 +static int mt7623_ir_pins[] = { 46, };
4442 +static int mt7623_ir_funcs[] = { 1, };
4443 +
4444 +/* LCD */
4445 +static int mt7623_mipi_tx_pins[] = { 91, 92, 93, 94, 95, 96, 97, 98,
4446 + 99, 100, };
4447 +static int mt7623_mipi_tx_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
4448 +static int mt7623_dsi_te_pins[] = { 84, };
4449 +static int mt7623_dsi_te_funcs[] = { 1, };
4450 +static int mt7623_lcm_rst_pins[] = { 83, };
4451 +static int mt7623_lcm_rst_funcs[] = { 1, };
4452 +
4453 +/* MDC/MDIO */
4454 +static int mt7623_mdc_mdio_pins[] = { 275, 276, };
4455 +static int mt7623_mdc_mdio_funcs[] = { 1, 1, };
4456 +
4457 +/* MSDC */
4458 +static int mt7623_msdc0_pins[] = { 111, 112, 113, 114, 115, 116, 117, 118,
4459 + 119, 120, 121, };
4460 +static int mt7623_msdc0_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
4461 +static int mt7623_msdc1_pins[] = { 105, 106, 107, 108, 109, 110, };
4462 +static int mt7623_msdc1_funcs[] = { 1, 1, 1, 1, 1, 1, };
4463 +static int mt7623_msdc1_ins_pins[] = { 261, };
4464 +static int mt7623_msdc1_ins_funcs[] = { 1, };
4465 +static int mt7623_msdc1_wp_0_pins[] = { 29, };
4466 +static int mt7623_msdc1_wp_0_funcs[] = { 1, };
4467 +static int mt7623_msdc1_wp_1_pins[] = { 55, };
4468 +static int mt7623_msdc1_wp_1_funcs[] = { 3, };
4469 +static int mt7623_msdc1_wp_2_pins[] = { 209, };
4470 +static int mt7623_msdc1_wp_2_funcs[] = { 2, };
4471 +static int mt7623_msdc2_pins[] = { 85, 86, 87, 88, 89, 90, };
4472 +static int mt7623_msdc2_funcs[] = { 1, 1, 1, 1, 1, 1, };
4473 +static int mt7623_msdc3_pins[] = { 249, 250, 251, 252, 253, 254, 255, 256,
4474 + 257, 258, 259, 260, };
4475 +static int mt7623_msdc3_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
4476 +
4477 +/* NAND */
4478 +static int mt7623_nandc_pins[] = { 43, 47, 48, 111, 112, 113, 114, 115,
4479 + 116, 117, 118, 119, 120, 121, };
4480 +static int mt7623_nandc_funcs[] = { 1, 1, 1, 4, 4, 4, 4, 4, 4, 4, 4, 4,
4481 + 4, 4, };
4482 +static int mt7623_nandc_ceb0_pins[] = { 45, };
4483 +static int mt7623_nandc_ceb0_funcs[] = { 1, };
4484 +static int mt7623_nandc_ceb1_pins[] = { 44, };
4485 +static int mt7623_nandc_ceb1_funcs[] = { 1, };
4486 +
4487 +/* RTC */
4488 +static int mt7623_rtc_pins[] = { 10, };
4489 +static int mt7623_rtc_funcs[] = { 1, };
4490 +
4491 +/* OTG */
4492 +static int mt7623_otg_iddig0_0_pins[] = { 29, };
4493 +static int mt7623_otg_iddig0_0_funcs[] = { 1, };
4494 +static int mt7623_otg_iddig0_1_pins[] = { 44, };
4495 +static int mt7623_otg_iddig0_1_funcs[] = { 2, };
4496 +static int mt7623_otg_iddig0_2_pins[] = { 236, };
4497 +static int mt7623_otg_iddig0_2_funcs[] = { 2, };
4498 +static int mt7623_otg_iddig1_0_pins[] = { 27, };
4499 +static int mt7623_otg_iddig1_0_funcs[] = { 2, };
4500 +static int mt7623_otg_iddig1_1_pins[] = { 47, };
4501 +static int mt7623_otg_iddig1_1_funcs[] = { 2, };
4502 +static int mt7623_otg_iddig1_2_pins[] = { 238, };
4503 +static int mt7623_otg_iddig1_2_funcs[] = { 2, };
4504 +static int mt7623_otg_drv_vbus0_0_pins[] = { 28, };
4505 +static int mt7623_otg_drv_vbus0_0_funcs[] = { 1, };
4506 +static int mt7623_otg_drv_vbus0_1_pins[] = { 45, };
4507 +static int mt7623_otg_drv_vbus0_1_funcs[] = { 2, };
4508 +static int mt7623_otg_drv_vbus0_2_pins[] = { 237, };
4509 +static int mt7623_otg_drv_vbus0_2_funcs[] = { 2, };
4510 +static int mt7623_otg_drv_vbus1_0_pins[] = { 26, };
4511 +static int mt7623_otg_drv_vbus1_0_funcs[] = { 2, };
4512 +static int mt7623_otg_drv_vbus1_1_pins[] = { 48, };
4513 +static int mt7623_otg_drv_vbus1_1_funcs[] = { 2, };
4514 +static int mt7623_otg_drv_vbus1_2_pins[] = { 239, };
4515 +static int mt7623_otg_drv_vbus1_2_funcs[] = { 2, };
4516 +
4517 +/* PCIE */
4518 +static int mt7623_pcie0_0_perst_pins[] = { 208, };
4519 +static int mt7623_pcie0_0_perst_funcs[] = { 3, };
4520 +static int mt7623_pcie0_1_perst_pins[] = { 22, };
4521 +static int mt7623_pcie0_1_perst_funcs[] = { 2, };
4522 +static int mt7623_pcie1_0_perst_pins[] = { 209, };
4523 +static int mt7623_pcie1_0_perst_funcs[] = { 3, };
4524 +static int mt7623_pcie1_1_perst_pins[] = { 23, };
4525 +static int mt7623_pcie1_1_perst_funcs[] = { 2, };
4526 +static int mt7623_pcie2_0_perst_pins[] = { 24, };
4527 +static int mt7623_pcie2_0_perst_funcs[] = { 2, };
4528 +static int mt7623_pcie2_1_perst_pins[] = { 29, };
4529 +static int mt7623_pcie2_1_perst_funcs[] = { 6, };
4530 +static int mt7623_pcie0_0_wake_pins[] = { 28, };
4531 +static int mt7623_pcie0_0_wake_funcs[] = { 6, };
4532 +static int mt7623_pcie0_1_wake_pins[] = { 251, };
4533 +static int mt7623_pcie0_1_wake_funcs[] = { 6, };
4534 +static int mt7623_pcie1_0_wake_pins[] = { 27, };
4535 +static int mt7623_pcie1_0_wake_funcs[] = { 6, };
4536 +static int mt7623_pcie1_1_wake_pins[] = { 253, };
4537 +static int mt7623_pcie1_1_wake_funcs[] = { 6, };
4538 +static int mt7623_pcie2_0_wake_pins[] = { 26, };
4539 +static int mt7623_pcie2_0_wake_funcs[] = { 6, };
4540 +static int mt7623_pcie2_1_wake_pins[] = { 255, };
4541 +static int mt7623_pcie2_1_wake_funcs[] = { 6, };
4542 +static int mt7623_pcie0_clkreq_pins[] = { 250, };
4543 +static int mt7623_pcie0_clkreq_funcs[] = { 6, };
4544 +static int mt7623_pcie1_clkreq_pins[] = { 252, };
4545 +static int mt7623_pcie1_clkreq_funcs[] = { 6, };
4546 +static int mt7623_pcie2_clkreq_pins[] = { 254, };
4547 +static int mt7623_pcie2_clkreq_funcs[] = { 6, };
4548 +
4549 +/* the pcie_*_rev are only used for MT7623 */
4550 +static int mt7623_pcie0_0_rev_perst_pins[] = { 208, };
4551 +static int mt7623_pcie0_0_rev_perst_funcs[] = { 11, };
4552 +static int mt7623_pcie0_1_rev_perst_pins[] = { 22, };
4553 +static int mt7623_pcie0_1_rev_perst_funcs[] = { 10, };
4554 +static int mt7623_pcie1_0_rev_perst_pins[] = { 209, };
4555 +static int mt7623_pcie1_0_rev_perst_funcs[] = { 11, };
4556 +static int mt7623_pcie1_1_rev_perst_pins[] = { 23, };
4557 +static int mt7623_pcie1_1_rev_perst_funcs[] = { 10, };
4558 +static int mt7623_pcie2_0_rev_perst_pins[] = { 24, };
4559 +static int mt7623_pcie2_0_rev_perst_funcs[] = { 11, };
4560 +static int mt7623_pcie2_1_rev_perst_pins[] = { 29, };
4561 +static int mt7623_pcie2_1_rev_perst_funcs[] = { 14, };
4562 +
4563 +/* PCM */
4564 +static int mt7623_pcm_clk_0_pins[] = { 18, };
4565 +static int mt7623_pcm_clk_0_funcs[] = { 1, };
4566 +static int mt7623_pcm_clk_1_pins[] = { 17, };
4567 +static int mt7623_pcm_clk_1_funcs[] = { 3, };
4568 +static int mt7623_pcm_clk_2_pins[] = { 35, };
4569 +static int mt7623_pcm_clk_2_funcs[] = { 3, };
4570 +static int mt7623_pcm_clk_3_pins[] = { 50, };
4571 +static int mt7623_pcm_clk_3_funcs[] = { 3, };
4572 +static int mt7623_pcm_clk_4_pins[] = { 74, };
4573 +static int mt7623_pcm_clk_4_funcs[] = { 3, };
4574 +static int mt7623_pcm_clk_5_pins[] = { 191, };
4575 +static int mt7623_pcm_clk_5_funcs[] = { 3, };
4576 +static int mt7623_pcm_clk_6_pins[] = { 196, };
4577 +static int mt7623_pcm_clk_6_funcs[] = { 3, };
4578 +static int mt7623_pcm_sync_0_pins[] = { 19, };
4579 +static int mt7623_pcm_sync_0_funcs[] = { 1, };
4580 +static int mt7623_pcm_sync_1_pins[] = { 30, };
4581 +static int mt7623_pcm_sync_1_funcs[] = { 3, };
4582 +static int mt7623_pcm_sync_2_pins[] = { 36, };
4583 +static int mt7623_pcm_sync_2_funcs[] = { 3, };
4584 +static int mt7623_pcm_sync_3_pins[] = { 52, };
4585 +static int mt7623_pcm_sync_3_funcs[] = { 31, };
4586 +static int mt7623_pcm_sync_4_pins[] = { 73, };
4587 +static int mt7623_pcm_sync_4_funcs[] = { 3, };
4588 +static int mt7623_pcm_sync_5_pins[] = { 192, };
4589 +static int mt7623_pcm_sync_5_funcs[] = { 3, };
4590 +static int mt7623_pcm_sync_6_pins[] = { 197, };
4591 +static int mt7623_pcm_sync_6_funcs[] = { 3, };
4592 +static int mt7623_pcm_rx_0_pins[] = { 20, };
4593 +static int mt7623_pcm_rx_0_funcs[] = { 1, };
4594 +static int mt7623_pcm_rx_1_pins[] = { 16, };
4595 +static int mt7623_pcm_rx_1_funcs[] = { 3, };
4596 +static int mt7623_pcm_rx_2_pins[] = { 34, };
4597 +static int mt7623_pcm_rx_2_funcs[] = { 3, };
4598 +static int mt7623_pcm_rx_3_pins[] = { 51, };
4599 +static int mt7623_pcm_rx_3_funcs[] = { 3, };
4600 +static int mt7623_pcm_rx_4_pins[] = { 72, };
4601 +static int mt7623_pcm_rx_4_funcs[] = { 3, };
4602 +static int mt7623_pcm_rx_5_pins[] = { 190, };
4603 +static int mt7623_pcm_rx_5_funcs[] = { 3, };
4604 +static int mt7623_pcm_rx_6_pins[] = { 195, };
4605 +static int mt7623_pcm_rx_6_funcs[] = { 3, };
4606 +static int mt7623_pcm_tx_0_pins[] = { 21, };
4607 +static int mt7623_pcm_tx_0_funcs[] = { 1, };
4608 +static int mt7623_pcm_tx_1_pins[] = { 32, };
4609 +static int mt7623_pcm_tx_1_funcs[] = { 3, };
4610 +static int mt7623_pcm_tx_2_pins[] = { 33, };
4611 +static int mt7623_pcm_tx_2_funcs[] = { 3, };
4612 +static int mt7623_pcm_tx_3_pins[] = { 38, };
4613 +static int mt7623_pcm_tx_3_funcs[] = { 3, };
4614 +static int mt7623_pcm_tx_4_pins[] = { 49, };
4615 +static int mt7623_pcm_tx_4_funcs[] = { 3, };
4616 +static int mt7623_pcm_tx_5_pins[] = { 189, };
4617 +static int mt7623_pcm_tx_5_funcs[] = { 3, };
4618 +static int mt7623_pcm_tx_6_pins[] = { 194, };
4619 +static int mt7623_pcm_tx_6_funcs[] = { 3, };
4620 +
4621 +/* PWM */
4622 +static int mt7623_pwm_ch1_0_pins[] = { 203, };
4623 +static int mt7623_pwm_ch1_0_funcs[] = { 1, };
4624 +static int mt7623_pwm_ch1_1_pins[] = { 208, };
4625 +static int mt7623_pwm_ch1_1_funcs[] = { 2, };
4626 +static int mt7623_pwm_ch1_2_pins[] = { 72, };
4627 +static int mt7623_pwm_ch1_2_funcs[] = { 4, };
4628 +static int mt7623_pwm_ch1_3_pins[] = { 88, };
4629 +static int mt7623_pwm_ch1_3_funcs[] = { 3, };
4630 +static int mt7623_pwm_ch1_4_pins[] = { 108, };
4631 +static int mt7623_pwm_ch1_4_funcs[] = { 3, };
4632 +static int mt7623_pwm_ch2_0_pins[] = { 204, };
4633 +static int mt7623_pwm_ch2_0_funcs[] = { 1, };
4634 +static int mt7623_pwm_ch2_1_pins[] = { 53, };
4635 +static int mt7623_pwm_ch2_1_funcs[] = { 5, };
4636 +static int mt7623_pwm_ch2_2_pins[] = { 88, };
4637 +static int mt7623_pwm_ch2_2_funcs[] = { 6, };
4638 +static int mt7623_pwm_ch2_3_pins[] = { 108, };
4639 +static int mt7623_pwm_ch2_3_funcs[] = { 6, };
4640 +static int mt7623_pwm_ch2_4_pins[] = { 209, };
4641 +static int mt7623_pwm_ch2_4_funcs[] = { 5, };
4642 +static int mt7623_pwm_ch3_0_pins[] = { 205, };
4643 +static int mt7623_pwm_ch3_0_funcs[] = { 1, };
4644 +static int mt7623_pwm_ch3_1_pins[] = { 55, };
4645 +static int mt7623_pwm_ch3_1_funcs[] = { 5, };
4646 +static int mt7623_pwm_ch3_2_pins[] = { 89, };
4647 +static int mt7623_pwm_ch3_2_funcs[] = { 6, };
4648 +static int mt7623_pwm_ch3_3_pins[] = { 109, };
4649 +static int mt7623_pwm_ch3_3_funcs[] = { 6, };
4650 +static int mt7623_pwm_ch4_0_pins[] = { 206, };
4651 +static int mt7623_pwm_ch4_0_funcs[] = { 1, };
4652 +static int mt7623_pwm_ch4_1_pins[] = { 90, };
4653 +static int mt7623_pwm_ch4_1_funcs[] = { 6, };
4654 +static int mt7623_pwm_ch4_2_pins[] = { 110, };
4655 +static int mt7623_pwm_ch4_2_funcs[] = { 6, };
4656 +static int mt7623_pwm_ch4_3_pins[] = { 124, };
4657 +static int mt7623_pwm_ch4_3_funcs[] = { 5, };
4658 +static int mt7623_pwm_ch5_0_pins[] = { 207, };
4659 +static int mt7623_pwm_ch5_0_funcs[] = { 1, };
4660 +static int mt7623_pwm_ch5_1_pins[] = { 125, };
4661 +static int mt7623_pwm_ch5_1_funcs[] = { 5, };
4662 +
4663 +/* PWRAP */
4664 +static int mt7623_pwrap_pins[] = { 0, 1, 2, 3, 4, 5, 6, };
4665 +static int mt7623_pwrap_funcs[] = { 1, 1, 1, 1, 1, 1, 1, };
4666 +
4667 +/* SPDIF */
4668 +static int mt7623_spdif_in0_0_pins[] = { 56, };
4669 +static int mt7623_spdif_in0_0_funcs[] = { 3, };
4670 +static int mt7623_spdif_in0_1_pins[] = { 201, };
4671 +static int mt7623_spdif_in0_1_funcs[] = { 1, };
4672 +static int mt7623_spdif_in1_0_pins[] = { 54, };
4673 +static int mt7623_spdif_in1_0_funcs[] = { 3, };
4674 +static int mt7623_spdif_in1_1_pins[] = { 202, };
4675 +static int mt7623_spdif_in1_1_funcs[] = { 1, };
4676 +static int mt7623_spdif_out_pins[] = { 202, };
4677 +static int mt7623_spdif_out_funcs[] = { 1, };
4678 +
4679 +/* SPI */
4680 +static int mt7623_spi0_pins[] = { 53, 54, 55, 56, };
4681 +static int mt7623_spi0_funcs[] = { 1, 1, 1, 1, };
4682 +static int mt7623_spi1_pins[] = { 7, 199, 8, 9, };
4683 +static int mt7623_spi1_funcs[] = { 1, 1, 1, 1, };
4684 +static int mt7623_spi2_pins[] = { 101, 104, 102, 103, };
4685 +static int mt7623_spi2_funcs[] = { 1, 1, 1, 1, };
4686 +
4687 +/* UART */
4688 +static int mt7623_uart0_0_txd_rxd_pins[] = { 79, 80, };
4689 +static int mt7623_uart0_0_txd_rxd_funcs[] = { 1, 1, };
4690 +static int mt7623_uart0_1_txd_rxd_pins[] = { 87, 88, };
4691 +static int mt7623_uart0_1_txd_rxd_funcs[] = { 5, 5, };
4692 +static int mt7623_uart0_2_txd_rxd_pins[] = { 107, 108, };
4693 +static int mt7623_uart0_2_txd_rxd_funcs[] = { 5, 5, };
4694 +static int mt7623_uart0_3_txd_rxd_pins[] = { 123, 122, };
4695 +static int mt7623_uart0_3_txd_rxd_funcs[] = { 5, 5, };
4696 +static int mt7623_uart0_rts_cts_pins[] = { 22, 23, };
4697 +static int mt7623_uart0_rts_cts_funcs[] = { 1, 1, };
4698 +static int mt7623_uart1_0_txd_rxd_pins[] = { 81, 82, };
4699 +static int mt7623_uart1_0_txd_rxd_funcs[] = { 1, 1, };
4700 +static int mt7623_uart1_1_txd_rxd_pins[] = { 89, 90, };
4701 +static int mt7623_uart1_1_txd_rxd_funcs[] = { 5, 5, };
4702 +static int mt7623_uart1_2_txd_rxd_pins[] = { 109, 110, };
4703 +static int mt7623_uart1_2_txd_rxd_funcs[] = { 5, 5, };
4704 +static int mt7623_uart1_rts_cts_pins[] = { 24, 25, };
4705 +static int mt7623_uart1_rts_cts_funcs[] = { 1, 1, };
4706 +static int mt7623_uart2_0_txd_rxd_pins[] = { 14, 15, };
4707 +static int mt7623_uart2_0_txd_rxd_funcs[] = { 1, 1, };
4708 +static int mt7623_uart2_1_txd_rxd_pins[] = { 200, 201, };
4709 +static int mt7623_uart2_1_txd_rxd_funcs[] = { 6, 6, };
4710 +static int mt7623_uart2_rts_cts_pins[] = { 242, 243, };
4711 +static int mt7623_uart2_rts_cts_funcs[] = { 1, 1, };
4712 +static int mt7623_uart3_txd_rxd_pins[] = { 242, 243, };
4713 +static int mt7623_uart3_txd_rxd_funcs[] = { 2, 2, };
4714 +static int mt7623_uart3_rts_cts_pins[] = { 26, 27, };
4715 +static int mt7623_uart3_rts_cts_funcs[] = { 1, 1, };
4716 +
4717 +/* Watchdog */
4718 +static int mt7623_watchdog_0_pins[] = { 11, };
4719 +static int mt7623_watchdog_0_funcs[] = { 1, };
4720 +static int mt7623_watchdog_1_pins[] = { 121, };
4721 +static int mt7623_watchdog_1_funcs[] = { 5, };
4722 +
4723 +static const struct group_desc mt7623_groups[] = {
4724 + PINCTRL_PIN_GROUP("aud_ext_clk0", mt7623_aud_ext_clk0),
4725 + PINCTRL_PIN_GROUP("aud_ext_clk1", mt7623_aud_ext_clk1),
4726 + PINCTRL_PIN_GROUP("dsi_te", mt7623_dsi_te),
4727 + PINCTRL_PIN_GROUP("disp_pwm_0", mt7623_disp_pwm_0),
4728 + PINCTRL_PIN_GROUP("disp_pwm_1", mt7623_disp_pwm_1),
4729 + PINCTRL_PIN_GROUP("disp_pwm_2", mt7623_disp_pwm_2),
4730 + PINCTRL_PIN_GROUP("ephy", mt7623_ephy),
4731 + PINCTRL_PIN_GROUP("esw_int", mt7623_esw_int),
4732 + PINCTRL_PIN_GROUP("esw_rst", mt7623_esw_rst),
4733 + PINCTRL_PIN_GROUP("ext_sdio", mt7623_ext_sdio),
4734 + PINCTRL_PIN_GROUP("hdmi_cec", mt7623_hdmi_cec),
4735 + PINCTRL_PIN_GROUP("hdmi_htplg", mt7623_hdmi_htplg),
4736 + PINCTRL_PIN_GROUP("hdmi_i2c", mt7623_hdmi_i2c),
4737 + PINCTRL_PIN_GROUP("hdmi_rx", mt7623_hdmi_rx),
4738 + PINCTRL_PIN_GROUP("hdmi_rx_i2c", mt7623_hdmi_rx_i2c),
4739 + PINCTRL_PIN_GROUP("i2c0", mt7623_i2c0),
4740 + PINCTRL_PIN_GROUP("i2c1_0", mt7623_i2c1_0),
4741 + PINCTRL_PIN_GROUP("i2c1_1", mt7623_i2c1_1),
4742 + PINCTRL_PIN_GROUP("i2c1_2", mt7623_i2c1_2),
4743 + PINCTRL_PIN_GROUP("i2c1_3", mt7623_i2c1_3),
4744 + PINCTRL_PIN_GROUP("i2c1_4", mt7623_i2c1_4),
4745 + PINCTRL_PIN_GROUP("i2c2_0", mt7623_i2c2_0),
4746 + PINCTRL_PIN_GROUP("i2c2_1", mt7623_i2c2_1),
4747 + PINCTRL_PIN_GROUP("i2c2_2", mt7623_i2c2_2),
4748 + PINCTRL_PIN_GROUP("i2c2_3", mt7623_i2c2_3),
4749 + PINCTRL_PIN_GROUP("i2s0", mt7623_i2s0),
4750 + PINCTRL_PIN_GROUP("i2s1", mt7623_i2s1),
4751 + PINCTRL_PIN_GROUP("i2s4", mt7623_i2s4),
4752 + PINCTRL_PIN_GROUP("i2s5", mt7623_i2s5),
4753 + PINCTRL_PIN_GROUP("i2s2_bclk_lrclk_mclk", mt7623_i2s2_bclk_lrclk_mclk),
4754 + PINCTRL_PIN_GROUP("i2s3_bclk_lrclk_mclk", mt7623_i2s3_bclk_lrclk_mclk),
4755 + PINCTRL_PIN_GROUP("i2s2_data_in", mt7623_i2s2_data_in),
4756 + PINCTRL_PIN_GROUP("i2s3_data_in", mt7623_i2s3_data_in),
4757 + PINCTRL_PIN_GROUP("i2s2_data_0", mt7623_i2s2_data_0),
4758 + PINCTRL_PIN_GROUP("i2s2_data_1", mt7623_i2s2_data_1),
4759 + PINCTRL_PIN_GROUP("i2s3_data_0", mt7623_i2s3_data_0),
4760 + PINCTRL_PIN_GROUP("i2s3_data_1", mt7623_i2s3_data_1),
4761 + PINCTRL_PIN_GROUP("ir", mt7623_ir),
4762 + PINCTRL_PIN_GROUP("lcm_rst", mt7623_lcm_rst),
4763 + PINCTRL_PIN_GROUP("mdc_mdio", mt7623_mdc_mdio),
4764 + PINCTRL_PIN_GROUP("mipi_tx", mt7623_mipi_tx),
4765 + PINCTRL_PIN_GROUP("msdc0", mt7623_msdc0),
4766 + PINCTRL_PIN_GROUP("msdc1", mt7623_msdc1),
4767 + PINCTRL_PIN_GROUP("msdc1_ins", mt7623_msdc1_ins),
4768 + PINCTRL_PIN_GROUP("msdc1_wp_0", mt7623_msdc1_wp_0),
4769 + PINCTRL_PIN_GROUP("msdc1_wp_1", mt7623_msdc1_wp_1),
4770 + PINCTRL_PIN_GROUP("msdc1_wp_2", mt7623_msdc1_wp_2),
4771 + PINCTRL_PIN_GROUP("msdc2", mt7623_msdc2),
4772 + PINCTRL_PIN_GROUP("msdc3", mt7623_msdc3),
4773 + PINCTRL_PIN_GROUP("nandc", mt7623_nandc),
4774 + PINCTRL_PIN_GROUP("nandc_ceb0", mt7623_nandc_ceb0),
4775 + PINCTRL_PIN_GROUP("nandc_ceb1", mt7623_nandc_ceb1),
4776 + PINCTRL_PIN_GROUP("otg_iddig0_0", mt7623_otg_iddig0_0),
4777 + PINCTRL_PIN_GROUP("otg_iddig0_1", mt7623_otg_iddig0_1),
4778 + PINCTRL_PIN_GROUP("otg_iddig0_2", mt7623_otg_iddig0_2),
4779 + PINCTRL_PIN_GROUP("otg_iddig1_0", mt7623_otg_iddig1_0),
4780 + PINCTRL_PIN_GROUP("otg_iddig1_1", mt7623_otg_iddig1_1),
4781 + PINCTRL_PIN_GROUP("otg_iddig1_2", mt7623_otg_iddig1_2),
4782 + PINCTRL_PIN_GROUP("otg_drv_vbus0_0", mt7623_otg_drv_vbus0_0),
4783 + PINCTRL_PIN_GROUP("otg_drv_vbus0_1", mt7623_otg_drv_vbus0_1),
4784 + PINCTRL_PIN_GROUP("otg_drv_vbus0_2", mt7623_otg_drv_vbus0_2),
4785 + PINCTRL_PIN_GROUP("otg_drv_vbus1_0", mt7623_otg_drv_vbus1_0),
4786 + PINCTRL_PIN_GROUP("otg_drv_vbus1_1", mt7623_otg_drv_vbus1_1),
4787 + PINCTRL_PIN_GROUP("otg_drv_vbus1_2", mt7623_otg_drv_vbus1_2),
4788 + PINCTRL_PIN_GROUP("pcie0_0_perst", mt7623_pcie0_0_perst),
4789 + PINCTRL_PIN_GROUP("pcie0_1_perst", mt7623_pcie0_1_perst),
4790 + PINCTRL_PIN_GROUP("pcie1_0_perst", mt7623_pcie1_0_perst),
4791 + PINCTRL_PIN_GROUP("pcie1_1_perst", mt7623_pcie1_1_perst),
4792 + PINCTRL_PIN_GROUP("pcie1_1_perst", mt7623_pcie1_1_perst),
4793 + PINCTRL_PIN_GROUP("pcie0_0_rev_perst", mt7623_pcie0_0_rev_perst),
4794 + PINCTRL_PIN_GROUP("pcie0_1_rev_perst", mt7623_pcie0_1_rev_perst),
4795 + PINCTRL_PIN_GROUP("pcie1_0_rev_perst", mt7623_pcie1_0_rev_perst),
4796 + PINCTRL_PIN_GROUP("pcie1_1_rev_perst", mt7623_pcie1_1_rev_perst),
4797 + PINCTRL_PIN_GROUP("pcie2_0_rev_perst", mt7623_pcie2_0_rev_perst),
4798 + PINCTRL_PIN_GROUP("pcie2_1_rev_perst", mt7623_pcie2_1_rev_perst),
4799 + PINCTRL_PIN_GROUP("pcie2_0_perst", mt7623_pcie2_0_perst),
4800 + PINCTRL_PIN_GROUP("pcie2_1_perst", mt7623_pcie2_1_perst),
4801 + PINCTRL_PIN_GROUP("pcie0_0_wake", mt7623_pcie0_0_wake),
4802 + PINCTRL_PIN_GROUP("pcie0_1_wake", mt7623_pcie0_1_wake),
4803 + PINCTRL_PIN_GROUP("pcie1_0_wake", mt7623_pcie1_0_wake),
4804 + PINCTRL_PIN_GROUP("pcie1_1_wake", mt7623_pcie1_1_wake),
4805 + PINCTRL_PIN_GROUP("pcie2_0_wake", mt7623_pcie2_0_wake),
4806 + PINCTRL_PIN_GROUP("pcie2_1_wake", mt7623_pcie2_1_wake),
4807 + PINCTRL_PIN_GROUP("pcie0_clkreq", mt7623_pcie0_clkreq),
4808 + PINCTRL_PIN_GROUP("pcie1_clkreq", mt7623_pcie1_clkreq),
4809 + PINCTRL_PIN_GROUP("pcie2_clkreq", mt7623_pcie2_clkreq),
4810 + PINCTRL_PIN_GROUP("pcm_clk_0", mt7623_pcm_clk_0),
4811 + PINCTRL_PIN_GROUP("pcm_clk_1", mt7623_pcm_clk_1),
4812 + PINCTRL_PIN_GROUP("pcm_clk_2", mt7623_pcm_clk_2),
4813 + PINCTRL_PIN_GROUP("pcm_clk_3", mt7623_pcm_clk_3),
4814 + PINCTRL_PIN_GROUP("pcm_clk_4", mt7623_pcm_clk_4),
4815 + PINCTRL_PIN_GROUP("pcm_clk_5", mt7623_pcm_clk_5),
4816 + PINCTRL_PIN_GROUP("pcm_clk_6", mt7623_pcm_clk_6),
4817 + PINCTRL_PIN_GROUP("pcm_sync_0", mt7623_pcm_sync_0),
4818 + PINCTRL_PIN_GROUP("pcm_sync_1", mt7623_pcm_sync_1),
4819 + PINCTRL_PIN_GROUP("pcm_sync_2", mt7623_pcm_sync_2),
4820 + PINCTRL_PIN_GROUP("pcm_sync_3", mt7623_pcm_sync_3),
4821 + PINCTRL_PIN_GROUP("pcm_sync_4", mt7623_pcm_sync_4),
4822 + PINCTRL_PIN_GROUP("pcm_sync_5", mt7623_pcm_sync_5),
4823 + PINCTRL_PIN_GROUP("pcm_sync_6", mt7623_pcm_sync_6),
4824 + PINCTRL_PIN_GROUP("pcm_rx_0", mt7623_pcm_rx_0),
4825 + PINCTRL_PIN_GROUP("pcm_rx_1", mt7623_pcm_rx_1),
4826 + PINCTRL_PIN_GROUP("pcm_rx_2", mt7623_pcm_rx_2),
4827 + PINCTRL_PIN_GROUP("pcm_rx_3", mt7623_pcm_rx_3),
4828 + PINCTRL_PIN_GROUP("pcm_rx_4", mt7623_pcm_rx_4),
4829 + PINCTRL_PIN_GROUP("pcm_rx_5", mt7623_pcm_rx_5),
4830 + PINCTRL_PIN_GROUP("pcm_rx_6", mt7623_pcm_rx_6),
4831 + PINCTRL_PIN_GROUP("pcm_tx_0", mt7623_pcm_tx_0),
4832 + PINCTRL_PIN_GROUP("pcm_tx_1", mt7623_pcm_tx_1),
4833 + PINCTRL_PIN_GROUP("pcm_tx_2", mt7623_pcm_tx_2),
4834 + PINCTRL_PIN_GROUP("pcm_tx_3", mt7623_pcm_tx_3),
4835 + PINCTRL_PIN_GROUP("pcm_tx_4", mt7623_pcm_tx_4),
4836 + PINCTRL_PIN_GROUP("pcm_tx_5", mt7623_pcm_tx_5),
4837 + PINCTRL_PIN_GROUP("pcm_tx_6", mt7623_pcm_tx_6),
4838 + PINCTRL_PIN_GROUP("pwm_ch1_0", mt7623_pwm_ch1_0),
4839 + PINCTRL_PIN_GROUP("pwm_ch1_1", mt7623_pwm_ch1_1),
4840 + PINCTRL_PIN_GROUP("pwm_ch1_2", mt7623_pwm_ch1_2),
4841 + PINCTRL_PIN_GROUP("pwm_ch1_3", mt7623_pwm_ch1_3),
4842 + PINCTRL_PIN_GROUP("pwm_ch1_4", mt7623_pwm_ch1_4),
4843 + PINCTRL_PIN_GROUP("pwm_ch2_0", mt7623_pwm_ch2_0),
4844 + PINCTRL_PIN_GROUP("pwm_ch2_1", mt7623_pwm_ch2_1),
4845 + PINCTRL_PIN_GROUP("pwm_ch2_2", mt7623_pwm_ch2_2),
4846 + PINCTRL_PIN_GROUP("pwm_ch2_3", mt7623_pwm_ch2_3),
4847 + PINCTRL_PIN_GROUP("pwm_ch2_4", mt7623_pwm_ch2_4),
4848 + PINCTRL_PIN_GROUP("pwm_ch3_0", mt7623_pwm_ch3_0),
4849 + PINCTRL_PIN_GROUP("pwm_ch3_1", mt7623_pwm_ch3_1),
4850 + PINCTRL_PIN_GROUP("pwm_ch3_2", mt7623_pwm_ch3_2),
4851 + PINCTRL_PIN_GROUP("pwm_ch3_3", mt7623_pwm_ch3_3),
4852 + PINCTRL_PIN_GROUP("pwm_ch4_0", mt7623_pwm_ch4_0),
4853 + PINCTRL_PIN_GROUP("pwm_ch4_1", mt7623_pwm_ch4_1),
4854 + PINCTRL_PIN_GROUP("pwm_ch4_2", mt7623_pwm_ch4_2),
4855 + PINCTRL_PIN_GROUP("pwm_ch4_3", mt7623_pwm_ch4_3),
4856 + PINCTRL_PIN_GROUP("pwm_ch5_0", mt7623_pwm_ch5_0),
4857 + PINCTRL_PIN_GROUP("pwm_ch5_1", mt7623_pwm_ch5_1),
4858 + PINCTRL_PIN_GROUP("pwrap", mt7623_pwrap),
4859 + PINCTRL_PIN_GROUP("rtc", mt7623_rtc),
4860 + PINCTRL_PIN_GROUP("spdif_in0_0", mt7623_spdif_in0_0),
4861 + PINCTRL_PIN_GROUP("spdif_in0_1", mt7623_spdif_in0_1),
4862 + PINCTRL_PIN_GROUP("spdif_in1_0", mt7623_spdif_in1_0),
4863 + PINCTRL_PIN_GROUP("spdif_in1_1", mt7623_spdif_in1_1),
4864 + PINCTRL_PIN_GROUP("spdif_out", mt7623_spdif_out),
4865 + PINCTRL_PIN_GROUP("spi0", mt7623_spi0),
4866 + PINCTRL_PIN_GROUP("spi1", mt7623_spi1),
4867 + PINCTRL_PIN_GROUP("spi2", mt7623_spi2),
4868 + PINCTRL_PIN_GROUP("uart0_0_txd_rxd", mt7623_uart0_0_txd_rxd),
4869 + PINCTRL_PIN_GROUP("uart0_1_txd_rxd", mt7623_uart0_1_txd_rxd),
4870 + PINCTRL_PIN_GROUP("uart0_2_txd_rxd", mt7623_uart0_2_txd_rxd),
4871 + PINCTRL_PIN_GROUP("uart0_3_txd_rxd", mt7623_uart0_3_txd_rxd),
4872 + PINCTRL_PIN_GROUP("uart1_0_txd_rxd", mt7623_uart1_0_txd_rxd),
4873 + PINCTRL_PIN_GROUP("uart1_1_txd_rxd", mt7623_uart1_1_txd_rxd),
4874 + PINCTRL_PIN_GROUP("uart1_2_txd_rxd", mt7623_uart1_2_txd_rxd),
4875 + PINCTRL_PIN_GROUP("uart2_0_txd_rxd", mt7623_uart2_0_txd_rxd),
4876 + PINCTRL_PIN_GROUP("uart2_1_txd_rxd", mt7623_uart2_1_txd_rxd),
4877 + PINCTRL_PIN_GROUP("uart3_txd_rxd", mt7623_uart3_txd_rxd),
4878 + PINCTRL_PIN_GROUP("uart0_rts_cts", mt7623_uart0_rts_cts),
4879 + PINCTRL_PIN_GROUP("uart1_rts_cts", mt7623_uart1_rts_cts),
4880 + PINCTRL_PIN_GROUP("uart2_rts_cts", mt7623_uart2_rts_cts),
4881 + PINCTRL_PIN_GROUP("uart3_rts_cts", mt7623_uart3_rts_cts),
4882 + PINCTRL_PIN_GROUP("watchdog_0", mt7623_watchdog_0),
4883 + PINCTRL_PIN_GROUP("watchdog_1", mt7623_watchdog_1),
4884 +};
4885 +
4886 +/* Joint those groups owning the same capability in user point of view which
4887 + * allows that people tend to use through the device tree.
4888 + */
4889 +static const char *mt7623_aud_clk_groups[] = { "aud_ext_clk0",
4890 + "aud_ext_clk1", };
4891 +static const char *mt7623_disp_pwm_groups[] = { "disp_pwm_0", "disp_pwm_1",
4892 + "disp_pwm_2", };
4893 +static const char *mt7623_ethernet_groups[] = { "esw_int", "esw_rst",
4894 + "ephy", "mdc_mdio", };
4895 +static const char *mt7623_ext_sdio_groups[] = { "ext_sdio", };
4896 +static const char *mt7623_hdmi_groups[] = { "hdmi_cec", "hdmi_htplg",
4897 + "hdmi_i2c", "hdmi_rx",
4898 + "hdmi_rx_i2c", };
4899 +static const char *mt7623_i2c_groups[] = { "i2c0", "i2c1_0", "i2c1_1",
4900 + "i2c1_2", "i2c1_3", "i2c1_4",
4901 + "i2c2_0", "i2c2_1", "i2c2_2",
4902 + "i2c2_3", };
4903 +static const char *mt7623_i2s_groups[] = { "i2s0", "i2s1",
4904 + "i2s2_bclk_lrclk_mclk",
4905 + "i2s3_bclk_lrclk_mclk",
4906 + "i2s4", "i2s5",
4907 + "i2s2_data_in", "i2s3_data_in",
4908 + "i2s2_data_0", "i2s2_data_1",
4909 + "i2s3_data_0", "i2s3_data_1", };
4910 +static const char *mt7623_ir_groups[] = { "ir", };
4911 +static const char *mt7623_lcd_groups[] = { "dsi_te", "lcm_rst", "mipi_tx", };
4912 +static const char *mt7623_msdc_groups[] = { "msdc0", "msdc1", "msdc1_ins",
4913 + "msdc1_wp_0", "msdc1_wp_1",
4914 + "msdc1_wp_2", "msdc2",
4915 + "msdc3", };
4916 +static const char *mt7623_nandc_groups[] = { "nandc", "nandc_ceb0",
4917 + "nandc_ceb1", };
4918 +static const char *mt7623_otg_groups[] = { "otg_iddig0_0", "otg_iddig0_1",
4919 + "otg_iddig0_2", "otg_iddig1_0",
4920 + "otg_iddig1_1", "otg_iddig1_2",
4921 + "otg_drv_vbus0_0",
4922 + "otg_drv_vbus0_1",
4923 + "otg_drv_vbus0_2",
4924 + "otg_drv_vbus1_0",
4925 + "otg_drv_vbus1_1",
4926 + "otg_drv_vbus1_2", };
4927 +static const char *mt7623_pcie_groups[] = { "pcie0_0_perst", "pcie0_1_perst",
4928 + "pcie1_0_perst", "pcie1_1_perst",
4929 + "pcie2_0_perst", "pcie2_1_perst",
4930 + "pcie0_0_rev_perst",
4931 + "pcie0_1_rev_perst",
4932 + "pcie1_0_rev_perst",
4933 + "pcie1_1_rev_perst",
4934 + "pcie2_0_rev_perst",
4935 + "pcie2_1_rev_perst",
4936 + "pcie0_0_wake", "pcie0_1_wake",
4937 + "pcie2_0_wake", "pcie2_1_wake",
4938 + "pcie0_clkreq", "pcie1_clkreq",
4939 + "pcie2_clkreq", };
4940 +static const char *mt7623_pcm_groups[] = { "pcm_clk_0", "pcm_clk_1",
4941 + "pcm_clk_2", "pcm_clk_3",
4942 + "pcm_clk_4", "pcm_clk_5",
4943 + "pcm_clk_6", "pcm_sync_0",
4944 + "pcm_sync_1", "pcm_sync_2",
4945 + "pcm_sync_3", "pcm_sync_4",
4946 + "pcm_sync_5", "pcm_sync_6",
4947 + "pcm_rx_0", "pcm_rx_1",
4948 + "pcm_rx_2", "pcm_rx_3",
4949 + "pcm_rx_4", "pcm_rx_5",
4950 + "pcm_rx_6", "pcm_tx_0",
4951 + "pcm_tx_1", "pcm_tx_2",
4952 + "pcm_tx_3", "pcm_tx_4",
4953 + "pcm_tx_5", "pcm_tx_6", };
4954 +static const char *mt7623_pwm_groups[] = { "pwm_ch1_0", "pwm_ch1_1",
4955 + "pwm_ch1_2", "pwm_ch2_0",
4956 + "pwm_ch2_1", "pwm_ch2_2",
4957 + "pwm_ch3_0", "pwm_ch3_1",
4958 + "pwm_ch3_2", "pwm_ch4_0",
4959 + "pwm_ch4_1", "pwm_ch4_2",
4960 + "pwm_ch4_3", "pwm_ch5_0",
4961 + "pwm_ch5_1", "pwm_ch5_2",
4962 + "pwm_ch6_0", "pwm_ch6_1",
4963 + "pwm_ch6_2", "pwm_ch6_3",
4964 + "pwm_ch7_0", "pwm_ch7_1",
4965 + "pwm_ch7_2", };
4966 +static const char *mt7623_pwrap_groups[] = { "pwrap", };
4967 +static const char *mt7623_rtc_groups[] = { "rtc", };
4968 +static const char *mt7623_spi_groups[] = { "spi0", "spi2", "spi2", };
4969 +static const char *mt7623_spdif_groups[] = { "spdif_in0_0", "spdif_in0_1",
4970 + "spdif_in1_0", "spdif_in1_1",
4971 + "spdif_out", };
4972 +static const char *mt7623_uart_groups[] = { "uart0_0_txd_rxd",
4973 + "uart0_1_txd_rxd",
4974 + "uart0_2_txd_rxd",
4975 + "uart0_3_txd_rxd",
4976 + "uart1_0_txd_rxd",
4977 + "uart1_1_txd_rxd",
4978 + "uart1_2_txd_rxd",
4979 + "uart2_0_txd_rxd",
4980 + "uart2_1_txd_rxd",
4981 + "uart3_txd_rxd",
4982 + "uart0_rts_cts",
4983 + "uart1_rts_cts",
4984 + "uart2_rts_cts",
4985 + "uart3_rts_cts", };
4986 +static const char *mt7623_wdt_groups[] = { "watchdog_0", "watchdog_1", };
4987 +
4988 +static const struct function_desc mt7623_functions[] = {
4989 + {"audck", mt7623_aud_clk_groups, ARRAY_SIZE(mt7623_aud_clk_groups)},
4990 + {"disp", mt7623_disp_pwm_groups, ARRAY_SIZE(mt7623_disp_pwm_groups)},
4991 + {"eth", mt7623_ethernet_groups, ARRAY_SIZE(mt7623_ethernet_groups)},
4992 + {"sdio", mt7623_ext_sdio_groups, ARRAY_SIZE(mt7623_ext_sdio_groups)},
4993 + {"hdmi", mt7623_hdmi_groups, ARRAY_SIZE(mt7623_hdmi_groups)},
4994 + {"i2c", mt7623_i2c_groups, ARRAY_SIZE(mt7623_i2c_groups)},
4995 + {"i2s", mt7623_i2s_groups, ARRAY_SIZE(mt7623_i2s_groups)},
4996 + {"ir", mt7623_ir_groups, ARRAY_SIZE(mt7623_ir_groups)},
4997 + {"lcd", mt7623_lcd_groups, ARRAY_SIZE(mt7623_lcd_groups)},
4998 + {"msdc", mt7623_msdc_groups, ARRAY_SIZE(mt7623_msdc_groups)},
4999 + {"nand", mt7623_nandc_groups, ARRAY_SIZE(mt7623_nandc_groups)},
5000 + {"otg", mt7623_otg_groups, ARRAY_SIZE(mt7623_otg_groups)},
5001 + {"pcie", mt7623_pcie_groups, ARRAY_SIZE(mt7623_pcie_groups)},
5002 + {"pcm", mt7623_pcm_groups, ARRAY_SIZE(mt7623_pcm_groups)},
5003 + {"pwm", mt7623_pwm_groups, ARRAY_SIZE(mt7623_pwm_groups)},
5004 + {"pwrap", mt7623_pwrap_groups, ARRAY_SIZE(mt7623_pwrap_groups)},
5005 + {"rtc", mt7623_rtc_groups, ARRAY_SIZE(mt7623_rtc_groups)},
5006 + {"spi", mt7623_spi_groups, ARRAY_SIZE(mt7623_spi_groups)},
5007 + {"spdif", mt7623_spdif_groups, ARRAY_SIZE(mt7623_spdif_groups)},
5008 + {"uart", mt7623_uart_groups, ARRAY_SIZE(mt7623_uart_groups)},
5009 + {"watchdog", mt7623_wdt_groups, ARRAY_SIZE(mt7623_wdt_groups)},
5010 +};
5011 +
5012 +static const struct mtk_eint_hw mt7623_eint_hw = {
5013 + .port_mask = 6,
5014 + .ports = 6,
5015 + .ap_num = 169,
5016 + .db_cnt = 20,
5017 +};
5018 +
5019 +static struct mtk_pin_soc mt7623_data = {
5020 + .reg_cal = mt7623_reg_cals,
5021 + .pins = mt7623_pins,
5022 + .npins = ARRAY_SIZE(mt7623_pins),
5023 + .grps = mt7623_groups,
5024 + .ngrps = ARRAY_SIZE(mt7623_groups),
5025 + .funcs = mt7623_functions,
5026 + .nfuncs = ARRAY_SIZE(mt7623_functions),
5027 + .eint_hw = &mt7623_eint_hw,
5028 + .gpio_m = 0,
5029 + .ies_present = true,
5030 + .base_names = mtk_default_register_base_names,
5031 + .nbase_names = ARRAY_SIZE(mtk_default_register_base_names),
5032 + .bias_disable_set = mtk_pinconf_bias_disable_set_rev1,
5033 + .bias_disable_get = mtk_pinconf_bias_disable_get_rev1,
5034 + .bias_set = mtk_pinconf_bias_set_rev1,
5035 + .bias_get = mtk_pinconf_bias_get_rev1,
5036 + .drive_set = mtk_pinconf_drive_set_rev1,
5037 + .drive_get = mtk_pinconf_drive_get_rev1,
5038 + .adv_pull_get = mtk_pinconf_adv_pull_get,
5039 + .adv_pull_set = mtk_pinconf_adv_pull_set,
5040 +};
5041 +
5042 +/*
5043 + * There are some specific pins have mux functions greater than 8,
5044 + * and if we want to switch thees high modes we need to disable
5045 + * bonding constraints firstly.
5046 + */
5047 +static void mt7623_bonding_disable(struct platform_device *pdev)
5048 +{
5049 + struct mtk_pinctrl *hw = platform_get_drvdata(pdev);
5050 +
5051 + mtk_rmw(hw, 0, PIN_BOND_REG0, BOND_PCIE_CLR, BOND_PCIE_CLR);
5052 + mtk_rmw(hw, 0, PIN_BOND_REG1, BOND_I2S_CLR, BOND_I2S_CLR);
5053 + mtk_rmw(hw, 0, PIN_BOND_REG2, BOND_MSDC0E_CLR, BOND_MSDC0E_CLR);
5054 +}
5055 +
5056 +static const struct of_device_id mt7623_pctrl_match[] = {
5057 + { .compatible = "mediatek,mt7623-moore-pinctrl", },
5058 + {}
5059 +};
5060 +
5061 +static int mt7623_pinctrl_probe(struct platform_device *pdev)
5062 +{
5063 + int err;
5064 +
5065 + err = mtk_moore_pinctrl_probe(pdev, &mt7623_data);
5066 + if (err)
5067 + return err;
5068 +
5069 + mt7623_bonding_disable(pdev);
5070 +
5071 + return 0;
5072 +}
5073 +
5074 +static struct platform_driver mtk_pinctrl_driver = {
5075 + .probe = mt7623_pinctrl_probe,
5076 + .driver = {
5077 + .name = "mt7623-moore-pinctrl",
5078 + .of_match_table = mt7623_pctrl_match,
5079 + },
5080 +};
5081 +
5082 +static int __init mtk_pinctrl_init(void)
5083 +{
5084 + return platform_driver_register(&mtk_pinctrl_driver);
5085 +}
5086 +arch_initcall(mtk_pinctrl_init);
5087 --- /dev/null
5088 +++ b/drivers/pinctrl/mediatek/pinctrl-mt7629.c
5089 @@ -0,0 +1,450 @@
5090 +// SPDX-License-Identifier: GPL-2.0
5091 +/*
5092 + * The MT7629 driver based on Linux generic pinctrl binding.
5093 + *
5094 + * Copyright (C) 2018 MediaTek Inc.
5095 + * Author: Ryder Lee <ryder.lee@mediatek.com>
5096 + */
5097 +
5098 +#include "pinctrl-moore.h"
5099 +
5100 +#define MT7629_PIN(_number, _name, _eint_n) \
5101 + MTK_PIN(_number, _name, 0, _eint_n, DRV_GRP1)
5102 +
5103 +static const struct mtk_pin_field_calc mt7629_pin_mode_range[] = {
5104 + PIN_FIELD(0, 78, 0x300, 0x10, 0, 4),
5105 +};
5106 +
5107 +static const struct mtk_pin_field_calc mt7629_pin_dir_range[] = {
5108 + PIN_FIELD(0, 78, 0x0, 0x10, 0, 1),
5109 +};
5110 +
5111 +static const struct mtk_pin_field_calc mt7629_pin_di_range[] = {
5112 + PIN_FIELD(0, 78, 0x200, 0x10, 0, 1),
5113 +};
5114 +
5115 +static const struct mtk_pin_field_calc mt7629_pin_do_range[] = {
5116 + PIN_FIELD(0, 78, 0x100, 0x10, 0, 1),
5117 +};
5118 +
5119 +static const struct mtk_pin_field_calc mt7629_pin_ies_range[] = {
5120 + PIN_FIELD(0, 10, 0x1000, 0x10, 0, 1),
5121 + PIN_FIELD(11, 18, 0x2000, 0x10, 0, 1),
5122 + PIN_FIELD(19, 32, 0x3000, 0x10, 0, 1),
5123 + PIN_FIELD(33, 48, 0x4000, 0x10, 0, 1),
5124 + PIN_FIELD(49, 50, 0x5000, 0x10, 0, 1),
5125 + PIN_FIELD(51, 69, 0x6000, 0x10, 0, 1),
5126 + PIN_FIELD(70, 78, 0x7000, 0x10, 0, 1),
5127 +};
5128 +
5129 +static const struct mtk_pin_field_calc mt7629_pin_smt_range[] = {
5130 + PIN_FIELD(0, 10, 0x1100, 0x10, 0, 1),
5131 + PIN_FIELD(11, 18, 0x2100, 0x10, 0, 1),
5132 + PIN_FIELD(19, 32, 0x3100, 0x10, 0, 1),
5133 + PIN_FIELD(33, 48, 0x4100, 0x10, 0, 1),
5134 + PIN_FIELD(49, 50, 0x5100, 0x10, 0, 1),
5135 + PIN_FIELD(51, 69, 0x6100, 0x10, 0, 1),
5136 + PIN_FIELD(70, 78, 0x7100, 0x10, 0, 1),
5137 +};
5138 +
5139 +static const struct mtk_pin_field_calc mt7629_pin_pullen_range[] = {
5140 + PIN_FIELD(0, 10, 0x1400, 0x10, 0, 1),
5141 + PIN_FIELD(11, 18, 0x2400, 0x10, 0, 1),
5142 + PIN_FIELD(19, 32, 0x3400, 0x10, 0, 1),
5143 + PIN_FIELD(33, 48, 0x4400, 0x10, 0, 1),
5144 + PIN_FIELD(49, 50, 0x5400, 0x10, 0, 1),
5145 + PIN_FIELD(51, 69, 0x6400, 0x10, 0, 1),
5146 + PIN_FIELD(70, 78, 0x7400, 0x10, 0, 1),
5147 +};
5148 +
5149 +static const struct mtk_pin_field_calc mt7629_pin_pullsel_range[] = {
5150 + PIN_FIELD(0, 10, 0x1500, 0x10, 0, 1),
5151 + PIN_FIELD(11, 18, 0x2500, 0x10, 0, 1),
5152 + PIN_FIELD(19, 32, 0x3500, 0x10, 0, 1),
5153 + PIN_FIELD(33, 48, 0x4500, 0x10, 0, 1),
5154 + PIN_FIELD(49, 50, 0x5500, 0x10, 0, 1),
5155 + PIN_FIELD(51, 69, 0x6500, 0x10, 0, 1),
5156 + PIN_FIELD(70, 78, 0x7500, 0x10, 0, 1),
5157 +};
5158 +
5159 +static const struct mtk_pin_field_calc mt7629_pin_drv_range[] = {
5160 + PIN_FIELD(0, 10, 0x1600, 0x10, 0, 4),
5161 + PIN_FIELD(11, 18, 0x2600, 0x10, 0, 4),
5162 + PIN_FIELD(19, 32, 0x3600, 0x10, 0, 4),
5163 + PIN_FIELD(33, 48, 0x4600, 0x10, 0, 4),
5164 + PIN_FIELD(49, 50, 0x5600, 0x10, 0, 4),
5165 + PIN_FIELD(51, 69, 0x6600, 0x10, 0, 4),
5166 + PIN_FIELD(70, 78, 0x7600, 0x10, 0, 4),
5167 +};
5168 +
5169 +static const struct mtk_pin_field_calc mt7629_pin_tdsel_range[] = {
5170 + PIN_FIELD(0, 10, 0x1200, 0x10, 0, 4),
5171 + PIN_FIELD(11, 18, 0x2200, 0x10, 0, 4),
5172 + PIN_FIELD(19, 32, 0x3200, 0x10, 0, 4),
5173 + PIN_FIELD(33, 48, 0x4200, 0x10, 0, 4),
5174 + PIN_FIELD(49, 50, 0x5200, 0x10, 0, 4),
5175 + PIN_FIELD(51, 69, 0x6200, 0x10, 0, 4),
5176 + PIN_FIELD(70, 78, 0x7200, 0x10, 0, 4),
5177 +};
5178 +
5179 +static const struct mtk_pin_field_calc mt7629_pin_rdsel_range[] = {
5180 + PIN_FIELD(0, 10, 0x1300, 0x10, 0, 4),
5181 + PIN_FIELD(11, 18, 0x2300, 0x10, 0, 4),
5182 + PIN_FIELD(19, 32, 0x3300, 0x10, 0, 4),
5183 + PIN_FIELD(33, 48, 0x4300, 0x10, 0, 4),
5184 + PIN_FIELD(49, 50, 0x5300, 0x10, 0, 4),
5185 + PIN_FIELD(51, 69, 0x6300, 0x10, 0, 4),
5186 + PIN_FIELD(70, 78, 0x7300, 0x10, 0, 4),
5187 +};
5188 +
5189 +static const struct mtk_pin_reg_calc mt7629_reg_cals[] = {
5190 + [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt7629_pin_mode_range),
5191 + [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt7629_pin_dir_range),
5192 + [PINCTRL_PIN_REG_DI] = MTK_RANGE(mt7629_pin_di_range),
5193 + [PINCTRL_PIN_REG_DO] = MTK_RANGE(mt7629_pin_do_range),
5194 + [PINCTRL_PIN_REG_IES] = MTK_RANGE(mt7629_pin_ies_range),
5195 + [PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt7629_pin_smt_range),
5196 + [PINCTRL_PIN_REG_PULLSEL] = MTK_RANGE(mt7629_pin_pullsel_range),
5197 + [PINCTRL_PIN_REG_PULLEN] = MTK_RANGE(mt7629_pin_pullen_range),
5198 + [PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt7629_pin_drv_range),
5199 + [PINCTRL_PIN_REG_TDSEL] = MTK_RANGE(mt7629_pin_tdsel_range),
5200 + [PINCTRL_PIN_REG_RDSEL] = MTK_RANGE(mt7629_pin_rdsel_range),
5201 +};
5202 +
5203 +static const struct mtk_pin_desc mt7629_pins[] = {
5204 + MT7629_PIN(0, "TOP_5G_CLK", 53),
5205 + MT7629_PIN(1, "TOP_5G_DATA", 54),
5206 + MT7629_PIN(2, "WF0_5G_HB0", 55),
5207 + MT7629_PIN(3, "WF0_5G_HB1", 56),
5208 + MT7629_PIN(4, "WF0_5G_HB2", 57),
5209 + MT7629_PIN(5, "WF0_5G_HB3", 58),
5210 + MT7629_PIN(6, "WF0_5G_HB4", 59),
5211 + MT7629_PIN(7, "WF0_5G_HB5", 60),
5212 + MT7629_PIN(8, "WF0_5G_HB6", 61),
5213 + MT7629_PIN(9, "XO_REQ", 9),
5214 + MT7629_PIN(10, "TOP_RST_N", 10),
5215 + MT7629_PIN(11, "SYS_WATCHDOG", 11),
5216 + MT7629_PIN(12, "EPHY_LED0_N_JTDO", 12),
5217 + MT7629_PIN(13, "EPHY_LED1_N_JTDI", 13),
5218 + MT7629_PIN(14, "EPHY_LED2_N_JTMS", 14),
5219 + MT7629_PIN(15, "EPHY_LED3_N_JTCLK", 15),
5220 + MT7629_PIN(16, "EPHY_LED4_N_JTRST_N", 16),
5221 + MT7629_PIN(17, "WF2G_LED_N", 17),
5222 + MT7629_PIN(18, "WF5G_LED_N", 18),
5223 + MT7629_PIN(19, "I2C_SDA", 19),
5224 + MT7629_PIN(20, "I2C_SCL", 20),
5225 + MT7629_PIN(21, "GPIO_9", 21),
5226 + MT7629_PIN(22, "GPIO_10", 22),
5227 + MT7629_PIN(23, "GPIO_11", 23),
5228 + MT7629_PIN(24, "GPIO_12", 24),
5229 + MT7629_PIN(25, "UART1_TXD", 25),
5230 + MT7629_PIN(26, "UART1_RXD", 26),
5231 + MT7629_PIN(27, "UART1_CTS", 27),
5232 + MT7629_PIN(28, "UART1_RTS", 28),
5233 + MT7629_PIN(29, "UART2_TXD", 29),
5234 + MT7629_PIN(30, "UART2_RXD", 30),
5235 + MT7629_PIN(31, "UART2_CTS", 31),
5236 + MT7629_PIN(32, "UART2_RTS", 32),
5237 + MT7629_PIN(33, "MDI_TP_P1", 33),
5238 + MT7629_PIN(34, "MDI_TN_P1", 34),
5239 + MT7629_PIN(35, "MDI_RP_P1", 35),
5240 + MT7629_PIN(36, "MDI_RN_P1", 36),
5241 + MT7629_PIN(37, "MDI_RP_P2", 37),
5242 + MT7629_PIN(38, "MDI_RN_P2", 38),
5243 + MT7629_PIN(39, "MDI_TP_P2", 39),
5244 + MT7629_PIN(40, "MDI_TN_P2", 40),
5245 + MT7629_PIN(41, "MDI_TP_P3", 41),
5246 + MT7629_PIN(42, "MDI_TN_P3", 42),
5247 + MT7629_PIN(43, "MDI_RP_P3", 43),
5248 + MT7629_PIN(44, "MDI_RN_P3", 44),
5249 + MT7629_PIN(45, "MDI_RP_P4", 45),
5250 + MT7629_PIN(46, "MDI_RN_P4", 46),
5251 + MT7629_PIN(47, "MDI_TP_P4", 47),
5252 + MT7629_PIN(48, "MDI_TN_P4", 48),
5253 + MT7629_PIN(49, "SMI_MDC", 49),
5254 + MT7629_PIN(50, "SMI_MDIO", 50),
5255 + MT7629_PIN(51, "PCIE_PERESET_N", 51),
5256 + MT7629_PIN(52, "PWM_0", 52),
5257 + MT7629_PIN(53, "GPIO_0", 0),
5258 + MT7629_PIN(54, "GPIO_1", 1),
5259 + MT7629_PIN(55, "GPIO_2", 2),
5260 + MT7629_PIN(56, "GPIO_3", 3),
5261 + MT7629_PIN(57, "GPIO_4", 4),
5262 + MT7629_PIN(58, "GPIO_5", 5),
5263 + MT7629_PIN(59, "GPIO_6", 6),
5264 + MT7629_PIN(60, "GPIO_7", 7),
5265 + MT7629_PIN(61, "GPIO_8", 8),
5266 + MT7629_PIN(62, "SPI_CLK", 62),
5267 + MT7629_PIN(63, "SPI_CS", 63),
5268 + MT7629_PIN(64, "SPI_MOSI", 64),
5269 + MT7629_PIN(65, "SPI_MISO", 65),
5270 + MT7629_PIN(66, "SPI_WP", 66),
5271 + MT7629_PIN(67, "SPI_HOLD", 67),
5272 + MT7629_PIN(68, "UART0_TXD", 68),
5273 + MT7629_PIN(69, "UART0_RXD", 69),
5274 + MT7629_PIN(70, "TOP_2G_CLK", 70),
5275 + MT7629_PIN(71, "TOP_2G_DATA", 71),
5276 + MT7629_PIN(72, "WF0_2G_HB0", 72),
5277 + MT7629_PIN(73, "WF0_2G_HB1", 73),
5278 + MT7629_PIN(74, "WF0_2G_HB2", 74),
5279 + MT7629_PIN(75, "WF0_2G_HB3", 75),
5280 + MT7629_PIN(76, "WF0_2G_HB4", 76),
5281 + MT7629_PIN(77, "WF0_2G_HB5", 77),
5282 + MT7629_PIN(78, "WF0_2G_HB6", 78),
5283 +};
5284 +
5285 +/* List all groups consisting of these pins dedicated to the enablement of
5286 + * certain hardware block and the corresponding mode for all of the pins.
5287 + * The hardware probably has multiple combinations of these pinouts.
5288 + */
5289 +
5290 +/* LED for EPHY */
5291 +static int mt7629_ephy_leds_pins[] = { 12, 13, 14, 15, 16, 17, 18, };
5292 +static int mt7629_ephy_leds_funcs[] = { 1, 1, 1, 1, 1, 1, 1, };
5293 +static int mt7629_ephy_led0_pins[] = { 12, };
5294 +static int mt7629_ephy_led0_funcs[] = { 1, };
5295 +static int mt7629_ephy_led1_pins[] = { 13, };
5296 +static int mt7629_ephy_led1_funcs[] = { 1, };
5297 +static int mt7629_ephy_led2_pins[] = { 14, };
5298 +static int mt7629_ephy_led2_funcs[] = { 1, };
5299 +static int mt7629_ephy_led3_pins[] = { 15, };
5300 +static int mt7629_ephy_led3_funcs[] = { 1, };
5301 +static int mt7629_ephy_led4_pins[] = { 16, };
5302 +static int mt7629_ephy_led4_funcs[] = { 1, };
5303 +static int mt7629_wf2g_led_pins[] = { 17, };
5304 +static int mt7629_wf2g_led_funcs[] = { 1, };
5305 +static int mt7629_wf5g_led_pins[] = { 18, };
5306 +static int mt7629_wf5g_led_funcs[] = { 1, };
5307 +
5308 +/* Watchdog */
5309 +static int mt7629_watchdog_pins[] = { 11, };
5310 +static int mt7629_watchdog_funcs[] = { 1, };
5311 +
5312 +/* LED for GPHY */
5313 +static int mt7629_gphy_leds_0_pins[] = { 21, 22, 23, };
5314 +static int mt7629_gphy_leds_0_funcs[] = { 2, 2, 2, };
5315 +static int mt7629_gphy_led1_0_pins[] = { 21, };
5316 +static int mt7629_gphy_led1_0_funcs[] = { 2, };
5317 +static int mt7629_gphy_led2_0_pins[] = { 22, };
5318 +static int mt7629_gphy_led2_0_funcs[] = { 2, };
5319 +static int mt7629_gphy_led3_0_pins[] = { 23, };
5320 +static int mt7629_gphy_led3_0_funcs[] = { 2, };
5321 +static int mt7629_gphy_leds_1_pins[] = { 57, 58, 59, };
5322 +static int mt7629_gphy_leds_1_funcs[] = { 1, 1, 1, };
5323 +static int mt7629_gphy_led1_1_pins[] = { 57, };
5324 +static int mt7629_gphy_led1_1_funcs[] = { 1, };
5325 +static int mt7629_gphy_led2_1_pins[] = { 58, };
5326 +static int mt7629_gphy_led2_1_funcs[] = { 1, };
5327 +static int mt7629_gphy_led3_1_pins[] = { 59, };
5328 +static int mt7629_gphy_led3_1_funcs[] = { 1, };
5329 +
5330 +/* I2C */
5331 +static int mt7629_i2c_0_pins[] = { 19, 20, };
5332 +static int mt7629_i2c_0_funcs[] = { 1, 1, };
5333 +static int mt7629_i2c_1_pins[] = { 53, 54, };
5334 +static int mt7629_i2c_1_funcs[] = { 1, 1, };
5335 +
5336 +/* SPI */
5337 +static int mt7629_spi_0_pins[] = { 21, 22, 23, 24, };
5338 +static int mt7629_spi_0_funcs[] = { 1, 1, 1, 1, };
5339 +static int mt7629_spi_1_pins[] = { 62, 63, 64, 65, };
5340 +static int mt7629_spi_1_funcs[] = { 1, 1, 1, 1, };
5341 +static int mt7629_spi_wp_pins[] = { 66, };
5342 +static int mt7629_spi_wp_funcs[] = { 1, };
5343 +static int mt7629_spi_hold_pins[] = { 67, };
5344 +static int mt7629_spi_hold_funcs[] = { 1, };
5345 +
5346 +/* UART */
5347 +static int mt7629_uart1_0_txd_rxd_pins[] = { 25, 26, };
5348 +static int mt7629_uart1_0_txd_rxd_funcs[] = { 1, 1, };
5349 +static int mt7629_uart1_1_txd_rxd_pins[] = { 53, 54, };
5350 +static int mt7629_uart1_1_txd_rxd_funcs[] = { 2, 2, };
5351 +static int mt7629_uart2_0_txd_rxd_pins[] = { 29, 30, };
5352 +static int mt7629_uart2_0_txd_rxd_funcs[] = { 1, 1, };
5353 +static int mt7629_uart2_1_txd_rxd_pins[] = { 57, 58, };
5354 +static int mt7629_uart2_1_txd_rxd_funcs[] = { 2, 2, };
5355 +static int mt7629_uart1_0_cts_rts_pins[] = { 27, 28, };
5356 +static int mt7629_uart1_0_cts_rts_funcs[] = { 1, 1, };
5357 +static int mt7629_uart1_1_cts_rts_pins[] = { 55, 56, };
5358 +static int mt7629_uart1_1_cts_rts_funcs[] = { 2, 2, };
5359 +static int mt7629_uart2_0_cts_rts_pins[] = { 31, 32, };
5360 +static int mt7629_uart2_0_cts_rts_funcs[] = { 1, 1, };
5361 +static int mt7629_uart2_1_cts_rts_pins[] = { 59, 60, };
5362 +static int mt7629_uart2_1_cts_rts_funcs[] = { 2, 2, };
5363 +static int mt7629_uart0_txd_rxd_pins[] = { 68, 69, };
5364 +static int mt7629_uart0_txd_rxd_funcs[] = { 1, 1, };
5365 +
5366 +/* MDC/MDIO */
5367 +static int mt7629_mdc_mdio_pins[] = { 49, 50, };
5368 +static int mt7629_mdc_mdio_funcs[] = { 1, 1, };
5369 +
5370 +/* PCIE */
5371 +static int mt7629_pcie_pereset_pins[] = { 51, };
5372 +static int mt7629_pcie_pereset_funcs[] = { 1, };
5373 +static int mt7629_pcie_wake_pins[] = { 55, };
5374 +static int mt7629_pcie_wake_funcs[] = { 1, };
5375 +static int mt7629_pcie_clkreq_pins[] = { 56, };
5376 +static int mt7629_pcie_clkreq_funcs[] = { 1, };
5377 +
5378 +/* PWM */
5379 +static int mt7629_pwm_0_pins[] = { 52, };
5380 +static int mt7629_pwm_0_funcs[] = { 1, };
5381 +static int mt7629_pwm_1_pins[] = { 61, };
5382 +static int mt7629_pwm_1_funcs[] = { 2, };
5383 +
5384 +/* WF 2G */
5385 +static int mt7629_wf0_2g_pins[] = { 70, 71, 72, 73, 74, 75, 76, 77, 78, };
5386 +static int mt7629_wf0_2g_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, };
5387 +
5388 +/* WF 5G */
5389 +static int mt7629_wf0_5g_pins[] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, };
5390 +static int mt7629_wf0_5g_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
5391 +
5392 +/* SNFI */
5393 +static int mt7629_snfi_pins[] = { 62, 63, 64, 65, 66, 67 };
5394 +static int mt7629_snfi_funcs[] = { 2, 2, 2, 2, 2, 2 };
5395 +
5396 +/* SPI NOR */
5397 +static int mt7629_snor_pins[] = { 62, 63, 64, 65, 66, 67 };
5398 +static int mt7629_snor_funcs[] = { 1, 1, 1, 1, 1, 1 };
5399 +
5400 +static const struct group_desc mt7629_groups[] = {
5401 + PINCTRL_PIN_GROUP("ephy_leds", mt7629_ephy_leds),
5402 + PINCTRL_PIN_GROUP("ephy_led0", mt7629_ephy_led0),
5403 + PINCTRL_PIN_GROUP("ephy_led1", mt7629_ephy_led1),
5404 + PINCTRL_PIN_GROUP("ephy_led2", mt7629_ephy_led2),
5405 + PINCTRL_PIN_GROUP("ephy_led3", mt7629_ephy_led3),
5406 + PINCTRL_PIN_GROUP("ephy_led4", mt7629_ephy_led4),
5407 + PINCTRL_PIN_GROUP("wf2g_led", mt7629_wf2g_led),
5408 + PINCTRL_PIN_GROUP("wf5g_led", mt7629_wf5g_led),
5409 + PINCTRL_PIN_GROUP("watchdog", mt7629_watchdog),
5410 + PINCTRL_PIN_GROUP("gphy_leds_0", mt7629_gphy_leds_0),
5411 + PINCTRL_PIN_GROUP("gphy_led1_0", mt7629_gphy_led1_0),
5412 + PINCTRL_PIN_GROUP("gphy_led2_0", mt7629_gphy_led2_0),
5413 + PINCTRL_PIN_GROUP("gphy_led3_0", mt7629_gphy_led3_0),
5414 + PINCTRL_PIN_GROUP("gphy_leds_1", mt7629_gphy_leds_1),
5415 + PINCTRL_PIN_GROUP("gphy_led1_1", mt7629_gphy_led1_1),
5416 + PINCTRL_PIN_GROUP("gphy_led2_1", mt7629_gphy_led2_1),
5417 + PINCTRL_PIN_GROUP("gphy_led3_1", mt7629_gphy_led3_1),
5418 + PINCTRL_PIN_GROUP("i2c_0", mt7629_i2c_0),
5419 + PINCTRL_PIN_GROUP("i2c_1", mt7629_i2c_1),
5420 + PINCTRL_PIN_GROUP("spi_0", mt7629_spi_0),
5421 + PINCTRL_PIN_GROUP("spi_1", mt7629_spi_1),
5422 + PINCTRL_PIN_GROUP("spi_wp", mt7629_spi_wp),
5423 + PINCTRL_PIN_GROUP("spi_hold", mt7629_spi_hold),
5424 + PINCTRL_PIN_GROUP("uart1_0_txd_rxd", mt7629_uart1_0_txd_rxd),
5425 + PINCTRL_PIN_GROUP("uart1_1_txd_rxd", mt7629_uart1_1_txd_rxd),
5426 + PINCTRL_PIN_GROUP("uart2_0_txd_rxd", mt7629_uart2_0_txd_rxd),
5427 + PINCTRL_PIN_GROUP("uart2_1_txd_rxd", mt7629_uart2_1_txd_rxd),
5428 + PINCTRL_PIN_GROUP("uart1_0_cts_rts", mt7629_uart1_0_cts_rts),
5429 + PINCTRL_PIN_GROUP("uart1_1_cts_rts", mt7629_uart1_1_cts_rts),
5430 + PINCTRL_PIN_GROUP("uart2_0_cts_rts", mt7629_uart2_0_cts_rts),
5431 + PINCTRL_PIN_GROUP("uart2_1_cts_rts", mt7629_uart2_1_cts_rts),
5432 + PINCTRL_PIN_GROUP("uart0_txd_rxd", mt7629_uart0_txd_rxd),
5433 + PINCTRL_PIN_GROUP("mdc_mdio", mt7629_mdc_mdio),
5434 + PINCTRL_PIN_GROUP("pcie_pereset", mt7629_pcie_pereset),
5435 + PINCTRL_PIN_GROUP("pcie_wake", mt7629_pcie_wake),
5436 + PINCTRL_PIN_GROUP("pcie_clkreq", mt7629_pcie_clkreq),
5437 + PINCTRL_PIN_GROUP("pwm_0", mt7629_pwm_0),
5438 + PINCTRL_PIN_GROUP("pwm_1", mt7629_pwm_1),
5439 + PINCTRL_PIN_GROUP("wf0_5g", mt7629_wf0_5g),
5440 + PINCTRL_PIN_GROUP("wf0_2g", mt7629_wf0_2g),
5441 + PINCTRL_PIN_GROUP("snfi", mt7629_snfi),
5442 + PINCTRL_PIN_GROUP("spi_nor", mt7629_snor),
5443 +};
5444 +
5445 +/* Joint those groups owning the same capability in user point of view which
5446 + * allows that people tend to use through the device tree.
5447 + */
5448 +static const char *mt7629_ethernet_groups[] = { "mdc_mdio", };
5449 +static const char *mt7629_i2c_groups[] = { "i2c_0", "i2c_1", };
5450 +static const char *mt7629_led_groups[] = { "ephy_leds", "ephy_led0",
5451 + "ephy_led1", "ephy_led2",
5452 + "ephy_led3", "ephy_led4",
5453 + "wf2g_led", "wf5g_led",
5454 + "gphy_leds_0", "gphy_led1_0",
5455 + "gphy_led2_0", "gphy_led3_0",
5456 + "gphy_leds_1", "gphy_led1_1",
5457 + "gphy_led2_1", "gphy_led3_1",};
5458 +static const char *mt7629_pcie_groups[] = { "pcie_pereset", "pcie_wake",
5459 + "pcie_clkreq", };
5460 +static const char *mt7629_pwm_groups[] = { "pwm_0", "pwm_1", };
5461 +static const char *mt7629_spi_groups[] = { "spi_0", "spi_1", "spi_wp",
5462 + "spi_hold", };
5463 +static const char *mt7629_uart_groups[] = { "uart1_0_txd_rxd",
5464 + "uart1_1_txd_rxd",
5465 + "uart2_0_txd_rxd",
5466 + "uart2_1_txd_rxd",
5467 + "uart1_0_cts_rts",
5468 + "uart1_1_cts_rts",
5469 + "uart2_0_cts_rts",
5470 + "uart2_1_cts_rts",
5471 + "uart0_txd_rxd", };
5472 +static const char *mt7629_wdt_groups[] = { "watchdog", };
5473 +static const char *mt7629_wifi_groups[] = { "wf0_5g", "wf0_2g", };
5474 +static const char *mt7629_flash_groups[] = { "snfi", "spi_nor" };
5475 +
5476 +static const struct function_desc mt7629_functions[] = {
5477 + {"eth", mt7629_ethernet_groups, ARRAY_SIZE(mt7629_ethernet_groups)},
5478 + {"i2c", mt7629_i2c_groups, ARRAY_SIZE(mt7629_i2c_groups)},
5479 + {"led", mt7629_led_groups, ARRAY_SIZE(mt7629_led_groups)},
5480 + {"pcie", mt7629_pcie_groups, ARRAY_SIZE(mt7629_pcie_groups)},
5481 + {"pwm", mt7629_pwm_groups, ARRAY_SIZE(mt7629_pwm_groups)},
5482 + {"spi", mt7629_spi_groups, ARRAY_SIZE(mt7629_spi_groups)},
5483 + {"uart", mt7629_uart_groups, ARRAY_SIZE(mt7629_uart_groups)},
5484 + {"watchdog", mt7629_wdt_groups, ARRAY_SIZE(mt7629_wdt_groups)},
5485 + {"wifi", mt7629_wifi_groups, ARRAY_SIZE(mt7629_wifi_groups)},
5486 + {"flash", mt7629_flash_groups, ARRAY_SIZE(mt7629_flash_groups)},
5487 +};
5488 +
5489 +static const struct mtk_eint_hw mt7629_eint_hw = {
5490 + .port_mask = 7,
5491 + .ports = 7,
5492 + .ap_num = ARRAY_SIZE(mt7629_pins),
5493 + .db_cnt = 16,
5494 +};
5495 +
5496 +static struct mtk_pin_soc mt7629_data = {
5497 + .reg_cal = mt7629_reg_cals,
5498 + .pins = mt7629_pins,
5499 + .npins = ARRAY_SIZE(mt7629_pins),
5500 + .grps = mt7629_groups,
5501 + .ngrps = ARRAY_SIZE(mt7629_groups),
5502 + .funcs = mt7629_functions,
5503 + .nfuncs = ARRAY_SIZE(mt7629_functions),
5504 + .eint_hw = &mt7629_eint_hw,
5505 + .gpio_m = 0,
5506 + .ies_present = true,
5507 + .base_names = mtk_default_register_base_names,
5508 + .nbase_names = ARRAY_SIZE(mtk_default_register_base_names),
5509 + .bias_disable_set = mtk_pinconf_bias_disable_set_rev1,
5510 + .bias_disable_get = mtk_pinconf_bias_disable_get_rev1,
5511 + .bias_set = mtk_pinconf_bias_set_rev1,
5512 + .bias_get = mtk_pinconf_bias_get_rev1,
5513 + .drive_set = mtk_pinconf_drive_set_rev1,
5514 + .drive_get = mtk_pinconf_drive_get_rev1,
5515 +};
5516 +
5517 +static const struct of_device_id mt7629_pinctrl_of_match[] = {
5518 + { .compatible = "mediatek,mt7629-pinctrl", },
5519 + {}
5520 +};
5521 +
5522 +static int mt7629_pinctrl_probe(struct platform_device *pdev)
5523 +{
5524 + return mtk_moore_pinctrl_probe(pdev, &mt7629_data);
5525 +}
5526 +
5527 +static struct platform_driver mt7629_pinctrl_driver = {
5528 + .driver = {
5529 + .name = "mt7629-pinctrl",
5530 + .of_match_table = mt7629_pinctrl_of_match,
5531 + },
5532 + .probe = mt7629_pinctrl_probe,
5533 +};
5534 +
5535 +static int __init mt7629_pinctrl_init(void)
5536 +{
5537 + return platform_driver_register(&mt7629_pinctrl_driver);
5538 +}
5539 +arch_initcall(mt7629_pinctrl_init);
5540 --- /dev/null
5541 +++ b/drivers/pinctrl/mediatek/pinctrl-mt8183.c
5542 @@ -0,0 +1,595 @@
5543 +// SPDX-License-Identifier: GPL-2.0
5544 +/*
5545 + * Copyright (C) 2018 MediaTek Inc.
5546 + *
5547 + * Author: Zhiyong Tao <zhiyong.tao@mediatek.com>
5548 + *
5549 + */
5550 +
5551 +#include "pinctrl-mtk-mt8183.h"
5552 +#include "pinctrl-paris.h"
5553 +
5554 +/* MT8183 have multiple bases to program pin configuration listed as the below:
5555 + * iocfg[0]:0x10005000, iocfg[1]:0x11F20000, iocfg[2]:0x11E80000,
5556 + * iocfg[3]:0x11E70000, iocfg[4]:0x11E90000, iocfg[5]:0x11D30000,
5557 + * iocfg[6]:0x11D20000, iocfg[7]:0x11C50000, iocfg[8]:0x11F30000.
5558 + * _i_based could be used to indicate what base the pin should be mapped into.
5559 + */
5560 +
5561 +#define PIN_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, _x_bits) \
5562 + PIN_FIELD_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \
5563 + _x_bits, 32, 0)
5564 +
5565 +#define PINS_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, _x_bits) \
5566 + PIN_FIELD_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \
5567 + _x_bits, 32, 1)
5568 +
5569 +static const struct mtk_pin_field_calc mt8183_pin_mode_range[] = {
5570 + PIN_FIELD(0, 192, 0x300, 0x10, 0, 4),
5571 +};
5572 +
5573 +static const struct mtk_pin_field_calc mt8183_pin_dir_range[] = {
5574 + PIN_FIELD(0, 192, 0x0, 0x10, 0, 1),
5575 +};
5576 +
5577 +static const struct mtk_pin_field_calc mt8183_pin_di_range[] = {
5578 + PIN_FIELD(0, 192, 0x200, 0x10, 0, 1),
5579 +};
5580 +
5581 +static const struct mtk_pin_field_calc mt8183_pin_do_range[] = {
5582 + PIN_FIELD(0, 192, 0x100, 0x10, 0, 1),
5583 +};
5584 +
5585 +static const struct mtk_pin_field_calc mt8183_pin_ies_range[] = {
5586 + PINS_FIELD_BASE(0, 3, 6, 0x000, 0x10, 3, 1),
5587 + PINS_FIELD_BASE(4, 7, 6, 0x000, 0x10, 5, 1),
5588 + PIN_FIELD_BASE(8, 8, 6, 0x000, 0x10, 0, 1),
5589 + PINS_FIELD_BASE(9, 10, 6, 0x000, 0x10, 12, 1),
5590 + PIN_FIELD_BASE(11, 11, 1, 0x000, 0x10, 3, 1),
5591 + PIN_FIELD_BASE(12, 12, 1, 0x000, 0x10, 7, 1),
5592 + PINS_FIELD_BASE(13, 16, 2, 0x000, 0x10, 2, 1),
5593 + PINS_FIELD_BASE(17, 20, 2, 0x000, 0x10, 3, 1),
5594 + PINS_FIELD_BASE(21, 24, 2, 0x000, 0x10, 4, 1),
5595 + PINS_FIELD_BASE(25, 28, 2, 0x000, 0x10, 5, 1),
5596 + PIN_FIELD_BASE(29, 29, 2, 0x000, 0x10, 6, 1),
5597 + PIN_FIELD_BASE(30, 30, 2, 0x000, 0x10, 7, 1),
5598 + PINS_FIELD_BASE(31, 31, 2, 0x000, 0x10, 8, 1),
5599 + PINS_FIELD_BASE(32, 34, 2, 0x000, 0x10, 7, 1),
5600 + PINS_FIELD_BASE(35, 37, 3, 0x000, 0x10, 0, 1),
5601 + PINS_FIELD_BASE(38, 40, 3, 0x000, 0x10, 1, 1),
5602 + PINS_FIELD_BASE(41, 42, 3, 0x000, 0x10, 2, 1),
5603 + PINS_FIELD_BASE(43, 45, 3, 0x000, 0x10, 3, 1),
5604 + PINS_FIELD_BASE(46, 47, 3, 0x000, 0x10, 4, 1),
5605 + PINS_FIELD_BASE(48, 49, 3, 0x000, 0x10, 5, 1),
5606 + PINS_FIELD_BASE(50, 51, 4, 0x000, 0x10, 0, 1),
5607 + PINS_FIELD_BASE(52, 57, 4, 0x000, 0x10, 1, 1),
5608 + PINS_FIELD_BASE(58, 60, 4, 0x000, 0x10, 2, 1),
5609 + PINS_FIELD_BASE(61, 64, 5, 0x000, 0x10, 0, 1),
5610 + PINS_FIELD_BASE(65, 66, 5, 0x000, 0x10, 1, 1),
5611 + PINS_FIELD_BASE(67, 68, 5, 0x000, 0x10, 2, 1),
5612 + PINS_FIELD_BASE(69, 71, 5, 0x000, 0x10, 3, 1),
5613 + PINS_FIELD_BASE(72, 76, 5, 0x000, 0x10, 4, 1),
5614 + PINS_FIELD_BASE(77, 80, 5, 0x000, 0x10, 5, 1),
5615 + PIN_FIELD_BASE(81, 81, 5, 0x000, 0x10, 6, 1),
5616 + PINS_FIELD_BASE(82, 83, 5, 0x000, 0x10, 7, 1),
5617 + PIN_FIELD_BASE(84, 84, 5, 0x000, 0x10, 6, 1),
5618 + PINS_FIELD_BASE(85, 88, 5, 0x000, 0x10, 8, 1),
5619 + PIN_FIELD_BASE(89, 89, 6, 0x000, 0x10, 11, 1),
5620 + PIN_FIELD_BASE(90, 90, 6, 0x000, 0x10, 1, 1),
5621 + PINS_FIELD_BASE(91, 94, 6, 0x000, 0x10, 2, 1),
5622 + PINS_FIELD_BASE(95, 96, 6, 0x000, 0x10, 6, 1),
5623 + PINS_FIELD_BASE(97, 98, 6, 0x000, 0x10, 7, 1),
5624 + PIN_FIELD_BASE(99, 99, 6, 0x000, 0x10, 8, 1),
5625 + PIN_FIELD_BASE(100, 100, 6, 0x000, 0x10, 9, 1),
5626 + PINS_FIELD_BASE(101, 102, 6, 0x000, 0x10, 10, 1),
5627 + PINS_FIELD_BASE(103, 104, 6, 0x000, 0x10, 13, 1),
5628 + PINS_FIELD_BASE(105, 106, 6, 0x000, 0x10, 14, 1),
5629 + PIN_FIELD_BASE(107, 107, 7, 0x000, 0x10, 0, 1),
5630 + PIN_FIELD_BASE(108, 108, 7, 0x000, 0x10, 1, 1),
5631 + PIN_FIELD_BASE(109, 109, 7, 0x000, 0x10, 2, 1),
5632 + PIN_FIELD_BASE(110, 110, 7, 0x000, 0x10, 0, 1),
5633 + PIN_FIELD_BASE(111, 111, 7, 0x000, 0x10, 3, 1),
5634 + PIN_FIELD_BASE(112, 112, 7, 0x000, 0x10, 2, 1),
5635 + PIN_FIELD_BASE(113, 113, 7, 0x000, 0x10, 4, 1),
5636 + PIN_FIELD_BASE(114, 114, 7, 0x000, 0x10, 5, 1),
5637 + PIN_FIELD_BASE(115, 115, 7, 0x000, 0x10, 6, 1),
5638 + PIN_FIELD_BASE(116, 116, 7, 0x000, 0x10, 7, 1),
5639 + PIN_FIELD_BASE(117, 117, 7, 0x000, 0x10, 8, 1),
5640 + PIN_FIELD_BASE(118, 118, 7, 0x000, 0x10, 9, 1),
5641 + PIN_FIELD_BASE(119, 119, 7, 0x000, 0x10, 10, 1),
5642 + PIN_FIELD_BASE(120, 120, 7, 0x000, 0x10, 11, 1),
5643 + PIN_FIELD_BASE(121, 121, 7, 0x000, 0x10, 12, 1),
5644 + PIN_FIELD_BASE(122, 122, 8, 0x000, 0x10, 0, 1),
5645 + PIN_FIELD_BASE(123, 123, 8, 0x000, 0x10, 1, 1),
5646 + PIN_FIELD_BASE(124, 124, 8, 0x000, 0x10, 2, 1),
5647 + PINS_FIELD_BASE(125, 130, 8, 0x000, 0x10, 1, 1),
5648 + PIN_FIELD_BASE(131, 131, 8, 0x000, 0x10, 3, 1),
5649 + PIN_FIELD_BASE(132, 132, 8, 0x000, 0x10, 1, 1),
5650 + PIN_FIELD_BASE(133, 133, 8, 0x000, 0x10, 4, 1),
5651 + PIN_FIELD_BASE(134, 134, 1, 0x000, 0x10, 0, 1),
5652 + PIN_FIELD_BASE(135, 135, 1, 0x000, 0x10, 1, 1),
5653 + PINS_FIELD_BASE(136, 143, 1, 0x000, 0x10, 2, 1),
5654 + PINS_FIELD_BASE(144, 147, 1, 0x000, 0x10, 4, 1),
5655 + PIN_FIELD_BASE(148, 148, 1, 0x000, 0x10, 5, 1),
5656 + PIN_FIELD_BASE(149, 149, 1, 0x000, 0x10, 6, 1),
5657 + PINS_FIELD_BASE(150, 153, 1, 0x000, 0x10, 8, 1),
5658 + PIN_FIELD_BASE(154, 154, 1, 0x000, 0x10, 9, 1),
5659 + PINS_FIELD_BASE(155, 157, 1, 0x000, 0x10, 10, 1),
5660 + PINS_FIELD_BASE(158, 160, 1, 0x000, 0x10, 8, 1),
5661 + PINS_FIELD_BASE(161, 164, 2, 0x000, 0x10, 0, 1),
5662 + PINS_FIELD_BASE(165, 166, 2, 0x000, 0x10, 1, 1),
5663 + PINS_FIELD_BASE(167, 168, 4, 0x000, 0x10, 2, 1),
5664 + PIN_FIELD_BASE(169, 169, 4, 0x000, 0x10, 3, 1),
5665 + PINS_FIELD_BASE(170, 174, 4, 0x000, 0x10, 4, 1),
5666 + PINS_FIELD_BASE(175, 176, 4, 0x000, 0x10, 3, 1),
5667 + PINS_FIELD_BASE(177, 179, 6, 0x000, 0x10, 4, 1),
5668 +};
5669 +
5670 +static const struct mtk_pin_field_calc mt8183_pin_smt_range[] = {
5671 + PINS_FIELD_BASE(0, 3, 6, 0x010, 0x10, 3, 1),
5672 + PINS_FIELD_BASE(4, 7, 6, 0x010, 0x10, 5, 1),
5673 + PIN_FIELD_BASE(8, 8, 6, 0x010, 0x10, 0, 1),
5674 + PINS_FIELD_BASE(9, 10, 6, 0x010, 0x10, 12, 1),
5675 + PIN_FIELD_BASE(11, 11, 1, 0x010, 0x10, 3, 1),
5676 + PIN_FIELD_BASE(12, 12, 1, 0x010, 0x10, 7, 1),
5677 + PINS_FIELD_BASE(13, 16, 2, 0x010, 0x10, 2, 1),
5678 + PINS_FIELD_BASE(17, 20, 2, 0x010, 0x10, 3, 1),
5679 + PINS_FIELD_BASE(21, 24, 2, 0x010, 0x10, 4, 1),
5680 + PINS_FIELD_BASE(25, 28, 2, 0x010, 0x10, 5, 1),
5681 + PIN_FIELD_BASE(29, 29, 2, 0x010, 0x10, 6, 1),
5682 + PIN_FIELD_BASE(30, 30, 2, 0x010, 0x10, 7, 1),
5683 + PINS_FIELD_BASE(31, 31, 2, 0x010, 0x10, 8, 1),
5684 + PINS_FIELD_BASE(32, 34, 2, 0x010, 0x10, 7, 1),
5685 + PINS_FIELD_BASE(35, 37, 3, 0x010, 0x10, 0, 1),
5686 + PINS_FIELD_BASE(38, 40, 3, 0x010, 0x10, 1, 1),
5687 + PINS_FIELD_BASE(41, 42, 3, 0x010, 0x10, 2, 1),
5688 + PINS_FIELD_BASE(43, 45, 3, 0x010, 0x10, 3, 1),
5689 + PINS_FIELD_BASE(46, 47, 3, 0x010, 0x10, 4, 1),
5690 + PINS_FIELD_BASE(48, 49, 3, 0x010, 0x10, 5, 1),
5691 + PINS_FIELD_BASE(50, 51, 4, 0x010, 0x10, 0, 1),
5692 + PINS_FIELD_BASE(52, 57, 4, 0x010, 0x10, 1, 1),
5693 + PINS_FIELD_BASE(58, 60, 4, 0x010, 0x10, 2, 1),
5694 + PINS_FIELD_BASE(61, 64, 5, 0x010, 0x10, 0, 1),
5695 + PINS_FIELD_BASE(65, 66, 5, 0x010, 0x10, 1, 1),
5696 + PINS_FIELD_BASE(67, 68, 5, 0x010, 0x10, 2, 1),
5697 + PINS_FIELD_BASE(69, 71, 5, 0x010, 0x10, 3, 1),
5698 + PINS_FIELD_BASE(72, 76, 5, 0x010, 0x10, 4, 1),
5699 + PINS_FIELD_BASE(77, 80, 5, 0x010, 0x10, 5, 1),
5700 + PIN_FIELD_BASE(81, 81, 5, 0x010, 0x10, 6, 1),
5701 + PINS_FIELD_BASE(82, 83, 5, 0x010, 0x10, 7, 1),
5702 + PIN_FIELD_BASE(84, 84, 5, 0x010, 0x10, 6, 1),
5703 + PINS_FIELD_BASE(85, 88, 5, 0x010, 0x10, 8, 1),
5704 + PIN_FIELD_BASE(89, 89, 6, 0x010, 0x10, 11, 1),
5705 + PIN_FIELD_BASE(90, 90, 6, 0x010, 0x10, 1, 1),
5706 + PINS_FIELD_BASE(91, 94, 6, 0x010, 0x10, 2, 1),
5707 + PINS_FIELD_BASE(95, 96, 6, 0x010, 0x10, 6, 1),
5708 + PINS_FIELD_BASE(97, 98, 6, 0x010, 0x10, 7, 1),
5709 + PIN_FIELD_BASE(99, 99, 6, 0x010, 0x10, 8, 1),
5710 + PIN_FIELD_BASE(100, 100, 6, 0x010, 0x10, 9, 1),
5711 + PINS_FIELD_BASE(101, 102, 6, 0x010, 0x10, 10, 1),
5712 + PINS_FIELD_BASE(103, 104, 6, 0x010, 0x10, 13, 1),
5713 + PINS_FIELD_BASE(105, 106, 6, 0x010, 0x10, 14, 1),
5714 + PIN_FIELD_BASE(107, 107, 7, 0x010, 0x10, 0, 1),
5715 + PIN_FIELD_BASE(108, 108, 7, 0x010, 0x10, 1, 1),
5716 + PIN_FIELD_BASE(109, 109, 7, 0x010, 0x10, 2, 1),
5717 + PIN_FIELD_BASE(110, 110, 7, 0x010, 0x10, 0, 1),
5718 + PIN_FIELD_BASE(111, 111, 7, 0x010, 0x10, 3, 1),
5719 + PIN_FIELD_BASE(112, 112, 7, 0x010, 0x10, 2, 1),
5720 + PIN_FIELD_BASE(113, 113, 7, 0x010, 0x10, 4, 1),
5721 + PIN_FIELD_BASE(114, 114, 7, 0x010, 0x10, 5, 1),
5722 + PIN_FIELD_BASE(115, 115, 7, 0x010, 0x10, 6, 1),
5723 + PIN_FIELD_BASE(116, 116, 7, 0x010, 0x10, 7, 1),
5724 + PIN_FIELD_BASE(117, 117, 7, 0x010, 0x10, 8, 1),
5725 + PIN_FIELD_BASE(118, 118, 7, 0x010, 0x10, 9, 1),
5726 + PIN_FIELD_BASE(119, 119, 7, 0x010, 0x10, 10, 1),
5727 + PIN_FIELD_BASE(120, 120, 7, 0x010, 0x10, 11, 1),
5728 + PIN_FIELD_BASE(121, 121, 7, 0x010, 0x10, 12, 1),
5729 + PIN_FIELD_BASE(122, 122, 8, 0x010, 0x10, 0, 1),
5730 + PIN_FIELD_BASE(123, 123, 8, 0x010, 0x10, 1, 1),
5731 + PIN_FIELD_BASE(124, 124, 8, 0x010, 0x10, 2, 1),
5732 + PINS_FIELD_BASE(125, 130, 8, 0x010, 0x10, 1, 1),
5733 + PIN_FIELD_BASE(131, 131, 8, 0x010, 0x10, 3, 1),
5734 + PIN_FIELD_BASE(132, 132, 8, 0x010, 0x10, 1, 1),
5735 + PIN_FIELD_BASE(133, 133, 8, 0x010, 0x10, 4, 1),
5736 + PIN_FIELD_BASE(134, 134, 1, 0x010, 0x10, 0, 1),
5737 + PIN_FIELD_BASE(135, 135, 1, 0x010, 0x10, 1, 1),
5738 + PINS_FIELD_BASE(136, 143, 1, 0x010, 0x10, 2, 1),
5739 + PINS_FIELD_BASE(144, 147, 1, 0x010, 0x10, 4, 1),
5740 + PIN_FIELD_BASE(148, 148, 1, 0x010, 0x10, 5, 1),
5741 + PIN_FIELD_BASE(149, 149, 1, 0x010, 0x10, 6, 1),
5742 + PINS_FIELD_BASE(150, 153, 1, 0x010, 0x10, 8, 1),
5743 + PIN_FIELD_BASE(154, 154, 1, 0x010, 0x10, 9, 1),
5744 + PINS_FIELD_BASE(155, 157, 1, 0x010, 0x10, 10, 1),
5745 + PINS_FIELD_BASE(158, 160, 1, 0x010, 0x10, 8, 1),
5746 + PINS_FIELD_BASE(161, 164, 2, 0x010, 0x10, 0, 1),
5747 + PINS_FIELD_BASE(165, 166, 2, 0x010, 0x10, 1, 1),
5748 + PINS_FIELD_BASE(167, 168, 4, 0x010, 0x10, 2, 1),
5749 + PIN_FIELD_BASE(169, 169, 4, 0x010, 0x10, 3, 1),
5750 + PINS_FIELD_BASE(170, 174, 4, 0x010, 0x10, 4, 1),
5751 + PINS_FIELD_BASE(175, 176, 4, 0x010, 0x10, 3, 1),
5752 + PINS_FIELD_BASE(177, 179, 6, 0x010, 0x10, 4, 1),
5753 +};
5754 +
5755 +static const struct mtk_pin_field_calc mt8183_pin_pullen_range[] = {
5756 + PIN_FIELD_BASE(0, 3, 6, 0x060, 0x10, 6, 1),
5757 + PIN_FIELD_BASE(4, 7, 6, 0x060, 0x10, 11, 1),
5758 + PIN_FIELD_BASE(8, 8, 6, 0x060, 0x10, 0, 1),
5759 + PIN_FIELD_BASE(9, 10, 6, 0x060, 0x10, 26, 1),
5760 + PIN_FIELD_BASE(11, 11, 1, 0x060, 0x10, 10, 1),
5761 + PIN_FIELD_BASE(12, 12, 1, 0x060, 0x10, 17, 1),
5762 + PIN_FIELD_BASE(13, 28, 2, 0x060, 0x10, 6, 1),
5763 + PIN_FIELD_BASE(43, 49, 3, 0x060, 0x10, 8, 1),
5764 + PIN_FIELD_BASE(50, 60, 4, 0x060, 0x10, 0, 1),
5765 + PIN_FIELD_BASE(61, 88, 5, 0x060, 0x10, 0, 1),
5766 + PIN_FIELD_BASE(89, 89, 6, 0x060, 0x10, 24, 1),
5767 + PIN_FIELD_BASE(90, 90, 6, 0x060, 0x10, 1, 1),
5768 + PIN_FIELD_BASE(95, 95, 6, 0x060, 0x10, 15, 1),
5769 + PIN_FIELD_BASE(96, 102, 6, 0x060, 0x10, 17, 1),
5770 + PIN_FIELD_BASE(103, 106, 6, 0x060, 0x10, 28, 1),
5771 + PIN_FIELD_BASE(107, 121, 7, 0x060, 0x10, 0, 1),
5772 + PIN_FIELD_BASE(134, 143, 1, 0x060, 0x10, 0, 1),
5773 + PIN_FIELD_BASE(144, 149, 1, 0x060, 0x10, 11, 1),
5774 + PIN_FIELD_BASE(150, 160, 1, 0x060, 0x10, 18, 1),
5775 + PIN_FIELD_BASE(161, 166, 2, 0x060, 0x10, 0, 1),
5776 + PIN_FIELD_BASE(167, 176, 4, 0x060, 0x10, 11, 1),
5777 + PIN_FIELD_BASE(177, 177, 6, 0x060, 0x10, 10, 1),
5778 + PIN_FIELD_BASE(178, 178, 6, 0x060, 0x10, 16, 1),
5779 + PIN_FIELD_BASE(179, 179, 6, 0x060, 0x10, 25, 1),
5780 +};
5781 +
5782 +static const struct mtk_pin_field_calc mt8183_pin_pullsel_range[] = {
5783 + PIN_FIELD_BASE(0, 3, 6, 0x080, 0x10, 6, 1),
5784 + PIN_FIELD_BASE(4, 7, 6, 0x080, 0x10, 11, 1),
5785 + PIN_FIELD_BASE(8, 8, 6, 0x080, 0x10, 0, 1),
5786 + PIN_FIELD_BASE(9, 10, 6, 0x080, 0x10, 26, 1),
5787 + PIN_FIELD_BASE(11, 11, 1, 0x080, 0x10, 10, 1),
5788 + PIN_FIELD_BASE(12, 12, 1, 0x080, 0x10, 17, 1),
5789 + PIN_FIELD_BASE(13, 28, 2, 0x080, 0x10, 6, 1),
5790 + PIN_FIELD_BASE(43, 49, 3, 0x080, 0x10, 8, 1),
5791 + PIN_FIELD_BASE(50, 60, 4, 0x080, 0x10, 0, 1),
5792 + PIN_FIELD_BASE(61, 88, 5, 0x080, 0x10, 0, 1),
5793 + PIN_FIELD_BASE(89, 89, 6, 0x080, 0x10, 24, 1),
5794 + PIN_FIELD_BASE(90, 90, 6, 0x080, 0x10, 1, 1),
5795 + PIN_FIELD_BASE(95, 95, 6, 0x080, 0x10, 15, 1),
5796 + PIN_FIELD_BASE(96, 102, 6, 0x080, 0x10, 17, 1),
5797 + PIN_FIELD_BASE(103, 106, 6, 0x080, 0x10, 28, 1),
5798 + PIN_FIELD_BASE(107, 121, 7, 0x080, 0x10, 0, 1),
5799 + PIN_FIELD_BASE(134, 143, 1, 0x080, 0x10, 0, 1),
5800 + PIN_FIELD_BASE(144, 149, 1, 0x080, 0x10, 11, 1),
5801 + PIN_FIELD_BASE(150, 160, 1, 0x080, 0x10, 18, 1),
5802 + PIN_FIELD_BASE(161, 166, 2, 0x080, 0x10, 0, 1),
5803 + PIN_FIELD_BASE(167, 176, 4, 0x080, 0x10, 11, 1),
5804 + PIN_FIELD_BASE(177, 177, 6, 0x080, 0x10, 10, 1),
5805 + PIN_FIELD_BASE(178, 178, 6, 0x080, 0x10, 16, 1),
5806 + PIN_FIELD_BASE(179, 179, 6, 0x080, 0x10, 25, 1),
5807 +};
5808 +
5809 +static const struct mtk_pin_field_calc mt8183_pin_drv_range[] = {
5810 + PINS_FIELD_BASE(0, 3, 6, 0x0A0, 0x10, 12, 3),
5811 + PINS_FIELD_BASE(4, 7, 6, 0x0A0, 0x10, 20, 3),
5812 + PIN_FIELD_BASE(8, 8, 6, 0x0A0, 0x10, 0, 3),
5813 + PINS_FIELD_BASE(9, 10, 6, 0x0B0, 0x10, 16, 3),
5814 + PIN_FIELD_BASE(11, 11, 1, 0x0A0, 0x10, 12, 3),
5815 + PIN_FIELD_BASE(12, 12, 1, 0x0A0, 0x10, 28, 3),
5816 + PINS_FIELD_BASE(13, 16, 2, 0x0A0, 0x10, 8, 3),
5817 + PINS_FIELD_BASE(17, 20, 2, 0x0A0, 0x10, 12, 3),
5818 + PINS_FIELD_BASE(21, 24, 2, 0x0A0, 0x10, 16, 3),
5819 + PINS_FIELD_BASE(25, 28, 2, 0x0A0, 0x10, 20, 3),
5820 + PIN_FIELD_BASE(29, 29, 2, 0x0A0, 0x10, 24, 3),
5821 + PIN_FIELD_BASE(30, 30, 2, 0x0A0, 0x10, 28, 3),
5822 + PINS_FIELD_BASE(31, 31, 2, 0x0B0, 0x10, 0, 3),
5823 + PINS_FIELD_BASE(32, 34, 2, 0x0A0, 0x10, 28, 3),
5824 + PINS_FIELD_BASE(35, 37, 3, 0x0A0, 0x10, 0, 3),
5825 + PINS_FIELD_BASE(38, 40, 3, 0x0A0, 0x10, 4, 3),
5826 + PINS_FIELD_BASE(41, 42, 3, 0x0A0, 0x10, 8, 3),
5827 + PINS_FIELD_BASE(43, 45, 3, 0x0A0, 0x10, 12, 3),
5828 + PINS_FIELD_BASE(46, 47, 3, 0x0A0, 0x10, 16, 3),
5829 + PINS_FIELD_BASE(48, 49, 3, 0x0A0, 0x10, 20, 3),
5830 + PINS_FIELD_BASE(50, 51, 4, 0x0A0, 0x10, 0, 3),
5831 + PINS_FIELD_BASE(52, 57, 4, 0x0A0, 0x10, 4, 3),
5832 + PINS_FIELD_BASE(58, 60, 4, 0x0A0, 0x10, 8, 3),
5833 + PINS_FIELD_BASE(61, 64, 5, 0x0A0, 0x10, 0, 3),
5834 + PINS_FIELD_BASE(65, 66, 5, 0x0A0, 0x10, 4, 3),
5835 + PINS_FIELD_BASE(67, 68, 5, 0x0A0, 0x10, 8, 3),
5836 + PINS_FIELD_BASE(69, 71, 5, 0x0A0, 0x10, 12, 3),
5837 + PINS_FIELD_BASE(72, 76, 5, 0x0A0, 0x10, 16, 3),
5838 + PINS_FIELD_BASE(77, 80, 5, 0x0A0, 0x10, 20, 3),
5839 + PIN_FIELD_BASE(81, 81, 5, 0x0A0, 0x10, 24, 3),
5840 + PINS_FIELD_BASE(82, 83, 5, 0x0A0, 0x10, 28, 3),
5841 + PIN_FIELD_BASE(84, 84, 5, 0x0A0, 0x10, 24, 3),
5842 + PINS_FIELD_BASE(85, 88, 5, 0x0B0, 0x10, 0, 3),
5843 + PIN_FIELD_BASE(89, 89, 6, 0x0B0, 0x10, 12, 3),
5844 + PIN_FIELD_BASE(90, 90, 6, 0x0A0, 0x10, 4, 3),
5845 + PINS_FIELD_BASE(91, 94, 6, 0x0A0, 0x10, 8, 3),
5846 + PINS_FIELD_BASE(95, 96, 6, 0x0A0, 0x10, 24, 3),
5847 + PINS_FIELD_BASE(97, 98, 6, 0x0A0, 0x10, 28, 3),
5848 + PIN_FIELD_BASE(99, 99, 6, 0x0B0, 0x10, 0, 3),
5849 + PIN_FIELD_BASE(100, 100, 6, 0x0B0, 0x10, 4, 3),
5850 + PINS_FIELD_BASE(101, 102, 6, 0x0B0, 0x10, 8, 3),
5851 + PINS_FIELD_BASE(103, 104, 6, 0x0B0, 0x10, 20, 3),
5852 + PINS_FIELD_BASE(105, 106, 6, 0x0B0, 0x10, 24, 3),
5853 + PIN_FIELD_BASE(107, 107, 7, 0x0A0, 0x10, 0, 3),
5854 + PIN_FIELD_BASE(108, 108, 7, 0x0A0, 0x10, 4, 3),
5855 + PIN_FIELD_BASE(109, 109, 7, 0x0A0, 0x10, 8, 3),
5856 + PIN_FIELD_BASE(110, 110, 7, 0x0A0, 0x10, 0, 3),
5857 + PIN_FIELD_BASE(111, 111, 7, 0x0A0, 0x10, 4, 3),
5858 + PIN_FIELD_BASE(112, 112, 7, 0x0A0, 0x10, 8, 3),
5859 + PIN_FIELD_BASE(113, 113, 7, 0x0A0, 0x10, 16, 3),
5860 + PIN_FIELD_BASE(114, 114, 7, 0x0A0, 0x10, 20, 3),
5861 + PIN_FIELD_BASE(115, 115, 7, 0x0A0, 0x10, 24, 3),
5862 + PIN_FIELD_BASE(116, 116, 7, 0x0A0, 0x10, 28, 3),
5863 + PIN_FIELD_BASE(117, 117, 7, 0x0B0, 0x10, 0, 3),
5864 + PIN_FIELD_BASE(118, 118, 7, 0x0B0, 0x10, 4, 3),
5865 + PIN_FIELD_BASE(119, 119, 7, 0x0B0, 0x10, 8, 3),
5866 + PIN_FIELD_BASE(120, 120, 7, 0x0B0, 0x10, 12, 3),
5867 + PIN_FIELD_BASE(121, 121, 7, 0x0B0, 0x10, 16, 3),
5868 + PIN_FIELD_BASE(122, 122, 8, 0x0A0, 0x10, 0, 3),
5869 + PIN_FIELD_BASE(123, 123, 8, 0x0A0, 0x10, 4, 3),
5870 + PIN_FIELD_BASE(124, 124, 8, 0x0A0, 0x10, 8, 3),
5871 + PINS_FIELD_BASE(125, 130, 8, 0x0A0, 0x10, 4, 3),
5872 + PIN_FIELD_BASE(131, 131, 8, 0x0A0, 0x10, 12, 3),
5873 + PIN_FIELD_BASE(132, 132, 8, 0x0A0, 0x10, 4, 3),
5874 + PIN_FIELD_BASE(133, 133, 8, 0x0A0, 0x10, 16, 3),
5875 + PIN_FIELD_BASE(134, 134, 1, 0x0A0, 0x10, 0, 3),
5876 + PIN_FIELD_BASE(135, 135, 1, 0x0A0, 0x10, 4, 3),
5877 + PINS_FIELD_BASE(136, 143, 1, 0x0A0, 0x10, 8, 3),
5878 + PINS_FIELD_BASE(144, 147, 1, 0x0A0, 0x10, 16, 3),
5879 + PIN_FIELD_BASE(148, 148, 1, 0x0A0, 0x10, 20, 3),
5880 + PIN_FIELD_BASE(149, 149, 1, 0x0A0, 0x10, 24, 3),
5881 + PINS_FIELD_BASE(150, 153, 1, 0x0B0, 0x10, 0, 3),
5882 + PIN_FIELD_BASE(154, 154, 1, 0x0B0, 0x10, 4, 3),
5883 + PINS_FIELD_BASE(155, 157, 1, 0x0B0, 0x10, 8, 3),
5884 + PINS_FIELD_BASE(158, 160, 1, 0x0B0, 0x10, 0, 3),
5885 + PINS_FIELD_BASE(161, 164, 2, 0x0A0, 0x10, 0, 3),
5886 + PINS_FIELD_BASE(165, 166, 2, 0x0A0, 0x10, 4, 3),
5887 + PINS_FIELD_BASE(167, 168, 4, 0x0A0, 0x10, 8, 3),
5888 + PIN_FIELD_BASE(169, 169, 4, 0x0A0, 0x10, 12, 3),
5889 + PINS_FIELD_BASE(170, 174, 4, 0x0A0, 0x10, 16, 3),
5890 + PINS_FIELD_BASE(175, 176, 4, 0x0A0, 0x10, 12, 3),
5891 + PINS_FIELD_BASE(177, 179, 6, 0x0A0, 0x10, 16, 3),
5892 +};
5893 +
5894 +static const struct mtk_pin_field_calc mt8183_pin_pupd_range[] = {
5895 + PIN_FIELD_BASE(29, 29, 2, 0x0C0, 0x10, 2, 1),
5896 + PIN_FIELD_BASE(30, 30, 2, 0x0C0, 0x10, 6, 1),
5897 + PIN_FIELD_BASE(31, 31, 2, 0x0C0, 0x10, 10, 1),
5898 + PIN_FIELD_BASE(32, 32, 2, 0x0C0, 0x10, 14, 1),
5899 + PIN_FIELD_BASE(33, 33, 2, 0x0C0, 0x10, 18, 1),
5900 + PIN_FIELD_BASE(34, 34, 2, 0x0C0, 0x10, 22, 1),
5901 + PIN_FIELD_BASE(35, 35, 3, 0x0C0, 0x10, 2, 1),
5902 + PIN_FIELD_BASE(36, 36, 3, 0x0C0, 0x10, 6, 1),
5903 + PIN_FIELD_BASE(37, 37, 3, 0x0C0, 0x10, 10, 1),
5904 + PIN_FIELD_BASE(38, 38, 3, 0x0C0, 0x10, 14, 1),
5905 + PIN_FIELD_BASE(39, 39, 3, 0x0C0, 0x10, 18, 1),
5906 + PIN_FIELD_BASE(40, 40, 3, 0x0C0, 0x10, 22, 1),
5907 + PIN_FIELD_BASE(41, 41, 3, 0x0C0, 0x10, 26, 1),
5908 + PIN_FIELD_BASE(42, 42, 3, 0x0C0, 0x10, 30, 1),
5909 + PIN_FIELD_BASE(91, 91, 6, 0x0C0, 0x10, 2, 1),
5910 + PIN_FIELD_BASE(92, 92, 6, 0x0C0, 0x10, 6, 1),
5911 + PIN_FIELD_BASE(93, 93, 6, 0x0C0, 0x10, 10, 1),
5912 + PIN_FIELD_BASE(94, 94, 6, 0x0C0, 0x10, 14, 1),
5913 + PIN_FIELD_BASE(122, 122, 8, 0x0C0, 0x10, 2, 1),
5914 + PIN_FIELD_BASE(123, 123, 8, 0x0C0, 0x10, 6, 1),
5915 + PIN_FIELD_BASE(124, 124, 8, 0x0C0, 0x10, 10, 1),
5916 + PIN_FIELD_BASE(125, 125, 8, 0x0C0, 0x10, 14, 1),
5917 + PIN_FIELD_BASE(126, 126, 8, 0x0C0, 0x10, 18, 1),
5918 + PIN_FIELD_BASE(127, 127, 8, 0x0C0, 0x10, 22, 1),
5919 + PIN_FIELD_BASE(128, 128, 8, 0x0C0, 0x10, 26, 1),
5920 + PIN_FIELD_BASE(129, 129, 8, 0x0C0, 0x10, 30, 1),
5921 + PIN_FIELD_BASE(130, 130, 8, 0x0D0, 0x10, 2, 1),
5922 + PIN_FIELD_BASE(131, 131, 8, 0x0D0, 0x10, 6, 1),
5923 + PIN_FIELD_BASE(132, 132, 8, 0x0D0, 0x10, 10, 1),
5924 + PIN_FIELD_BASE(133, 133, 8, 0x0D0, 0x10, 14, 1),
5925 +};
5926 +
5927 +static const struct mtk_pin_field_calc mt8183_pin_r0_range[] = {
5928 + PIN_FIELD_BASE(29, 29, 2, 0x0C0, 0x10, 0, 1),
5929 + PIN_FIELD_BASE(30, 30, 2, 0x0C0, 0x10, 4, 1),
5930 + PIN_FIELD_BASE(31, 31, 2, 0x0C0, 0x10, 8, 1),
5931 + PIN_FIELD_BASE(32, 32, 2, 0x0C0, 0x10, 12, 1),
5932 + PIN_FIELD_BASE(33, 33, 2, 0x0C0, 0x10, 16, 1),
5933 + PIN_FIELD_BASE(34, 34, 2, 0x0C0, 0x10, 20, 1),
5934 + PIN_FIELD_BASE(35, 35, 3, 0x0C0, 0x10, 0, 1),
5935 + PIN_FIELD_BASE(36, 36, 3, 0x0C0, 0x10, 4, 1),
5936 + PIN_FIELD_BASE(37, 37, 3, 0x0C0, 0x10, 8, 1),
5937 + PIN_FIELD_BASE(38, 38, 3, 0x0C0, 0x10, 12, 1),
5938 + PIN_FIELD_BASE(39, 39, 3, 0x0C0, 0x10, 16, 1),
5939 + PIN_FIELD_BASE(40, 40, 3, 0x0C0, 0x10, 20, 1),
5940 + PIN_FIELD_BASE(41, 41, 3, 0x0C0, 0x10, 24, 1),
5941 + PIN_FIELD_BASE(42, 42, 3, 0x0C0, 0x10, 28, 1),
5942 + PIN_FIELD_BASE(48, 48, 3, 0x0F0, 0x10, 18, 1),
5943 + PIN_FIELD_BASE(49, 49, 3, 0x0F0, 0x10, 13, 1),
5944 + PIN_FIELD_BASE(50, 50, 4, 0x0F0, 0x10, 10, 1),
5945 + PIN_FIELD_BASE(51, 51, 4, 0x0F0, 0x10, 5, 1),
5946 + PIN_FIELD_BASE(81, 81, 5, 0x0F0, 0x10, 7, 1),
5947 + PIN_FIELD_BASE(82, 82, 5, 0x0F0, 0x10, 5, 1),
5948 + PIN_FIELD_BASE(83, 83, 5, 0x0F0, 0x10, 15, 1),
5949 + PIN_FIELD_BASE(84, 84, 5, 0x0F0, 0x10, 17, 1),
5950 + PIN_FIELD_BASE(91, 91, 6, 0x0C0, 0x10, 0, 1),
5951 + PIN_FIELD_BASE(92, 92, 6, 0x0C0, 0x10, 4, 1),
5952 + PIN_FIELD_BASE(93, 93, 6, 0x0C0, 0x10, 8, 1),
5953 + PIN_FIELD_BASE(94, 94, 6, 0x0C0, 0x10, 12, 1),
5954 + PIN_FIELD_BASE(103, 103, 6, 0x0F0, 0x10, 20, 1),
5955 + PIN_FIELD_BASE(104, 104, 6, 0x0F0, 0x10, 10, 1),
5956 + PIN_FIELD_BASE(105, 105, 6, 0x0F0, 0x10, 22, 1),
5957 + PIN_FIELD_BASE(106, 106, 6, 0x0F0, 0x10, 12, 1),
5958 + PIN_FIELD_BASE(122, 122, 8, 0x0C0, 0x10, 0, 1),
5959 + PIN_FIELD_BASE(123, 123, 8, 0x0C0, 0x10, 4, 1),
5960 + PIN_FIELD_BASE(124, 124, 8, 0x0C0, 0x10, 8, 1),
5961 + PIN_FIELD_BASE(125, 125, 8, 0x0C0, 0x10, 12, 1),
5962 + PIN_FIELD_BASE(126, 126, 8, 0x0C0, 0x10, 16, 1),
5963 + PIN_FIELD_BASE(127, 127, 8, 0x0C0, 0x10, 20, 1),
5964 + PIN_FIELD_BASE(128, 128, 8, 0x0C0, 0x10, 24, 1),
5965 + PIN_FIELD_BASE(129, 129, 8, 0x0C0, 0x10, 28, 1),
5966 + PIN_FIELD_BASE(130, 130, 8, 0x0D0, 0x10, 0, 1),
5967 + PIN_FIELD_BASE(131, 131, 8, 0x0D0, 0x10, 4, 1),
5968 + PIN_FIELD_BASE(132, 132, 8, 0x0D0, 0x10, 8, 1),
5969 + PIN_FIELD_BASE(133, 133, 8, 0x0D0, 0x10, 12, 1),
5970 +};
5971 +
5972 +static const struct mtk_pin_field_calc mt8183_pin_r1_range[] = {
5973 + PIN_FIELD_BASE(29, 29, 2, 0x0C0, 0x10, 1, 1),
5974 + PIN_FIELD_BASE(30, 30, 2, 0x0C0, 0x10, 5, 1),
5975 + PIN_FIELD_BASE(31, 31, 2, 0x0C0, 0x10, 9, 1),
5976 + PIN_FIELD_BASE(32, 32, 2, 0x0C0, 0x10, 13, 1),
5977 + PIN_FIELD_BASE(33, 33, 2, 0x0C0, 0x10, 17, 1),
5978 + PIN_FIELD_BASE(34, 34, 2, 0x0C0, 0x10, 21, 1),
5979 + PIN_FIELD_BASE(35, 35, 3, 0x0C0, 0x10, 1, 1),
5980 + PIN_FIELD_BASE(36, 36, 3, 0x0C0, 0x10, 5, 1),
5981 + PIN_FIELD_BASE(37, 37, 3, 0x0C0, 0x10, 9, 1),
5982 + PIN_FIELD_BASE(38, 38, 3, 0x0C0, 0x10, 13, 1),
5983 + PIN_FIELD_BASE(39, 39, 3, 0x0C0, 0x10, 17, 1),
5984 + PIN_FIELD_BASE(40, 40, 3, 0x0C0, 0x10, 21, 1),
5985 + PIN_FIELD_BASE(41, 41, 3, 0x0C0, 0x10, 25, 1),
5986 + PIN_FIELD_BASE(42, 42, 3, 0x0C0, 0x10, 29, 1),
5987 + PIN_FIELD_BASE(48, 48, 3, 0x0F0, 0x10, 19, 1),
5988 + PIN_FIELD_BASE(49, 49, 3, 0x0F0, 0x10, 14, 1),
5989 + PIN_FIELD_BASE(50, 50, 4, 0x0F0, 0x10, 11, 1),
5990 + PIN_FIELD_BASE(51, 51, 4, 0x0F0, 0x10, 6, 1),
5991 + PIN_FIELD_BASE(81, 81, 5, 0x0F0, 0x10, 8, 1),
5992 + PIN_FIELD_BASE(82, 82, 5, 0x0F0, 0x10, 6, 1),
5993 + PIN_FIELD_BASE(83, 83, 5, 0x0F0, 0x10, 16, 1),
5994 + PIN_FIELD_BASE(84, 84, 5, 0x0F0, 0x10, 18, 1),
5995 + PIN_FIELD_BASE(91, 91, 6, 0x0C0, 0x10, 1, 1),
5996 + PIN_FIELD_BASE(92, 92, 6, 0x0C0, 0x10, 5, 1),
5997 + PIN_FIELD_BASE(93, 93, 6, 0x0C0, 0x10, 9, 1),
5998 + PIN_FIELD_BASE(94, 94, 6, 0x0C0, 0x10, 13, 1),
5999 + PIN_FIELD_BASE(103, 103, 6, 0x0F0, 0x10, 21, 1),
6000 + PIN_FIELD_BASE(104, 104, 6, 0x0F0, 0x10, 11, 1),
6001 + PIN_FIELD_BASE(105, 105, 6, 0x0F0, 0x10, 23, 1),
6002 + PIN_FIELD_BASE(106, 106, 6, 0x0F0, 0x10, 13, 1),
6003 + PIN_FIELD_BASE(122, 122, 8, 0x0C0, 0x10, 1, 1),
6004 + PIN_FIELD_BASE(123, 123, 8, 0x0C0, 0x10, 5, 1),
6005 + PIN_FIELD_BASE(124, 124, 8, 0x0C0, 0x10, 9, 1),
6006 + PIN_FIELD_BASE(125, 125, 8, 0x0C0, 0x10, 13, 1),
6007 + PIN_FIELD_BASE(126, 126, 8, 0x0C0, 0x10, 17, 1),
6008 + PIN_FIELD_BASE(127, 127, 8, 0x0C0, 0x10, 21, 1),
6009 + PIN_FIELD_BASE(128, 128, 8, 0x0C0, 0x10, 25, 1),
6010 + PIN_FIELD_BASE(129, 129, 8, 0x0C0, 0x10, 29, 1),
6011 + PIN_FIELD_BASE(130, 130, 8, 0x0D0, 0x10, 1, 1),
6012 + PIN_FIELD_BASE(131, 131, 8, 0x0D0, 0x10, 5, 1),
6013 + PIN_FIELD_BASE(132, 132, 8, 0x0D0, 0x10, 9, 1),
6014 + PIN_FIELD_BASE(133, 133, 8, 0x0D0, 0x10, 13, 1),
6015 +};
6016 +
6017 +static const struct mtk_pin_field_calc mt8183_pin_e1e0en_range[] = {
6018 + PIN_FIELD_BASE(48, 48, 3, 0x0F0, 0x10, 20, 1),
6019 + PIN_FIELD_BASE(49, 49, 3, 0x0F0, 0x10, 15, 1),
6020 + PIN_FIELD_BASE(50, 50, 4, 0x0F0, 0x10, 12, 1),
6021 + PIN_FIELD_BASE(51, 51, 4, 0x0F0, 0x10, 7, 1),
6022 + PIN_FIELD_BASE(81, 81, 5, 0x0F0, 0x10, 12, 1),
6023 + PIN_FIELD_BASE(82, 82, 5, 0x0F0, 0x10, 9, 1),
6024 + PIN_FIELD_BASE(83, 83, 5, 0x0F0, 0x10, 19, 1),
6025 + PIN_FIELD_BASE(84, 84, 5, 0x0F0, 0x10, 22, 1),
6026 + PIN_FIELD_BASE(103, 103, 6, 0x0F0, 0x10, 24, 1),
6027 + PIN_FIELD_BASE(104, 104, 6, 0x0F0, 0x10, 14, 1),
6028 + PIN_FIELD_BASE(105, 105, 6, 0x0F0, 0x10, 27, 1),
6029 + PIN_FIELD_BASE(106, 106, 6, 0x0F0, 0x10, 17, 1),
6030 +};
6031 +
6032 +static const struct mtk_pin_field_calc mt8183_pin_e0_range[] = {
6033 + PIN_FIELD_BASE(48, 48, 3, 0x0F0, 0x10, 21, 1),
6034 + PIN_FIELD_BASE(49, 49, 3, 0x0F0, 0x10, 16, 1),
6035 + PIN_FIELD_BASE(50, 50, 4, 0x0F0, 0x10, 13, 1),
6036 + PIN_FIELD_BASE(51, 51, 4, 0x0F0, 0x10, 8, 1),
6037 + PIN_FIELD_BASE(81, 81, 5, 0x0F0, 0x10, 13, 1),
6038 + PIN_FIELD_BASE(82, 82, 5, 0x0F0, 0x10, 10, 1),
6039 + PIN_FIELD_BASE(83, 83, 5, 0x0F0, 0x10, 20, 1),
6040 + PIN_FIELD_BASE(84, 84, 5, 0x0F0, 0x10, 23, 1),
6041 + PIN_FIELD_BASE(103, 103, 6, 0x0F0, 0x10, 25, 1),
6042 + PIN_FIELD_BASE(104, 104, 6, 0x0F0, 0x10, 15, 1),
6043 + PIN_FIELD_BASE(105, 105, 6, 0x0F0, 0x10, 28, 1),
6044 + PIN_FIELD_BASE(106, 106, 6, 0x0F0, 0x10, 18, 1),
6045 +};
6046 +
6047 +static const struct mtk_pin_field_calc mt8183_pin_e1_range[] = {
6048 + PIN_FIELD_BASE(48, 48, 3, 0x0F0, 0x10, 22, 1),
6049 + PIN_FIELD_BASE(49, 49, 3, 0x0F0, 0x10, 17, 1),
6050 + PIN_FIELD_BASE(50, 50, 4, 0x0F0, 0x10, 14, 1),
6051 + PIN_FIELD_BASE(51, 51, 4, 0x0F0, 0x10, 9, 1),
6052 + PIN_FIELD_BASE(81, 81, 5, 0x0F0, 0x10, 14, 1),
6053 + PIN_FIELD_BASE(82, 82, 5, 0x0F0, 0x10, 11, 1),
6054 + PIN_FIELD_BASE(83, 83, 5, 0x0F0, 0x10, 21, 1),
6055 + PIN_FIELD_BASE(84, 84, 5, 0x0F0, 0x10, 24, 1),
6056 + PIN_FIELD_BASE(103, 103, 6, 0x0F0, 0x10, 26, 1),
6057 + PIN_FIELD_BASE(104, 104, 6, 0x0F0, 0x10, 16, 1),
6058 + PIN_FIELD_BASE(105, 105, 6, 0x0F0, 0x10, 29, 1),
6059 + PIN_FIELD_BASE(106, 106, 6, 0x0F0, 0x10, 19, 1),
6060 +};
6061 +
6062 +static const struct mtk_pin_reg_calc mt8183_reg_cals[PINCTRL_PIN_REG_MAX] = {
6063 + [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt8183_pin_mode_range),
6064 + [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt8183_pin_dir_range),
6065 + [PINCTRL_PIN_REG_DI] = MTK_RANGE(mt8183_pin_di_range),
6066 + [PINCTRL_PIN_REG_DO] = MTK_RANGE(mt8183_pin_do_range),
6067 + [PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt8183_pin_smt_range),
6068 + [PINCTRL_PIN_REG_IES] = MTK_RANGE(mt8183_pin_ies_range),
6069 + [PINCTRL_PIN_REG_PULLEN] = MTK_RANGE(mt8183_pin_pullen_range),
6070 + [PINCTRL_PIN_REG_PULLSEL] = MTK_RANGE(mt8183_pin_pullsel_range),
6071 + [PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt8183_pin_drv_range),
6072 + [PINCTRL_PIN_REG_PUPD] = MTK_RANGE(mt8183_pin_pupd_range),
6073 + [PINCTRL_PIN_REG_R0] = MTK_RANGE(mt8183_pin_r0_range),
6074 + [PINCTRL_PIN_REG_R1] = MTK_RANGE(mt8183_pin_r1_range),
6075 + [PINCTRL_PIN_REG_DRV_EN] = MTK_RANGE(mt8183_pin_e1e0en_range),
6076 + [PINCTRL_PIN_REG_DRV_E0] = MTK_RANGE(mt8183_pin_e0_range),
6077 + [PINCTRL_PIN_REG_DRV_E1] = MTK_RANGE(mt8183_pin_e1_range),
6078 +};
6079 +
6080 +static const char * const mt8183_pinctrl_register_base_names[] = {
6081 + "iocfg0", "iocfg1", "iocfg2", "iocfg3", "iocfg4", "iocfg5",
6082 + "iocfg6", "iocfg7", "iocfg8",
6083 +};
6084 +
6085 +static const struct mtk_eint_hw mt8183_eint_hw = {
6086 + .port_mask = 7,
6087 + .ports = 6,
6088 + .ap_num = 212,
6089 + .db_cnt = 13,
6090 +};
6091 +
6092 +static const struct mtk_pin_soc mt8183_data = {
6093 + .reg_cal = mt8183_reg_cals,
6094 + .pins = mtk_pins_mt8183,
6095 + .npins = ARRAY_SIZE(mtk_pins_mt8183),
6096 + .ngrps = ARRAY_SIZE(mtk_pins_mt8183),
6097 + .eint_hw = &mt8183_eint_hw,
6098 + .gpio_m = 0,
6099 + .ies_present = true,
6100 + .base_names = mt8183_pinctrl_register_base_names,
6101 + .nbase_names = ARRAY_SIZE(mt8183_pinctrl_register_base_names),
6102 + .bias_disable_set = mtk_pinconf_bias_disable_set_rev1,
6103 + .bias_disable_get = mtk_pinconf_bias_disable_get_rev1,
6104 + .bias_set = mtk_pinconf_bias_set_rev1,
6105 + .bias_get = mtk_pinconf_bias_get_rev1,
6106 + .drive_set = mtk_pinconf_drive_set_rev1,
6107 + .drive_get = mtk_pinconf_drive_get_rev1,
6108 + .adv_pull_get = mtk_pinconf_adv_pull_get,
6109 + .adv_pull_set = mtk_pinconf_adv_pull_set,
6110 + .adv_drive_get = mtk_pinconf_adv_drive_get,
6111 + .adv_drive_set = mtk_pinconf_adv_drive_set,
6112 +};
6113 +
6114 +static const struct of_device_id mt8183_pinctrl_of_match[] = {
6115 + { .compatible = "mediatek,mt8183-pinctrl", },
6116 + { }
6117 +};
6118 +
6119 +static int mt8183_pinctrl_probe(struct platform_device *pdev)
6120 +{
6121 + return mtk_paris_pinctrl_probe(pdev, &mt8183_data);
6122 +}
6123 +
6124 +static struct platform_driver mt8183_pinctrl_driver = {
6125 + .driver = {
6126 + .name = "mt8183-pinctrl",
6127 + .of_match_table = mt8183_pinctrl_of_match,
6128 + .pm = &mtk_paris_pinctrl_pm_ops,
6129 + },
6130 + .probe = mt8183_pinctrl_probe,
6131 +};
6132 +
6133 +static int __init mt8183_pinctrl_init(void)
6134 +{
6135 + return platform_driver_register(&mt8183_pinctrl_driver);
6136 +}
6137 +arch_initcall(mt8183_pinctrl_init);
6138 --- /dev/null
6139 +++ b/drivers/pinctrl/mediatek/pinctrl-mt8516.c
6140 @@ -0,0 +1,362 @@
6141 +// SPDX-License-Identifier: GPL-2.0
6142 +/*
6143 + * Copyright (c) 2019 MediaTek Inc.
6144 + * Author: Min.Guo <min.guo@mediatek.com>
6145 + */
6146 +
6147 +#include <dt-bindings/pinctrl/mt65xx.h>
6148 +#include <linux/of.h>
6149 +#include <linux/of_device.h>
6150 +#include <linux/module.h>
6151 +#include <linux/pinctrl/pinctrl.h>
6152 +#include <linux/platform_device.h>
6153 +#include <linux/regmap.h>
6154 +
6155 +#include "pinctrl-mtk-common.h"
6156 +#include "pinctrl-mtk-mt8516.h"
6157 +
6158 +static const struct mtk_drv_group_desc mt8516_drv_grp[] = {
6159 + /* 0E4E8SR 4/8/12/16 */
6160 + MTK_DRV_GRP(4, 16, 1, 2, 4),
6161 + /* 0E2E4SR 2/4/6/8 */
6162 + MTK_DRV_GRP(2, 8, 1, 2, 2),
6163 + /* E8E4E2 2/4/6/8/10/12/14/16 */
6164 + MTK_DRV_GRP(2, 16, 0, 2, 2)
6165 +};
6166 +
6167 +static const struct mtk_pin_drv_grp mt8516_pin_drv[] = {
6168 + MTK_PIN_DRV_GRP(0, 0xd00, 0, 0),
6169 + MTK_PIN_DRV_GRP(1, 0xd00, 0, 0),
6170 + MTK_PIN_DRV_GRP(2, 0xd00, 0, 0),
6171 + MTK_PIN_DRV_GRP(3, 0xd00, 0, 0),
6172 + MTK_PIN_DRV_GRP(4, 0xd00, 0, 0),
6173 +
6174 + MTK_PIN_DRV_GRP(5, 0xd00, 4, 0),
6175 + MTK_PIN_DRV_GRP(6, 0xd00, 4, 0),
6176 + MTK_PIN_DRV_GRP(7, 0xd00, 4, 0),
6177 + MTK_PIN_DRV_GRP(8, 0xd00, 4, 0),
6178 + MTK_PIN_DRV_GRP(9, 0xd00, 4, 0),
6179 + MTK_PIN_DRV_GRP(10, 0xd00, 4, 0),
6180 +
6181 + MTK_PIN_DRV_GRP(11, 0xd00, 8, 0),
6182 + MTK_PIN_DRV_GRP(12, 0xd00, 8, 0),
6183 + MTK_PIN_DRV_GRP(13, 0xd00, 8, 0),
6184 +
6185 + MTK_PIN_DRV_GRP(14, 0xd00, 12, 2),
6186 + MTK_PIN_DRV_GRP(15, 0xd00, 12, 2),
6187 + MTK_PIN_DRV_GRP(16, 0xd00, 12, 2),
6188 + MTK_PIN_DRV_GRP(17, 0xd00, 12, 2),
6189 +
6190 + MTK_PIN_DRV_GRP(18, 0xd10, 0, 0),
6191 + MTK_PIN_DRV_GRP(19, 0xd10, 0, 0),
6192 + MTK_PIN_DRV_GRP(20, 0xd10, 0, 0),
6193 +
6194 + MTK_PIN_DRV_GRP(21, 0xd00, 12, 2),
6195 + MTK_PIN_DRV_GRP(22, 0xd00, 12, 2),
6196 + MTK_PIN_DRV_GRP(23, 0xd00, 12, 2),
6197 +
6198 + MTK_PIN_DRV_GRP(24, 0xd00, 8, 0),
6199 + MTK_PIN_DRV_GRP(25, 0xd00, 8, 0),
6200 +
6201 + MTK_PIN_DRV_GRP(26, 0xd10, 4, 1),
6202 + MTK_PIN_DRV_GRP(27, 0xd10, 4, 1),
6203 + MTK_PIN_DRV_GRP(28, 0xd10, 4, 1),
6204 + MTK_PIN_DRV_GRP(29, 0xd10, 4, 1),
6205 + MTK_PIN_DRV_GRP(30, 0xd10, 4, 1),
6206 +
6207 + MTK_PIN_DRV_GRP(31, 0xd10, 8, 1),
6208 + MTK_PIN_DRV_GRP(32, 0xd10, 8, 1),
6209 + MTK_PIN_DRV_GRP(33, 0xd10, 8, 1),
6210 +
6211 + MTK_PIN_DRV_GRP(34, 0xd10, 12, 0),
6212 + MTK_PIN_DRV_GRP(35, 0xd10, 12, 0),
6213 +
6214 + MTK_PIN_DRV_GRP(36, 0xd20, 0, 0),
6215 + MTK_PIN_DRV_GRP(37, 0xd20, 0, 0),
6216 + MTK_PIN_DRV_GRP(38, 0xd20, 0, 0),
6217 + MTK_PIN_DRV_GRP(39, 0xd20, 0, 0),
6218 +
6219 + MTK_PIN_DRV_GRP(40, 0xd20, 4, 1),
6220 +
6221 + MTK_PIN_DRV_GRP(41, 0xd20, 8, 1),
6222 + MTK_PIN_DRV_GRP(42, 0xd20, 8, 1),
6223 + MTK_PIN_DRV_GRP(43, 0xd20, 8, 1),
6224 +
6225 + MTK_PIN_DRV_GRP(44, 0xd20, 12, 1),
6226 + MTK_PIN_DRV_GRP(45, 0xd20, 12, 1),
6227 + MTK_PIN_DRV_GRP(46, 0xd20, 12, 1),
6228 + MTK_PIN_DRV_GRP(47, 0xd20, 12, 1),
6229 +
6230 + MTK_PIN_DRV_GRP(48, 0xd30, 0, 1),
6231 + MTK_PIN_DRV_GRP(49, 0xd30, 0, 1),
6232 + MTK_PIN_DRV_GRP(50, 0xd30, 0, 1),
6233 + MTK_PIN_DRV_GRP(51, 0xd30, 0, 1),
6234 +
6235 + MTK_PIN_DRV_GRP(54, 0xd30, 8, 1),
6236 +
6237 + MTK_PIN_DRV_GRP(55, 0xd30, 12, 1),
6238 + MTK_PIN_DRV_GRP(56, 0xd30, 12, 1),
6239 + MTK_PIN_DRV_GRP(57, 0xd30, 12, 1),
6240 +
6241 + MTK_PIN_DRV_GRP(62, 0xd40, 8, 1),
6242 + MTK_PIN_DRV_GRP(63, 0xd40, 8, 1),
6243 + MTK_PIN_DRV_GRP(64, 0xd40, 8, 1),
6244 + MTK_PIN_DRV_GRP(65, 0xd40, 8, 1),
6245 + MTK_PIN_DRV_GRP(66, 0xd40, 8, 1),
6246 + MTK_PIN_DRV_GRP(67, 0xd40, 8, 1),
6247 +
6248 + MTK_PIN_DRV_GRP(68, 0xd40, 12, 2),
6249 +
6250 + MTK_PIN_DRV_GRP(69, 0xd50, 0, 2),
6251 +
6252 + MTK_PIN_DRV_GRP(70, 0xd50, 4, 2),
6253 + MTK_PIN_DRV_GRP(71, 0xd50, 4, 2),
6254 + MTK_PIN_DRV_GRP(72, 0xd50, 4, 2),
6255 + MTK_PIN_DRV_GRP(73, 0xd50, 4, 2),
6256 +
6257 + MTK_PIN_DRV_GRP(100, 0xd50, 8, 1),
6258 + MTK_PIN_DRV_GRP(101, 0xd50, 8, 1),
6259 + MTK_PIN_DRV_GRP(102, 0xd50, 8, 1),
6260 + MTK_PIN_DRV_GRP(103, 0xd50, 8, 1),
6261 +
6262 + MTK_PIN_DRV_GRP(104, 0xd50, 12, 2),
6263 +
6264 + MTK_PIN_DRV_GRP(105, 0xd60, 0, 2),
6265 +
6266 + MTK_PIN_DRV_GRP(106, 0xd60, 4, 2),
6267 + MTK_PIN_DRV_GRP(107, 0xd60, 4, 2),
6268 + MTK_PIN_DRV_GRP(108, 0xd60, 4, 2),
6269 + MTK_PIN_DRV_GRP(109, 0xd60, 4, 2),
6270 +
6271 + MTK_PIN_DRV_GRP(110, 0xd70, 0, 2),
6272 + MTK_PIN_DRV_GRP(111, 0xd70, 0, 2),
6273 + MTK_PIN_DRV_GRP(112, 0xd70, 0, 2),
6274 + MTK_PIN_DRV_GRP(113, 0xd70, 0, 2),
6275 +
6276 + MTK_PIN_DRV_GRP(114, 0xd70, 4, 2),
6277 +
6278 + MTK_PIN_DRV_GRP(115, 0xd60, 12, 2),
6279 +
6280 + MTK_PIN_DRV_GRP(116, 0xd60, 8, 2),
6281 +
6282 + MTK_PIN_DRV_GRP(117, 0xd70, 0, 2),
6283 + MTK_PIN_DRV_GRP(118, 0xd70, 0, 2),
6284 + MTK_PIN_DRV_GRP(119, 0xd70, 0, 2),
6285 + MTK_PIN_DRV_GRP(120, 0xd70, 0, 2),
6286 +};
6287 +
6288 +static const struct mtk_pin_spec_pupd_set_samereg mt8516_spec_pupd[] = {
6289 + MTK_PIN_PUPD_SPEC_SR(14, 0xe50, 14, 13, 12),
6290 + MTK_PIN_PUPD_SPEC_SR(15, 0xe60, 2, 1, 0),
6291 + MTK_PIN_PUPD_SPEC_SR(16, 0xe60, 6, 5, 4),
6292 + MTK_PIN_PUPD_SPEC_SR(17, 0xe60, 10, 9, 8),
6293 +
6294 + MTK_PIN_PUPD_SPEC_SR(21, 0xe60, 14, 13, 12),
6295 + MTK_PIN_PUPD_SPEC_SR(22, 0xe70, 2, 1, 0),
6296 + MTK_PIN_PUPD_SPEC_SR(23, 0xe70, 6, 5, 4),
6297 +
6298 + MTK_PIN_PUPD_SPEC_SR(40, 0xe80, 2, 1, 0),
6299 + MTK_PIN_PUPD_SPEC_SR(41, 0xe80, 6, 5, 4),
6300 + MTK_PIN_PUPD_SPEC_SR(42, 0xe90, 2, 1, 0),
6301 + MTK_PIN_PUPD_SPEC_SR(43, 0xe90, 6, 5, 4),
6302 +
6303 + MTK_PIN_PUPD_SPEC_SR(68, 0xe50, 10, 9, 8),
6304 + MTK_PIN_PUPD_SPEC_SR(69, 0xe50, 6, 5, 4),
6305 + MTK_PIN_PUPD_SPEC_SR(70, 0xe40, 6, 5, 4),
6306 + MTK_PIN_PUPD_SPEC_SR(71, 0xe40, 10, 9, 8),
6307 + MTK_PIN_PUPD_SPEC_SR(72, 0xe40, 14, 13, 12),
6308 + MTK_PIN_PUPD_SPEC_SR(73, 0xe50, 2, 1, 0),
6309 +
6310 + MTK_PIN_PUPD_SPEC_SR(104, 0xe40, 2, 1, 0),
6311 + MTK_PIN_PUPD_SPEC_SR(105, 0xe30, 14, 13, 12),
6312 + MTK_PIN_PUPD_SPEC_SR(106, 0xe20, 14, 13, 12),
6313 + MTK_PIN_PUPD_SPEC_SR(107, 0xe30, 2, 1, 0),
6314 + MTK_PIN_PUPD_SPEC_SR(108, 0xe30, 6, 5, 4),
6315 + MTK_PIN_PUPD_SPEC_SR(109, 0xe30, 10, 9, 8),
6316 + MTK_PIN_PUPD_SPEC_SR(110, 0xe10, 14, 13, 12),
6317 + MTK_PIN_PUPD_SPEC_SR(111, 0xe10, 10, 9, 8),
6318 + MTK_PIN_PUPD_SPEC_SR(112, 0xe10, 6, 5, 4),
6319 + MTK_PIN_PUPD_SPEC_SR(113, 0xe10, 2, 1, 0),
6320 + MTK_PIN_PUPD_SPEC_SR(114, 0xe20, 10, 9, 8),
6321 + MTK_PIN_PUPD_SPEC_SR(115, 0xe20, 2, 1, 0),
6322 + MTK_PIN_PUPD_SPEC_SR(116, 0xe20, 6, 5, 4),
6323 + MTK_PIN_PUPD_SPEC_SR(117, 0xe00, 14, 13, 12),
6324 + MTK_PIN_PUPD_SPEC_SR(118, 0xe00, 10, 9, 8),
6325 + MTK_PIN_PUPD_SPEC_SR(119, 0xe00, 6, 5, 4),
6326 + MTK_PIN_PUPD_SPEC_SR(120, 0xe00, 2, 1, 0),
6327 +};
6328 +
6329 +static int mt8516_spec_pull_set(struct regmap *regmap, unsigned int pin,
6330 + unsigned char align, bool isup, unsigned int r1r0)
6331 +{
6332 + return mtk_pctrl_spec_pull_set_samereg(regmap, mt8516_spec_pupd,
6333 + ARRAY_SIZE(mt8516_spec_pupd), pin, align, isup, r1r0);
6334 +}
6335 +
6336 +static const struct mtk_pin_ies_smt_set mt8516_ies_set[] = {
6337 + MTK_PIN_IES_SMT_SPEC(0, 6, 0x900, 2),
6338 + MTK_PIN_IES_SMT_SPEC(7, 10, 0x900, 3),
6339 + MTK_PIN_IES_SMT_SPEC(11, 13, 0x900, 12),
6340 + MTK_PIN_IES_SMT_SPEC(14, 17, 0x900, 13),
6341 + MTK_PIN_IES_SMT_SPEC(18, 20, 0x910, 10),
6342 + MTK_PIN_IES_SMT_SPEC(21, 23, 0x900, 13),
6343 + MTK_PIN_IES_SMT_SPEC(24, 25, 0x900, 12),
6344 + MTK_PIN_IES_SMT_SPEC(26, 30, 0x900, 0),
6345 + MTK_PIN_IES_SMT_SPEC(31, 33, 0x900, 1),
6346 + MTK_PIN_IES_SMT_SPEC(34, 39, 0x900, 2),
6347 + MTK_PIN_IES_SMT_SPEC(40, 40, 0x910, 11),
6348 + MTK_PIN_IES_SMT_SPEC(41, 43, 0x900, 10),
6349 + MTK_PIN_IES_SMT_SPEC(44, 47, 0x900, 11),
6350 + MTK_PIN_IES_SMT_SPEC(48, 51, 0x900, 14),
6351 + MTK_PIN_IES_SMT_SPEC(52, 53, 0x910, 0),
6352 + MTK_PIN_IES_SMT_SPEC(54, 54, 0x910, 2),
6353 + MTK_PIN_IES_SMT_SPEC(55, 57, 0x910, 4),
6354 + MTK_PIN_IES_SMT_SPEC(58, 59, 0x900, 15),
6355 + MTK_PIN_IES_SMT_SPEC(60, 61, 0x910, 1),
6356 + MTK_PIN_IES_SMT_SPEC(62, 65, 0x910, 5),
6357 + MTK_PIN_IES_SMT_SPEC(66, 67, 0x910, 6),
6358 + MTK_PIN_IES_SMT_SPEC(68, 68, 0x930, 2),
6359 + MTK_PIN_IES_SMT_SPEC(69, 69, 0x930, 1),
6360 + MTK_PIN_IES_SMT_SPEC(70, 70, 0x930, 6),
6361 + MTK_PIN_IES_SMT_SPEC(71, 71, 0x930, 5),
6362 + MTK_PIN_IES_SMT_SPEC(72, 72, 0x930, 4),
6363 + MTK_PIN_IES_SMT_SPEC(73, 73, 0x930, 3),
6364 + MTK_PIN_IES_SMT_SPEC(100, 103, 0x910, 7),
6365 + MTK_PIN_IES_SMT_SPEC(104, 104, 0x920, 12),
6366 + MTK_PIN_IES_SMT_SPEC(105, 105, 0x920, 11),
6367 + MTK_PIN_IES_SMT_SPEC(106, 106, 0x930, 0),
6368 + MTK_PIN_IES_SMT_SPEC(107, 107, 0x920, 15),
6369 + MTK_PIN_IES_SMT_SPEC(108, 108, 0x920, 14),
6370 + MTK_PIN_IES_SMT_SPEC(109, 109, 0x920, 13),
6371 + MTK_PIN_IES_SMT_SPEC(110, 110, 0x920, 9),
6372 + MTK_PIN_IES_SMT_SPEC(111, 111, 0x920, 8),
6373 + MTK_PIN_IES_SMT_SPEC(112, 112, 0x920, 7),
6374 + MTK_PIN_IES_SMT_SPEC(113, 113, 0x920, 6),
6375 + MTK_PIN_IES_SMT_SPEC(114, 114, 0x920, 10),
6376 + MTK_PIN_IES_SMT_SPEC(115, 115, 0x920, 1),
6377 + MTK_PIN_IES_SMT_SPEC(116, 116, 0x920, 0),
6378 + MTK_PIN_IES_SMT_SPEC(117, 117, 0x920, 5),
6379 + MTK_PIN_IES_SMT_SPEC(118, 118, 0x920, 4),
6380 + MTK_PIN_IES_SMT_SPEC(119, 119, 0x920, 3),
6381 + MTK_PIN_IES_SMT_SPEC(120, 120, 0x920, 2),
6382 + MTK_PIN_IES_SMT_SPEC(121, 124, 0x910, 9),
6383 +};
6384 +
6385 +static const struct mtk_pin_ies_smt_set mt8516_smt_set[] = {
6386 + MTK_PIN_IES_SMT_SPEC(0, 6, 0xA00, 2),
6387 + MTK_PIN_IES_SMT_SPEC(7, 10, 0xA00, 3),
6388 + MTK_PIN_IES_SMT_SPEC(11, 13, 0xA00, 12),
6389 + MTK_PIN_IES_SMT_SPEC(14, 17, 0xA00, 13),
6390 + MTK_PIN_IES_SMT_SPEC(18, 20, 0xA10, 10),
6391 + MTK_PIN_IES_SMT_SPEC(21, 23, 0xA00, 13),
6392 + MTK_PIN_IES_SMT_SPEC(24, 25, 0xA00, 12),
6393 + MTK_PIN_IES_SMT_SPEC(26, 30, 0xA00, 0),
6394 + MTK_PIN_IES_SMT_SPEC(31, 33, 0xA00, 1),
6395 + MTK_PIN_IES_SMT_SPEC(34, 39, 0xA900, 2),
6396 + MTK_PIN_IES_SMT_SPEC(40, 40, 0xA10, 11),
6397 + MTK_PIN_IES_SMT_SPEC(41, 43, 0xA00, 10),
6398 + MTK_PIN_IES_SMT_SPEC(44, 47, 0xA00, 11),
6399 + MTK_PIN_IES_SMT_SPEC(48, 51, 0xA00, 14),
6400 + MTK_PIN_IES_SMT_SPEC(52, 53, 0xA10, 0),
6401 + MTK_PIN_IES_SMT_SPEC(54, 54, 0xA10, 2),
6402 + MTK_PIN_IES_SMT_SPEC(55, 57, 0xA10, 4),
6403 + MTK_PIN_IES_SMT_SPEC(58, 59, 0xA00, 15),
6404 + MTK_PIN_IES_SMT_SPEC(60, 61, 0xA10, 1),
6405 + MTK_PIN_IES_SMT_SPEC(62, 65, 0xA10, 5),
6406 + MTK_PIN_IES_SMT_SPEC(66, 67, 0xA10, 6),
6407 + MTK_PIN_IES_SMT_SPEC(68, 68, 0xA30, 2),
6408 + MTK_PIN_IES_SMT_SPEC(69, 69, 0xA30, 1),
6409 + MTK_PIN_IES_SMT_SPEC(70, 70, 0xA30, 3),
6410 + MTK_PIN_IES_SMT_SPEC(71, 71, 0xA30, 4),
6411 + MTK_PIN_IES_SMT_SPEC(72, 72, 0xA30, 5),
6412 + MTK_PIN_IES_SMT_SPEC(73, 73, 0xA30, 6),
6413 +
6414 + MTK_PIN_IES_SMT_SPEC(100, 103, 0xA10, 7),
6415 + MTK_PIN_IES_SMT_SPEC(104, 104, 0xA20, 12),
6416 + MTK_PIN_IES_SMT_SPEC(105, 105, 0xA20, 11),
6417 + MTK_PIN_IES_SMT_SPEC(106, 106, 0xA30, 13),
6418 + MTK_PIN_IES_SMT_SPEC(107, 107, 0xA20, 14),
6419 + MTK_PIN_IES_SMT_SPEC(108, 108, 0xA20, 15),
6420 + MTK_PIN_IES_SMT_SPEC(109, 109, 0xA30, 0),
6421 + MTK_PIN_IES_SMT_SPEC(110, 110, 0xA20, 9),
6422 + MTK_PIN_IES_SMT_SPEC(111, 111, 0xA20, 8),
6423 + MTK_PIN_IES_SMT_SPEC(112, 112, 0xA20, 7),
6424 + MTK_PIN_IES_SMT_SPEC(113, 113, 0xA20, 6),
6425 + MTK_PIN_IES_SMT_SPEC(114, 114, 0xA20, 10),
6426 + MTK_PIN_IES_SMT_SPEC(115, 115, 0xA20, 1),
6427 + MTK_PIN_IES_SMT_SPEC(116, 116, 0xA20, 0),
6428 + MTK_PIN_IES_SMT_SPEC(117, 117, 0xA20, 5),
6429 + MTK_PIN_IES_SMT_SPEC(118, 118, 0xA20, 4),
6430 + MTK_PIN_IES_SMT_SPEC(119, 119, 0xA20, 3),
6431 + MTK_PIN_IES_SMT_SPEC(120, 120, 0xA20, 2),
6432 + MTK_PIN_IES_SMT_SPEC(121, 124, 0xA10, 9),
6433 +};
6434 +
6435 +static int mt8516_ies_smt_set(struct regmap *regmap, unsigned int pin,
6436 + unsigned char align, int value, enum pin_config_param arg)
6437 +{
6438 + if (arg == PIN_CONFIG_INPUT_ENABLE)
6439 + return mtk_pconf_spec_set_ies_smt_range(regmap, mt8516_ies_set,
6440 + ARRAY_SIZE(mt8516_ies_set), pin, align, value);
6441 + else if (arg == PIN_CONFIG_INPUT_SCHMITT_ENABLE)
6442 + return mtk_pconf_spec_set_ies_smt_range(regmap, mt8516_smt_set,
6443 + ARRAY_SIZE(mt8516_smt_set), pin, align, value);
6444 + return -EINVAL;
6445 +}
6446 +
6447 +static const struct mtk_pinctrl_devdata mt8516_pinctrl_data = {
6448 + .pins = mtk_pins_mt8516,
6449 + .npins = ARRAY_SIZE(mtk_pins_mt8516),
6450 + .grp_desc = mt8516_drv_grp,
6451 + .n_grp_cls = ARRAY_SIZE(mt8516_drv_grp),
6452 + .pin_drv_grp = mt8516_pin_drv,
6453 + .n_pin_drv_grps = ARRAY_SIZE(mt8516_pin_drv),
6454 + .spec_pull_set = mt8516_spec_pull_set,
6455 + .spec_ies_smt_set = mt8516_ies_smt_set,
6456 + .dir_offset = 0x0000,
6457 + .pullen_offset = 0x0500,
6458 + .pullsel_offset = 0x0600,
6459 + .dout_offset = 0x0100,
6460 + .din_offset = 0x0200,
6461 + .pinmux_offset = 0x0300,
6462 + .type1_start = 125,
6463 + .type1_end = 125,
6464 + .port_shf = 4,
6465 + .port_mask = 0xf,
6466 + .port_align = 4,
6467 + .eint_hw = {
6468 + .port_mask = 7,
6469 + .ports = 6,
6470 + .ap_num = 169,
6471 + .db_cnt = 64,
6472 + },
6473 +};
6474 +
6475 +static int mt8516_pinctrl_probe(struct platform_device *pdev)
6476 +{
6477 + return mtk_pctrl_init(pdev, &mt8516_pinctrl_data, NULL);
6478 +}
6479 +
6480 +static const struct of_device_id mt8516_pctrl_match[] = {
6481 + {
6482 + .compatible = "mediatek,mt8516-pinctrl",
6483 + },
6484 + {}
6485 +};
6486 +
6487 +MODULE_DEVICE_TABLE(of, mt8516_pctrl_match);
6488 +
6489 +static struct platform_driver mtk_pinctrl_driver = {
6490 + .probe = mt8516_pinctrl_probe,
6491 + .driver = {
6492 + .name = "mediatek-mt8516-pinctrl",
6493 + .of_match_table = mt8516_pctrl_match,
6494 + .pm = &mtk_eint_pm_ops,
6495 + },
6496 +};
6497 +
6498 +static int __init mtk_pinctrl_init(void)
6499 +{
6500 + return platform_driver_register(&mtk_pinctrl_driver);
6501 +}
6502 +arch_initcall(mtk_pinctrl_init);
6503 --- /dev/null
6504 +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c
6505 @@ -0,0 +1,725 @@
6506 +// SPDX-License-Identifier: GPL-2.0
6507 +/*
6508 + * Copyright (C) 2018 MediaTek Inc.
6509 + *
6510 + * Author: Sean Wang <sean.wang@mediatek.com>
6511 + *
6512 + */
6513 +
6514 +#include <linux/device.h>
6515 +#include <linux/err.h>
6516 +#include <linux/gpio/driver.h>
6517 +#include <linux/platform_device.h>
6518 +#include <linux/io.h>
6519 +#include <linux/of_irq.h>
6520 +
6521 +#include "mtk-eint.h"
6522 +#include "pinctrl-mtk-common-v2.h"
6523 +
6524 +/**
6525 + * struct mtk_drive_desc - the structure that holds the information
6526 + * of the driving current
6527 + * @min: the minimum current of this group
6528 + * @max: the maximum current of this group
6529 + * @step: the step current of this group
6530 + * @scal: the weight factor
6531 + *
6532 + * formula: output = ((input) / step - 1) * scal
6533 + */
6534 +struct mtk_drive_desc {
6535 + u8 min;
6536 + u8 max;
6537 + u8 step;
6538 + u8 scal;
6539 +};
6540 +
6541 +/* The groups of drive strength */
6542 +static const struct mtk_drive_desc mtk_drive[] = {
6543 + [DRV_GRP0] = { 4, 16, 4, 1 },
6544 + [DRV_GRP1] = { 4, 16, 4, 2 },
6545 + [DRV_GRP2] = { 2, 8, 2, 1 },
6546 + [DRV_GRP3] = { 2, 8, 2, 2 },
6547 + [DRV_GRP4] = { 2, 16, 2, 1 },
6548 +};
6549 +
6550 +static void mtk_w32(struct mtk_pinctrl *pctl, u8 i, u32 reg, u32 val)
6551 +{
6552 + writel_relaxed(val, pctl->base[i] + reg);
6553 +}
6554 +
6555 +static u32 mtk_r32(struct mtk_pinctrl *pctl, u8 i, u32 reg)
6556 +{
6557 + return readl_relaxed(pctl->base[i] + reg);
6558 +}
6559 +
6560 +void mtk_rmw(struct mtk_pinctrl *pctl, u8 i, u32 reg, u32 mask, u32 set)
6561 +{
6562 + u32 val;
6563 +
6564 + val = mtk_r32(pctl, i, reg);
6565 + val &= ~mask;
6566 + val |= set;
6567 + mtk_w32(pctl, i, reg, val);
6568 +}
6569 +
6570 +static int mtk_hw_pin_field_lookup(struct mtk_pinctrl *hw,
6571 + const struct mtk_pin_desc *desc,
6572 + int field, struct mtk_pin_field *pfd)
6573 +{
6574 + const struct mtk_pin_field_calc *c, *e;
6575 + const struct mtk_pin_reg_calc *rc;
6576 + u32 bits;
6577 +
6578 + if (hw->soc->reg_cal && hw->soc->reg_cal[field].range) {
6579 + rc = &hw->soc->reg_cal[field];
6580 + } else {
6581 + dev_dbg(hw->dev,
6582 + "Not support field %d for pin %d (%s)\n",
6583 + field, desc->number, desc->name);
6584 + return -ENOTSUPP;
6585 + }
6586 +
6587 + c = rc->range;
6588 + e = c + rc->nranges;
6589 +
6590 + while (c < e) {
6591 + if (desc->number >= c->s_pin && desc->number <= c->e_pin)
6592 + break;
6593 + c++;
6594 + }
6595 +
6596 + if (c >= e) {
6597 + dev_dbg(hw->dev, "Not support field %d for pin = %d (%s)\n",
6598 + field, desc->number, desc->name);
6599 + return -ENOTSUPP;
6600 + }
6601 +
6602 + if (c->i_base > hw->nbase - 1) {
6603 + dev_err(hw->dev,
6604 + "Invalid base for field %d for pin = %d (%s)\n",
6605 + field, desc->number, desc->name);
6606 + return -EINVAL;
6607 + }
6608 +
6609 + /* Calculated bits as the overall offset the pin is located at,
6610 + * if c->fixed is held, that determines the all the pins in the
6611 + * range use the same field with the s_pin.
6612 + */
6613 + bits = c->fixed ? c->s_bit : c->s_bit +
6614 + (desc->number - c->s_pin) * (c->x_bits);
6615 +
6616 + /* Fill pfd from bits. For example 32-bit register applied is assumed
6617 + * when c->sz_reg is equal to 32.
6618 + */
6619 + pfd->index = c->i_base;
6620 + pfd->offset = c->s_addr + c->x_addrs * (bits / c->sz_reg);
6621 + pfd->bitpos = bits % c->sz_reg;
6622 + pfd->mask = (1 << c->x_bits) - 1;
6623 +
6624 + /* pfd->next is used for indicating that bit wrapping-around happens
6625 + * which requires the manipulation for bit 0 starting in the next
6626 + * register to form the complete field read/write.
6627 + */
6628 + pfd->next = pfd->bitpos + c->x_bits > c->sz_reg ? c->x_addrs : 0;
6629 +
6630 + return 0;
6631 +}
6632 +
6633 +static int mtk_hw_pin_field_get(struct mtk_pinctrl *hw,
6634 + const struct mtk_pin_desc *desc,
6635 + int field, struct mtk_pin_field *pfd)
6636 +{
6637 + if (field < 0 || field >= PINCTRL_PIN_REG_MAX) {
6638 + dev_err(hw->dev, "Invalid Field %d\n", field);
6639 + return -EINVAL;
6640 + }
6641 +
6642 + return mtk_hw_pin_field_lookup(hw, desc, field, pfd);
6643 +}
6644 +
6645 +static void mtk_hw_bits_part(struct mtk_pin_field *pf, int *h, int *l)
6646 +{
6647 + *l = 32 - pf->bitpos;
6648 + *h = get_count_order(pf->mask) - *l;
6649 +}
6650 +
6651 +static void mtk_hw_write_cross_field(struct mtk_pinctrl *hw,
6652 + struct mtk_pin_field *pf, int value)
6653 +{
6654 + int nbits_l, nbits_h;
6655 +
6656 + mtk_hw_bits_part(pf, &nbits_h, &nbits_l);
6657 +
6658 + mtk_rmw(hw, pf->index, pf->offset, pf->mask << pf->bitpos,
6659 + (value & pf->mask) << pf->bitpos);
6660 +
6661 + mtk_rmw(hw, pf->index, pf->offset + pf->next, BIT(nbits_h) - 1,
6662 + (value & pf->mask) >> nbits_l);
6663 +}
6664 +
6665 +static void mtk_hw_read_cross_field(struct mtk_pinctrl *hw,
6666 + struct mtk_pin_field *pf, int *value)
6667 +{
6668 + int nbits_l, nbits_h, h, l;
6669 +
6670 + mtk_hw_bits_part(pf, &nbits_h, &nbits_l);
6671 +
6672 + l = (mtk_r32(hw, pf->index, pf->offset)
6673 + >> pf->bitpos) & (BIT(nbits_l) - 1);
6674 + h = (mtk_r32(hw, pf->index, pf->offset + pf->next))
6675 + & (BIT(nbits_h) - 1);
6676 +
6677 + *value = (h << nbits_l) | l;
6678 +}
6679 +
6680 +int mtk_hw_set_value(struct mtk_pinctrl *hw, const struct mtk_pin_desc *desc,
6681 + int field, int value)
6682 +{
6683 + struct mtk_pin_field pf;
6684 + int err;
6685 +
6686 + err = mtk_hw_pin_field_get(hw, desc, field, &pf);
6687 + if (err)
6688 + return err;
6689 +
6690 + if (!pf.next)
6691 + mtk_rmw(hw, pf.index, pf.offset, pf.mask << pf.bitpos,
6692 + (value & pf.mask) << pf.bitpos);
6693 + else
6694 + mtk_hw_write_cross_field(hw, &pf, value);
6695 +
6696 + return 0;
6697 +}
6698 +
6699 +int mtk_hw_get_value(struct mtk_pinctrl *hw, const struct mtk_pin_desc *desc,
6700 + int field, int *value)
6701 +{
6702 + struct mtk_pin_field pf;
6703 + int err;
6704 +
6705 + err = mtk_hw_pin_field_get(hw, desc, field, &pf);
6706 + if (err)
6707 + return err;
6708 +
6709 + if (!pf.next)
6710 + *value = (mtk_r32(hw, pf.index, pf.offset)
6711 + >> pf.bitpos) & pf.mask;
6712 + else
6713 + mtk_hw_read_cross_field(hw, &pf, value);
6714 +
6715 + return 0;
6716 +}
6717 +
6718 +static int mtk_xt_find_eint_num(struct mtk_pinctrl *hw, unsigned long eint_n)
6719 +{
6720 + const struct mtk_pin_desc *desc;
6721 + int i = 0;
6722 +
6723 + desc = (const struct mtk_pin_desc *)hw->soc->pins;
6724 +
6725 + while (i < hw->soc->npins) {
6726 + if (desc[i].eint.eint_n == eint_n)
6727 + return desc[i].number;
6728 + i++;
6729 + }
6730 +
6731 + return EINT_NA;
6732 +}
6733 +
6734 +static int mtk_xt_get_gpio_n(void *data, unsigned long eint_n,
6735 + unsigned int *gpio_n,
6736 + struct gpio_chip **gpio_chip)
6737 +{
6738 + struct mtk_pinctrl *hw = (struct mtk_pinctrl *)data;
6739 + const struct mtk_pin_desc *desc;
6740 +
6741 + desc = (const struct mtk_pin_desc *)hw->soc->pins;
6742 + *gpio_chip = &hw->chip;
6743 +
6744 + /* Be greedy to guess first gpio_n is equal to eint_n */
6745 + if (desc[eint_n].eint.eint_n == eint_n)
6746 + *gpio_n = eint_n;
6747 + else
6748 + *gpio_n = mtk_xt_find_eint_num(hw, eint_n);
6749 +
6750 + return *gpio_n == EINT_NA ? -EINVAL : 0;
6751 +}
6752 +
6753 +static int mtk_xt_get_gpio_state(void *data, unsigned long eint_n)
6754 +{
6755 + struct mtk_pinctrl *hw = (struct mtk_pinctrl *)data;
6756 + const struct mtk_pin_desc *desc;
6757 + struct gpio_chip *gpio_chip;
6758 + unsigned int gpio_n;
6759 + int value, err;
6760 +
6761 + err = mtk_xt_get_gpio_n(hw, eint_n, &gpio_n, &gpio_chip);
6762 + if (err)
6763 + return err;
6764 +
6765 + desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio_n];
6766 +
6767 + err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DI, &value);
6768 + if (err)
6769 + return err;
6770 +
6771 + return !!value;
6772 +}
6773 +
6774 +static int mtk_xt_set_gpio_as_eint(void *data, unsigned long eint_n)
6775 +{
6776 + struct mtk_pinctrl *hw = (struct mtk_pinctrl *)data;
6777 + const struct mtk_pin_desc *desc;
6778 + struct gpio_chip *gpio_chip;
6779 + unsigned int gpio_n;
6780 + int err;
6781 +
6782 + err = mtk_xt_get_gpio_n(hw, eint_n, &gpio_n, &gpio_chip);
6783 + if (err)
6784 + return err;
6785 +
6786 + desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio_n];
6787 +
6788 + err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_MODE,
6789 + desc->eint.eint_m);
6790 + if (err)
6791 + return err;
6792 +
6793 + err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR, MTK_INPUT);
6794 + if (err)
6795 + return err;
6796 +
6797 + err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_SMT, MTK_ENABLE);
6798 + /* SMT is supposed to be supported by every real GPIO and doesn't
6799 + * support virtual GPIOs, so the extra condition err != -ENOTSUPP
6800 + * is just for adding EINT support to these virtual GPIOs. It should
6801 + * add an extra flag in the pin descriptor when more pins with
6802 + * distinctive characteristic come out.
6803 + */
6804 + if (err && err != -ENOTSUPP)
6805 + return err;
6806 +
6807 + return 0;
6808 +}
6809 +
6810 +static const struct mtk_eint_xt mtk_eint_xt = {
6811 + .get_gpio_n = mtk_xt_get_gpio_n,
6812 + .get_gpio_state = mtk_xt_get_gpio_state,
6813 + .set_gpio_as_eint = mtk_xt_set_gpio_as_eint,
6814 +};
6815 +
6816 +int mtk_build_eint(struct mtk_pinctrl *hw, struct platform_device *pdev)
6817 +{
6818 + struct device_node *np = pdev->dev.of_node;
6819 + struct resource *res;
6820 +
6821 + if (!IS_ENABLED(CONFIG_EINT_MTK))
6822 + return 0;
6823 +
6824 + if (!of_property_read_bool(np, "interrupt-controller"))
6825 + return -ENODEV;
6826 +
6827 + hw->eint = devm_kzalloc(hw->dev, sizeof(*hw->eint), GFP_KERNEL);
6828 + if (!hw->eint)
6829 + return -ENOMEM;
6830 +
6831 + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "eint");
6832 + if (!res) {
6833 + dev_err(&pdev->dev, "Unable to get eint resource\n");
6834 + return -ENODEV;
6835 + }
6836 +
6837 + hw->eint->base = devm_ioremap_resource(&pdev->dev, res);
6838 + if (IS_ERR(hw->eint->base))
6839 + return PTR_ERR(hw->eint->base);
6840 +
6841 + hw->eint->irq = irq_of_parse_and_map(np, 0);
6842 + if (!hw->eint->irq)
6843 + return -EINVAL;
6844 +
6845 + if (!hw->soc->eint_hw)
6846 + return -ENODEV;
6847 +
6848 + hw->eint->dev = &pdev->dev;
6849 + hw->eint->hw = hw->soc->eint_hw;
6850 + hw->eint->pctl = hw;
6851 + hw->eint->gpio_xlate = &mtk_eint_xt;
6852 +
6853 + return mtk_eint_do_init(hw->eint);
6854 +}
6855 +
6856 +/* Revision 0 */
6857 +int mtk_pinconf_bias_disable_set(struct mtk_pinctrl *hw,
6858 + const struct mtk_pin_desc *desc)
6859 +{
6860 + int err;
6861 +
6862 + err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PU,
6863 + MTK_DISABLE);
6864 + if (err)
6865 + return err;
6866 +
6867 + err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PD,
6868 + MTK_DISABLE);
6869 + if (err)
6870 + return err;
6871 +
6872 + return 0;
6873 +}
6874 +
6875 +int mtk_pinconf_bias_disable_get(struct mtk_pinctrl *hw,
6876 + const struct mtk_pin_desc *desc, int *res)
6877 +{
6878 + int v, v2;
6879 + int err;
6880 +
6881 + err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PU, &v);
6882 + if (err)
6883 + return err;
6884 +
6885 + err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PD, &v2);
6886 + if (err)
6887 + return err;
6888 +
6889 + if (v == MTK_ENABLE || v2 == MTK_ENABLE)
6890 + return -EINVAL;
6891 +
6892 + *res = 1;
6893 +
6894 + return 0;
6895 +}
6896 +
6897 +int mtk_pinconf_bias_set(struct mtk_pinctrl *hw,
6898 + const struct mtk_pin_desc *desc, bool pullup)
6899 +{
6900 + int err, arg;
6901 +
6902 + arg = pullup ? 1 : 2;
6903 +
6904 + err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PU, arg & 1);
6905 + if (err)
6906 + return err;
6907 +
6908 + err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PD,
6909 + !!(arg & 2));
6910 + if (err)
6911 + return err;
6912 +
6913 + return 0;
6914 +}
6915 +
6916 +int mtk_pinconf_bias_get(struct mtk_pinctrl *hw,
6917 + const struct mtk_pin_desc *desc, bool pullup, int *res)
6918 +{
6919 + int reg, err, v;
6920 +
6921 + reg = pullup ? PINCTRL_PIN_REG_PU : PINCTRL_PIN_REG_PD;
6922 +
6923 + err = mtk_hw_get_value(hw, desc, reg, &v);
6924 + if (err)
6925 + return err;
6926 +
6927 + if (!v)
6928 + return -EINVAL;
6929 +
6930 + *res = 1;
6931 +
6932 + return 0;
6933 +}
6934 +
6935 +/* Revision 1 */
6936 +int mtk_pinconf_bias_disable_set_rev1(struct mtk_pinctrl *hw,
6937 + const struct mtk_pin_desc *desc)
6938 +{
6939 + int err;
6940 +
6941 + err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PULLEN,
6942 + MTK_DISABLE);
6943 + if (err)
6944 + return err;
6945 +
6946 + return 0;
6947 +}
6948 +
6949 +int mtk_pinconf_bias_disable_get_rev1(struct mtk_pinctrl *hw,
6950 + const struct mtk_pin_desc *desc, int *res)
6951 +{
6952 + int v, err;
6953 +
6954 + err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PULLEN, &v);
6955 + if (err)
6956 + return err;
6957 +
6958 + if (v == MTK_ENABLE)
6959 + return -EINVAL;
6960 +
6961 + *res = 1;
6962 +
6963 + return 0;
6964 +}
6965 +
6966 +int mtk_pinconf_bias_set_rev1(struct mtk_pinctrl *hw,
6967 + const struct mtk_pin_desc *desc, bool pullup)
6968 +{
6969 + int err, arg;
6970 +
6971 + arg = pullup ? MTK_PULLUP : MTK_PULLDOWN;
6972 +
6973 + err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PULLEN,
6974 + MTK_ENABLE);
6975 + if (err)
6976 + return err;
6977 +
6978 + err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PULLSEL, arg);
6979 + if (err)
6980 + return err;
6981 +
6982 + return 0;
6983 +}
6984 +
6985 +int mtk_pinconf_bias_get_rev1(struct mtk_pinctrl *hw,
6986 + const struct mtk_pin_desc *desc, bool pullup,
6987 + int *res)
6988 +{
6989 + int err, v;
6990 +
6991 + err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PULLEN, &v);
6992 + if (err)
6993 + return err;
6994 +
6995 + if (v == MTK_DISABLE)
6996 + return -EINVAL;
6997 +
6998 + err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PULLSEL, &v);
6999 + if (err)
7000 + return err;
7001 +
7002 + if (pullup ^ (v == MTK_PULLUP))
7003 + return -EINVAL;
7004 +
7005 + *res = 1;
7006 +
7007 + return 0;
7008 +}
7009 +
7010 +/* Revision 0 */
7011 +int mtk_pinconf_drive_set(struct mtk_pinctrl *hw,
7012 + const struct mtk_pin_desc *desc, u32 arg)
7013 +{
7014 + const struct mtk_drive_desc *tb;
7015 + int err = -ENOTSUPP;
7016 +
7017 + tb = &mtk_drive[desc->drv_n];
7018 + /* 4mA when (e8, e4) = (0, 0)
7019 + * 8mA when (e8, e4) = (0, 1)
7020 + * 12mA when (e8, e4) = (1, 0)
7021 + * 16mA when (e8, e4) = (1, 1)
7022 + */
7023 + if ((arg >= tb->min && arg <= tb->max) && !(arg % tb->step)) {
7024 + arg = (arg / tb->step - 1) * tb->scal;
7025 + err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_E4,
7026 + arg & 0x1);
7027 + if (err)
7028 + return err;
7029 +
7030 + err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_E8,
7031 + (arg & 0x2) >> 1);
7032 + if (err)
7033 + return err;
7034 + }
7035 +
7036 + return err;
7037 +}
7038 +
7039 +int mtk_pinconf_drive_get(struct mtk_pinctrl *hw,
7040 + const struct mtk_pin_desc *desc, int *val)
7041 +{
7042 + const struct mtk_drive_desc *tb;
7043 + int err, val1, val2;
7044 +
7045 + tb = &mtk_drive[desc->drv_n];
7046 +
7047 + err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_E4, &val1);
7048 + if (err)
7049 + return err;
7050 +
7051 + err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_E8, &val2);
7052 + if (err)
7053 + return err;
7054 +
7055 + /* 4mA when (e8, e4) = (0, 0); 8mA when (e8, e4) = (0, 1)
7056 + * 12mA when (e8, e4) = (1, 0); 16mA when (e8, e4) = (1, 1)
7057 + */
7058 + *val = (((val2 << 1) + val1) / tb->scal + 1) * tb->step;
7059 +
7060 + return 0;
7061 +}
7062 +
7063 +/* Revision 1 */
7064 +int mtk_pinconf_drive_set_rev1(struct mtk_pinctrl *hw,
7065 + const struct mtk_pin_desc *desc, u32 arg)
7066 +{
7067 + const struct mtk_drive_desc *tb;
7068 + int err = -ENOTSUPP;
7069 +
7070 + tb = &mtk_drive[desc->drv_n];
7071 +
7072 + if ((arg >= tb->min && arg <= tb->max) && !(arg % tb->step)) {
7073 + arg = (arg / tb->step - 1) * tb->scal;
7074 +
7075 + err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DRV,
7076 + arg);
7077 + if (err)
7078 + return err;
7079 + }
7080 +
7081 + return err;
7082 +}
7083 +
7084 +int mtk_pinconf_drive_get_rev1(struct mtk_pinctrl *hw,
7085 + const struct mtk_pin_desc *desc, int *val)
7086 +{
7087 + const struct mtk_drive_desc *tb;
7088 + int err, val1;
7089 +
7090 + tb = &mtk_drive[desc->drv_n];
7091 +
7092 + err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DRV, &val1);
7093 + if (err)
7094 + return err;
7095 +
7096 + *val = ((val1 & 0x7) / tb->scal + 1) * tb->step;
7097 +
7098 + return 0;
7099 +}
7100 +
7101 +int mtk_pinconf_adv_pull_set(struct mtk_pinctrl *hw,
7102 + const struct mtk_pin_desc *desc, bool pullup,
7103 + u32 arg)
7104 +{
7105 + int err;
7106 +
7107 + /* 10K off & 50K (75K) off, when (R0, R1) = (0, 0);
7108 + * 10K off & 50K (75K) on, when (R0, R1) = (0, 1);
7109 + * 10K on & 50K (75K) off, when (R0, R1) = (1, 0);
7110 + * 10K on & 50K (75K) on, when (R0, R1) = (1, 1)
7111 + */
7112 + err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_R0, arg & 1);
7113 + if (err)
7114 + return 0;
7115 +
7116 + err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_R1,
7117 + !!(arg & 2));
7118 + if (err)
7119 + return 0;
7120 +
7121 + arg = pullup ? 0 : 1;
7122 +
7123 + err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PUPD, arg);
7124 +
7125 + /* If PUPD register is not supported for that pin, let's fallback to
7126 + * general bias control.
7127 + */
7128 + if (err == -ENOTSUPP) {
7129 + if (hw->soc->bias_set) {
7130 + err = hw->soc->bias_set(hw, desc, pullup);
7131 + if (err)
7132 + return err;
7133 + } else {
7134 + return -ENOTSUPP;
7135 + }
7136 + }
7137 +
7138 + return err;
7139 +}
7140 +
7141 +int mtk_pinconf_adv_pull_get(struct mtk_pinctrl *hw,
7142 + const struct mtk_pin_desc *desc, bool pullup,
7143 + u32 *val)
7144 +{
7145 + u32 t, t2;
7146 + int err;
7147 +
7148 + err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PUPD, &t);
7149 +
7150 + /* If PUPD register is not supported for that pin, let's fallback to
7151 + * general bias control.
7152 + */
7153 + if (err == -ENOTSUPP) {
7154 + if (hw->soc->bias_get) {
7155 + err = hw->soc->bias_get(hw, desc, pullup, val);
7156 + if (err)
7157 + return err;
7158 + } else {
7159 + return -ENOTSUPP;
7160 + }
7161 + } else {
7162 + /* t == 0 supposes PULLUP for the customized PULL setup */
7163 + if (err)
7164 + return err;
7165 +
7166 + if (pullup ^ !t)
7167 + return -EINVAL;
7168 + }
7169 +
7170 + err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_R0, &t);
7171 + if (err)
7172 + return err;
7173 +
7174 + err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_R1, &t2);
7175 + if (err)
7176 + return err;
7177 +
7178 + *val = (t | t2 << 1) & 0x7;
7179 +
7180 + return 0;
7181 +}
7182 +
7183 +int mtk_pinconf_adv_drive_set(struct mtk_pinctrl *hw,
7184 + const struct mtk_pin_desc *desc, u32 arg)
7185 +{
7186 + int err;
7187 + int en = arg & 1;
7188 + int e0 = !!(arg & 2);
7189 + int e1 = !!(arg & 4);
7190 +
7191 + err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DRV_EN, en);
7192 + if (err)
7193 + return err;
7194 +
7195 + if (!en)
7196 + return err;
7197 +
7198 + err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DRV_E0, e0);
7199 + if (err)
7200 + return err;
7201 +
7202 + err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DRV_E1, e1);
7203 + if (err)
7204 + return err;
7205 +
7206 + return err;
7207 +}
7208 +
7209 +int mtk_pinconf_adv_drive_get(struct mtk_pinctrl *hw,
7210 + const struct mtk_pin_desc *desc, u32 *val)
7211 +{
7212 + u32 en, e0, e1;
7213 + int err;
7214 +
7215 + err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DRV_EN, &en);
7216 + if (err)
7217 + return err;
7218 +
7219 + err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DRV_E0, &e0);
7220 + if (err)
7221 + return err;
7222 +
7223 + err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DRV_E1, &e1);
7224 + if (err)
7225 + return err;
7226 +
7227 + *val = (en | e0 << 1 | e1 << 2) & 0x7;
7228 +
7229 + return 0;
7230 +}
7231 --- /dev/null
7232 +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h
7233 @@ -0,0 +1,302 @@
7234 +/* SPDX-License-Identifier: GPL-2.0 */
7235 +/*
7236 + * Copyright (C) 2018 MediaTek Inc.
7237 + *
7238 + * Author: Sean Wang <sean.wang@mediatek.com>
7239 + *
7240 + */
7241 +
7242 +#ifndef __PINCTRL_MTK_COMMON_V2_H
7243 +#define __PINCTRL_MTK_COMMON_V2_H
7244 +
7245 +#include <linux/gpio/driver.h>
7246 +
7247 +#define MTK_INPUT 0
7248 +#define MTK_OUTPUT 1
7249 +#define MTK_DISABLE 0
7250 +#define MTK_ENABLE 1
7251 +#define MTK_PULLDOWN 0
7252 +#define MTK_PULLUP 1
7253 +
7254 +#define EINT_NA U16_MAX
7255 +#define NO_EINT_SUPPORT EINT_NA
7256 +
7257 +#define PIN_FIELD_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, \
7258 + _s_bit, _x_bits, _sz_reg, _fixed) { \
7259 + .s_pin = _s_pin, \
7260 + .e_pin = _e_pin, \
7261 + .i_base = _i_base, \
7262 + .s_addr = _s_addr, \
7263 + .x_addrs = _x_addrs, \
7264 + .s_bit = _s_bit, \
7265 + .x_bits = _x_bits, \
7266 + .sz_reg = _sz_reg, \
7267 + .fixed = _fixed, \
7268 + }
7269 +
7270 +#define PIN_FIELD(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits) \
7271 + PIN_FIELD_CALC(_s_pin, _e_pin, 0, _s_addr, _x_addrs, _s_bit, \
7272 + _x_bits, 32, 0)
7273 +
7274 +#define PINS_FIELD(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits) \
7275 + PIN_FIELD_CALC(_s_pin, _e_pin, 0, _s_addr, _x_addrs, _s_bit, \
7276 + _x_bits, 32, 1)
7277 +
7278 +/* List these attributes which could be modified for the pin */
7279 +enum {
7280 + PINCTRL_PIN_REG_MODE,
7281 + PINCTRL_PIN_REG_DIR,
7282 + PINCTRL_PIN_REG_DI,
7283 + PINCTRL_PIN_REG_DO,
7284 + PINCTRL_PIN_REG_SR,
7285 + PINCTRL_PIN_REG_SMT,
7286 + PINCTRL_PIN_REG_PD,
7287 + PINCTRL_PIN_REG_PU,
7288 + PINCTRL_PIN_REG_E4,
7289 + PINCTRL_PIN_REG_E8,
7290 + PINCTRL_PIN_REG_TDSEL,
7291 + PINCTRL_PIN_REG_RDSEL,
7292 + PINCTRL_PIN_REG_DRV,
7293 + PINCTRL_PIN_REG_PUPD,
7294 + PINCTRL_PIN_REG_R0,
7295 + PINCTRL_PIN_REG_R1,
7296 + PINCTRL_PIN_REG_IES,
7297 + PINCTRL_PIN_REG_PULLEN,
7298 + PINCTRL_PIN_REG_PULLSEL,
7299 + PINCTRL_PIN_REG_DRV_EN,
7300 + PINCTRL_PIN_REG_DRV_E0,
7301 + PINCTRL_PIN_REG_DRV_E1,
7302 + PINCTRL_PIN_REG_MAX,
7303 +};
7304 +
7305 +/* Group the pins by the driving current */
7306 +enum {
7307 + DRV_FIXED,
7308 + DRV_GRP0,
7309 + DRV_GRP1,
7310 + DRV_GRP2,
7311 + DRV_GRP3,
7312 + DRV_GRP4,
7313 + DRV_GRP_MAX,
7314 +};
7315 +
7316 +static const char * const mtk_default_register_base_names[] = {
7317 + "base",
7318 +};
7319 +
7320 +/* struct mtk_pin_field - the structure that holds the information of the field
7321 + * used to describe the attribute for the pin
7322 + * @base: the index pointing to the entry in base address list
7323 + * @offset: the register offset relative to the base address
7324 + * @mask: the mask used to filter out the field from the register
7325 + * @bitpos: the start bit relative to the register
7326 + * @next: the indication that the field would be extended to the
7327 + next register
7328 + */
7329 +struct mtk_pin_field {
7330 + u8 index;
7331 + u32 offset;
7332 + u32 mask;
7333 + u8 bitpos;
7334 + u8 next;
7335 +};
7336 +
7337 +/* struct mtk_pin_field_calc - the structure that holds the range providing
7338 + * the guide used to look up the relevant field
7339 + * @s_pin: the start pin within the range
7340 + * @e_pin: the end pin within the range
7341 + * @i_base: the index pointing to the entry in base address list
7342 + * @s_addr: the start address for the range
7343 + * @x_addrs: the address distance between two consecutive registers
7344 + * within the range
7345 + * @s_bit: the start bit for the first register within the range
7346 + * @x_bits: the bit distance between two consecutive pins within
7347 + * the range
7348 + * @sz_reg: the size of bits in a register
7349 + * @fixed: the consecutive pins share the same bits with the 1st
7350 + * pin
7351 + */
7352 +struct mtk_pin_field_calc {
7353 + u16 s_pin;
7354 + u16 e_pin;
7355 + u8 i_base;
7356 + u32 s_addr;
7357 + u8 x_addrs;
7358 + u8 s_bit;
7359 + u8 x_bits;
7360 + u8 sz_reg;
7361 + u8 fixed;
7362 +};
7363 +
7364 +/* struct mtk_pin_reg_calc - the structure that holds all ranges used to
7365 + * determine which register the pin would make use of
7366 + * for certain pin attribute.
7367 + * @range: the start address for the range
7368 + * @nranges: the number of items in the range
7369 + */
7370 +struct mtk_pin_reg_calc {
7371 + const struct mtk_pin_field_calc *range;
7372 + unsigned int nranges;
7373 +};
7374 +
7375 +/**
7376 + * struct mtk_func_desc - the structure that providing information
7377 + * all the funcs for this pin
7378 + * @name: the name of function
7379 + * @muxval: the mux to the function
7380 + */
7381 +struct mtk_func_desc {
7382 + const char *name;
7383 + u8 muxval;
7384 +};
7385 +
7386 +/**
7387 + * struct mtk_eint_desc - the structure that providing information
7388 + * for eint data per pin
7389 + * @eint_m: the eint mux for this pin
7390 + * @eitn_n: the eint number for this pin
7391 + */
7392 +struct mtk_eint_desc {
7393 + u16 eint_m;
7394 + u16 eint_n;
7395 +};
7396 +
7397 +/**
7398 + * struct mtk_pin_desc - the structure that providing information
7399 + * for each pin of chips
7400 + * @number: unique pin number from the global pin number space
7401 + * @name: name for this pin
7402 + * @eint: the eint data for this pin
7403 + * @drv_n: the index with the driving group
7404 + * @funcs: all available functions for this pins (only used in
7405 + * those drivers compatible to pinctrl-mtk-common.c-like
7406 + * ones)
7407 + */
7408 +struct mtk_pin_desc {
7409 + unsigned int number;
7410 + const char *name;
7411 + struct mtk_eint_desc eint;
7412 + u8 drv_n;
7413 + struct mtk_func_desc *funcs;
7414 +};
7415 +
7416 +struct mtk_pinctrl_group {
7417 + const char *name;
7418 + unsigned long config;
7419 + unsigned pin;
7420 +};
7421 +
7422 +struct mtk_pinctrl;
7423 +
7424 +/* struct mtk_pin_soc - the structure that holds SoC-specific data */
7425 +struct mtk_pin_soc {
7426 + const struct mtk_pin_reg_calc *reg_cal;
7427 + const struct mtk_pin_desc *pins;
7428 + unsigned int npins;
7429 + const struct group_desc *grps;
7430 + unsigned int ngrps;
7431 + const struct function_desc *funcs;
7432 + unsigned int nfuncs;
7433 + const struct mtk_eint_regs *eint_regs;
7434 + const struct mtk_eint_hw *eint_hw;
7435 +
7436 + /* Specific parameters per SoC */
7437 + u8 gpio_m;
7438 + bool ies_present;
7439 + const char * const *base_names;
7440 + unsigned int nbase_names;
7441 +
7442 + /* Specific pinconfig operations */
7443 + int (*bias_disable_set)(struct mtk_pinctrl *hw,
7444 + const struct mtk_pin_desc *desc);
7445 + int (*bias_disable_get)(struct mtk_pinctrl *hw,
7446 + const struct mtk_pin_desc *desc, int *res);
7447 + int (*bias_set)(struct mtk_pinctrl *hw,
7448 + const struct mtk_pin_desc *desc, bool pullup);
7449 + int (*bias_get)(struct mtk_pinctrl *hw,
7450 + const struct mtk_pin_desc *desc, bool pullup, int *res);
7451 +
7452 + int (*drive_set)(struct mtk_pinctrl *hw,
7453 + const struct mtk_pin_desc *desc, u32 arg);
7454 + int (*drive_get)(struct mtk_pinctrl *hw,
7455 + const struct mtk_pin_desc *desc, int *val);
7456 +
7457 + int (*adv_pull_set)(struct mtk_pinctrl *hw,
7458 + const struct mtk_pin_desc *desc, bool pullup,
7459 + u32 arg);
7460 + int (*adv_pull_get)(struct mtk_pinctrl *hw,
7461 + const struct mtk_pin_desc *desc, bool pullup,
7462 + u32 *val);
7463 + int (*adv_drive_set)(struct mtk_pinctrl *hw,
7464 + const struct mtk_pin_desc *desc, u32 arg);
7465 + int (*adv_drive_get)(struct mtk_pinctrl *hw,
7466 + const struct mtk_pin_desc *desc, u32 *val);
7467 +
7468 + /* Specific driver data */
7469 + void *driver_data;
7470 +};
7471 +
7472 +struct mtk_pinctrl {
7473 + struct pinctrl_dev *pctrl;
7474 + void __iomem **base;
7475 + u8 nbase;
7476 + struct device *dev;
7477 + struct gpio_chip chip;
7478 + const struct mtk_pin_soc *soc;
7479 + struct mtk_eint *eint;
7480 + struct mtk_pinctrl_group *groups;
7481 + const char **grp_names;
7482 +};
7483 +
7484 +void mtk_rmw(struct mtk_pinctrl *pctl, u8 i, u32 reg, u32 mask, u32 set);
7485 +
7486 +int mtk_hw_set_value(struct mtk_pinctrl *hw, const struct mtk_pin_desc *desc,
7487 + int field, int value);
7488 +int mtk_hw_get_value(struct mtk_pinctrl *hw, const struct mtk_pin_desc *desc,
7489 + int field, int *value);
7490 +
7491 +int mtk_build_eint(struct mtk_pinctrl *hw, struct platform_device *pdev);
7492 +
7493 +int mtk_pinconf_bias_disable_set(struct mtk_pinctrl *hw,
7494 + const struct mtk_pin_desc *desc);
7495 +int mtk_pinconf_bias_disable_get(struct mtk_pinctrl *hw,
7496 + const struct mtk_pin_desc *desc, int *res);
7497 +int mtk_pinconf_bias_set(struct mtk_pinctrl *hw,
7498 + const struct mtk_pin_desc *desc, bool pullup);
7499 +int mtk_pinconf_bias_get(struct mtk_pinctrl *hw,
7500 + const struct mtk_pin_desc *desc, bool pullup,
7501 + int *res);
7502 +
7503 +int mtk_pinconf_bias_disable_set_rev1(struct mtk_pinctrl *hw,
7504 + const struct mtk_pin_desc *desc);
7505 +int mtk_pinconf_bias_disable_get_rev1(struct mtk_pinctrl *hw,
7506 + const struct mtk_pin_desc *desc,
7507 + int *res);
7508 +int mtk_pinconf_bias_set_rev1(struct mtk_pinctrl *hw,
7509 + const struct mtk_pin_desc *desc, bool pullup);
7510 +int mtk_pinconf_bias_get_rev1(struct mtk_pinctrl *hw,
7511 + const struct mtk_pin_desc *desc, bool pullup,
7512 + int *res);
7513 +
7514 +int mtk_pinconf_drive_set(struct mtk_pinctrl *hw,
7515 + const struct mtk_pin_desc *desc, u32 arg);
7516 +int mtk_pinconf_drive_get(struct mtk_pinctrl *hw,
7517 + const struct mtk_pin_desc *desc, int *val);
7518 +
7519 +int mtk_pinconf_drive_set_rev1(struct mtk_pinctrl *hw,
7520 + const struct mtk_pin_desc *desc, u32 arg);
7521 +int mtk_pinconf_drive_get_rev1(struct mtk_pinctrl *hw,
7522 + const struct mtk_pin_desc *desc, int *val);
7523 +
7524 +int mtk_pinconf_adv_pull_set(struct mtk_pinctrl *hw,
7525 + const struct mtk_pin_desc *desc, bool pullup,
7526 + u32 arg);
7527 +int mtk_pinconf_adv_pull_get(struct mtk_pinctrl *hw,
7528 + const struct mtk_pin_desc *desc, bool pullup,
7529 + u32 *val);
7530 +int mtk_pinconf_adv_drive_set(struct mtk_pinctrl *hw,
7531 + const struct mtk_pin_desc *desc, u32 arg);
7532 +int mtk_pinconf_adv_drive_get(struct mtk_pinctrl *hw,
7533 + const struct mtk_pin_desc *desc, u32 *val);
7534 +
7535 +#endif /* __PINCTRL_MTK_COMMON_V2_H */
7536 --- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
7537 +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
7538 @@ -514,8 +514,8 @@ static int mtk_pctrl_dt_subnode_to_map(s
7539
7540 pins = of_find_property(node, "pinmux", NULL);
7541 if (!pins) {
7542 - dev_err(pctl->dev, "missing pins property in node %s .\n",
7543 - node->name);
7544 + dev_err(pctl->dev, "missing pins property in node %pOFn .\n",
7545 + node);
7546 return -EINVAL;
7547 }
7548
7549 --- /dev/null
7550 +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-mt6765.h
7551 @@ -0,0 +1,1754 @@
7552 +/* SPDX-License-Identifier: GPL-2.0 */
7553 +/*
7554 + * Copyright (C) 2018 MediaTek Inc.
7555 + *
7556 + * Author: ZH Chen <zh.chen@mediatek.com>
7557 + *
7558 + */
7559 +
7560 +#ifndef __PINCTRL_MTK_MT6765_H
7561 +#define __PINCTRL_MTK_MT6765_H
7562 +
7563 +#include "pinctrl-paris.h"
7564 +
7565 +static struct mtk_pin_desc mtk_pins_mt6765[] = {
7566 + MTK_PIN(
7567 + 0, "GPIO0",
7568 + MTK_EINT_FUNCTION(0, 0),
7569 + DRV_GRP4,
7570 + MTK_FUNCTION(0, "GPIO0"),
7571 + MTK_FUNCTION(1, "UTXD1"),
7572 + MTK_FUNCTION(2, "CLKM0"),
7573 + MTK_FUNCTION(3, "MD_INT0"),
7574 + MTK_FUNCTION(4, "I2S0_MCK"),
7575 + MTK_FUNCTION(5, "MD_UTXD1"),
7576 + MTK_FUNCTION(6, "TP_GPIO0_AO"),
7577 + MTK_FUNCTION(7, "DBG_MON_B9")
7578 + ),
7579 + MTK_PIN(
7580 + 1, "GPIO1",
7581 + MTK_EINT_FUNCTION(0, 1),
7582 + DRV_GRP4,
7583 + MTK_FUNCTION(0, "GPIO1"),
7584 + MTK_FUNCTION(1, "URXD1"),
7585 + MTK_FUNCTION(2, "CLKM1"),
7586 + MTK_FUNCTION(4, "I2S0_BCK"),
7587 + MTK_FUNCTION(5, "MD_URXD1"),
7588 + MTK_FUNCTION(6, "TP_GPIO1_AO"),
7589 + MTK_FUNCTION(7, "DBG_MON_B10")
7590 + ),
7591 + MTK_PIN(
7592 + 2, "GPIO2",
7593 + MTK_EINT_FUNCTION(0, 2),
7594 + DRV_GRP4,
7595 + MTK_FUNCTION(0, "GPIO2"),
7596 + MTK_FUNCTION(1, "UCTS0"),
7597 + MTK_FUNCTION(2, "CLKM2"),
7598 + MTK_FUNCTION(3, "UTXD1"),
7599 + MTK_FUNCTION(4, "I2S0_LRCK"),
7600 + MTK_FUNCTION(5, "ANT_SEL6"),
7601 + MTK_FUNCTION(6, "TP_GPIO2_AO"),
7602 + MTK_FUNCTION(7, "DBG_MON_B11")
7603 + ),
7604 + MTK_PIN(
7605 + 3, "GPIO3",
7606 + MTK_EINT_FUNCTION(0, 3),
7607 + DRV_GRP4,
7608 + MTK_FUNCTION(0, "GPIO3"),
7609 + MTK_FUNCTION(1, "URTS0"),
7610 + MTK_FUNCTION(2, "CLKM3"),
7611 + MTK_FUNCTION(3, "URXD1"),
7612 + MTK_FUNCTION(4, "I2S0_DI"),
7613 + MTK_FUNCTION(5, "ANT_SEL7"),
7614 + MTK_FUNCTION(6, "TP_GPIO3_AO"),
7615 + MTK_FUNCTION(7, "DBG_MON_B12")
7616 + ),
7617 + MTK_PIN(
7618 + 4, "GPIO4",
7619 + MTK_EINT_FUNCTION(0, 4),
7620 + DRV_GRP4,
7621 + MTK_FUNCTION(0, "GPIO4"),
7622 + MTK_FUNCTION(1, "SPI1_B_MI"),
7623 + MTK_FUNCTION(2, "SCP_SPI1_MI"),
7624 + MTK_FUNCTION(3, "UCTS0"),
7625 + MTK_FUNCTION(4, "I2S3_MCK"),
7626 + MTK_FUNCTION(5, "SSPM_URXD_AO"),
7627 + MTK_FUNCTION(6, "TP_GPIO4_AO")
7628 + ),
7629 + MTK_PIN(
7630 + 5, "GPIO5",
7631 + MTK_EINT_FUNCTION(0, 5),
7632 + DRV_GRP4,
7633 + MTK_FUNCTION(0, "GPIO5"),
7634 + MTK_FUNCTION(1, "SPI1_B_CSB"),
7635 + MTK_FUNCTION(2, "SCP_SPI1_CS"),
7636 + MTK_FUNCTION(3, "URTS0"),
7637 + MTK_FUNCTION(4, "I2S3_BCK"),
7638 + MTK_FUNCTION(5, "SSPM_UTXD_AO"),
7639 + MTK_FUNCTION(6, "TP_GPIO5_AO")
7640 + ),
7641 + MTK_PIN(
7642 + 6, "GPIO6",
7643 + MTK_EINT_FUNCTION(0, 6),
7644 + DRV_GRP4,
7645 + MTK_FUNCTION(0, "GPIO6"),
7646 + MTK_FUNCTION(1, "SPI1_B_MO"),
7647 + MTK_FUNCTION(2, "SCP_SPI1_MO"),
7648 + MTK_FUNCTION(3, "PWM0"),
7649 + MTK_FUNCTION(4, "I2S3_LRCK"),
7650 + MTK_FUNCTION(5, "MD_UTXD0"),
7651 + MTK_FUNCTION(6, "TP_GPIO6_AO")
7652 + ),
7653 + MTK_PIN(
7654 + 7, "GPIO7",
7655 + MTK_EINT_FUNCTION(0, 7),
7656 + DRV_GRP4,
7657 + MTK_FUNCTION(0, "GPIO7"),
7658 + MTK_FUNCTION(1, "SPI1_B_CLK"),
7659 + MTK_FUNCTION(2, "SCP_SPI1_CK"),
7660 + MTK_FUNCTION(3, "PWM1"),
7661 + MTK_FUNCTION(4, "I2S3_DO"),
7662 + MTK_FUNCTION(5, "MD_URXD0"),
7663 + MTK_FUNCTION(6, "TP_GPIO7_AO")
7664 + ),
7665 + MTK_PIN(
7666 + 8, "GPIO8",
7667 + MTK_EINT_FUNCTION(0, 8),
7668 + DRV_GRP4,
7669 + MTK_FUNCTION(0, "GPIO8"),
7670 + MTK_FUNCTION(1, "UTXD1"),
7671 + MTK_FUNCTION(2, "SRCLKENAI0"),
7672 + MTK_FUNCTION(3, "MD_INT1_C2K_UIM0_HOT_PLUG"),
7673 + MTK_FUNCTION(4, "ANT_SEL3"),
7674 + MTK_FUNCTION(5, "MFG_JTAG_TRSTN"),
7675 + MTK_FUNCTION(6, "I2S2_MCK"),
7676 + MTK_FUNCTION(7, "JTRSTN_SEL1")
7677 + ),
7678 + MTK_PIN(
7679 + 9, "GPIO9",
7680 + MTK_EINT_FUNCTION(0, 9),
7681 + DRV_GRP4,
7682 + MTK_FUNCTION(0, "GPIO9"),
7683 + MTK_FUNCTION(1, "MD_INT0"),
7684 + MTK_FUNCTION(2, "CMMCLK2"),
7685 + MTK_FUNCTION(3, "CONN_MCU_TRST_B"),
7686 + MTK_FUNCTION(4, "IDDIG"),
7687 + MTK_FUNCTION(5, "SDA_6306"),
7688 + MTK_FUNCTION(6, "MCUPM_JTAG_TRSTN"),
7689 + MTK_FUNCTION(7, "DBG_MON_B22")
7690 + ),
7691 + MTK_PIN(
7692 + 10, "GPIO10",
7693 + MTK_EINT_FUNCTION(0, 10),
7694 + DRV_GRP4,
7695 + MTK_FUNCTION(0, "GPIO10"),
7696 + MTK_FUNCTION(1, "MD_INT1_C2K_UIM0_HOT_PLUG"),
7697 + MTK_FUNCTION(3, "CONN_MCU_DBGI_N"),
7698 + MTK_FUNCTION(4, "SRCLKENAI1"),
7699 + MTK_FUNCTION(5, "EXT_FRAME_SYNC"),
7700 + MTK_FUNCTION(6, "CMVREF1"),
7701 + MTK_FUNCTION(7, "DBG_MON_B23")
7702 + ),
7703 + MTK_PIN(
7704 + 11, "GPIO11",
7705 + MTK_EINT_FUNCTION(0, 11),
7706 + DRV_GRP4,
7707 + MTK_FUNCTION(0, "GPIO11"),
7708 + MTK_FUNCTION(1, "MD_INT2_C2K_UIM1_HOT_PLUG"),
7709 + MTK_FUNCTION(2, "CLKM3"),
7710 + MTK_FUNCTION(3, "ANT_SEL6"),
7711 + MTK_FUNCTION(4, "SRCLKENAI0"),
7712 + MTK_FUNCTION(5, "EXT_FRAME_SYNC"),
7713 + MTK_FUNCTION(6, "UCTS1"),
7714 + MTK_FUNCTION(7, "DBG_MON_B24")
7715 + ),
7716 + MTK_PIN(
7717 + 12, "GPIO12",
7718 + MTK_EINT_FUNCTION(0, 12),
7719 + DRV_GRP4,
7720 + MTK_FUNCTION(0, "GPIO12"),
7721 + MTK_FUNCTION(1, "PWM0"),
7722 + MTK_FUNCTION(2, "SRCLKENAI1"),
7723 + MTK_FUNCTION(3, "EXT_FRAME_SYNC"),
7724 + MTK_FUNCTION(4, "MD_INT0"),
7725 + MTK_FUNCTION(5, "DVFSRC_EXT_REQ"),
7726 + MTK_FUNCTION(6, "URTS1")
7727 + ),
7728 + MTK_PIN(
7729 + 13, "GPIO13",
7730 + MTK_EINT_FUNCTION(0, 13),
7731 + DRV_GRP4,
7732 + MTK_FUNCTION(0, "GPIO13"),
7733 + MTK_FUNCTION(1, "ANT_SEL0"),
7734 + MTK_FUNCTION(2, "SPI4_MI"),
7735 + MTK_FUNCTION(3, "SCP_SPI0_MI"),
7736 + MTK_FUNCTION(4, "MD_URXD0"),
7737 + MTK_FUNCTION(5, "CLKM0"),
7738 + MTK_FUNCTION(6, "I2S0_MCK"),
7739 + MTK_FUNCTION(7, "DBG_MON_A0")
7740 + ),
7741 + MTK_PIN(
7742 + 14, "GPIO14",
7743 + MTK_EINT_FUNCTION(0, 14),
7744 + DRV_GRP4,
7745 + MTK_FUNCTION(0, "GPIO14"),
7746 + MTK_FUNCTION(1, "ANT_SEL1"),
7747 + MTK_FUNCTION(2, "SPI4_CSB"),
7748 + MTK_FUNCTION(3, "SCP_SPI0_CS"),
7749 + MTK_FUNCTION(4, "MD_UTXD0"),
7750 + MTK_FUNCTION(5, "CLKM1"),
7751 + MTK_FUNCTION(6, "I2S0_BCK"),
7752 + MTK_FUNCTION(7, "DBG_MON_A1")
7753 + ),
7754 + MTK_PIN(
7755 + 15, "GPIO15",
7756 + MTK_EINT_FUNCTION(0, 15),
7757 + DRV_GRP4,
7758 + MTK_FUNCTION(0, "GPIO15"),
7759 + MTK_FUNCTION(1, "ANT_SEL2"),
7760 + MTK_FUNCTION(2, "SPI4_MO"),
7761 + MTK_FUNCTION(3, "SCP_SPI0_MO"),
7762 + MTK_FUNCTION(4, "MD_URXD1"),
7763 + MTK_FUNCTION(5, "CLKM2"),
7764 + MTK_FUNCTION(6, "I2S0_LRCK"),
7765 + MTK_FUNCTION(7, "DBG_MON_A2")
7766 + ),
7767 + MTK_PIN(
7768 + 16, "GPIO16",
7769 + MTK_EINT_FUNCTION(0, 16),
7770 + DRV_GRP4,
7771 + MTK_FUNCTION(0, "GPIO16"),
7772 + MTK_FUNCTION(1, "ANT_SEL3"),
7773 + MTK_FUNCTION(2, "SPI4_CLK"),
7774 + MTK_FUNCTION(3, "SCP_SPI0_CK"),
7775 + MTK_FUNCTION(4, "MD_UTXD1"),
7776 + MTK_FUNCTION(5, "CLKM3"),
7777 + MTK_FUNCTION(6, "I2S3_MCK"),
7778 + MTK_FUNCTION(7, "DBG_MON_A3")
7779 + ),
7780 + MTK_PIN(
7781 + 17, "GPIO17",
7782 + MTK_EINT_FUNCTION(0, 17),
7783 + DRV_GRP4,
7784 + MTK_FUNCTION(0, "GPIO17"),
7785 + MTK_FUNCTION(1, "ANT_SEL4"),
7786 + MTK_FUNCTION(2, "SPI2_MO"),
7787 + MTK_FUNCTION(3, "SCP_SPI0_MO"),
7788 + MTK_FUNCTION(4, "PWM1"),
7789 + MTK_FUNCTION(5, "IDDIG"),
7790 + MTK_FUNCTION(6, "I2S0_DI"),
7791 + MTK_FUNCTION(7, "DBG_MON_A4")
7792 + ),
7793 + MTK_PIN(
7794 + 18, "GPIO18",
7795 + MTK_EINT_FUNCTION(0, 18),
7796 + DRV_GRP4,
7797 + MTK_FUNCTION(0, "GPIO18"),
7798 + MTK_FUNCTION(1, "ANT_SEL5"),
7799 + MTK_FUNCTION(2, "SPI2_CLK"),
7800 + MTK_FUNCTION(3, "SCP_SPI0_CK"),
7801 + MTK_FUNCTION(4, "MD_INT0"),
7802 + MTK_FUNCTION(5, "USB_DRVVBUS"),
7803 + MTK_FUNCTION(6, "I2S3_BCK"),
7804 + MTK_FUNCTION(7, "DBG_MON_A5")
7805 + ),
7806 + MTK_PIN(
7807 + 19, "GPIO19",
7808 + MTK_EINT_FUNCTION(0, 19),
7809 + DRV_GRP4,
7810 + MTK_FUNCTION(0, "GPIO19"),
7811 + MTK_FUNCTION(1, "ANT_SEL6"),
7812 + MTK_FUNCTION(2, "SPI2_MI"),
7813 + MTK_FUNCTION(3, "SCP_SPI0_MI"),
7814 + MTK_FUNCTION(4, "MD_INT2_C2K_UIM1_HOT_PLUG"),
7815 + MTK_FUNCTION(6, "I2S3_LRCK"),
7816 + MTK_FUNCTION(7, "DBG_MON_A6")
7817 + ),
7818 + MTK_PIN(
7819 + 20, "GPIO20",
7820 + MTK_EINT_FUNCTION(0, 20),
7821 + DRV_GRP4,
7822 + MTK_FUNCTION(0, "GPIO20"),
7823 + MTK_FUNCTION(1, "ANT_SEL7"),
7824 + MTK_FUNCTION(2, "SPI2_CSB"),
7825 + MTK_FUNCTION(3, "SCP_SPI0_CS"),
7826 + MTK_FUNCTION(4, "MD_INT1_C2K_UIM0_HOT_PLUG"),
7827 + MTK_FUNCTION(5, "CMMCLK3"),
7828 + MTK_FUNCTION(6, "I2S3_DO"),
7829 + MTK_FUNCTION(7, "DBG_MON_A7")
7830 + ),
7831 + MTK_PIN(
7832 + 21, "GPIO21",
7833 + MTK_EINT_FUNCTION(0, 21),
7834 + DRV_GRP4,
7835 + MTK_FUNCTION(0, "GPIO21"),
7836 + MTK_FUNCTION(1, "SPI3_MI"),
7837 + MTK_FUNCTION(2, "SRCLKENAI1"),
7838 + MTK_FUNCTION(3, "DAP_MD32_SWD"),
7839 + MTK_FUNCTION(4, "CMVREF0"),
7840 + MTK_FUNCTION(5, "SCP_SPI0_MI"),
7841 + MTK_FUNCTION(6, "I2S2_MCK"),
7842 + MTK_FUNCTION(7, "DBG_MON_A8")
7843 + ),
7844 + MTK_PIN(
7845 + 22, "GPIO22",
7846 + MTK_EINT_FUNCTION(0, 22),
7847 + DRV_GRP4,
7848 + MTK_FUNCTION(0, "GPIO22"),
7849 + MTK_FUNCTION(1, "SPI3_CSB"),
7850 + MTK_FUNCTION(2, "SRCLKENAI0"),
7851 + MTK_FUNCTION(3, "DAP_MD32_SWCK"),
7852 + MTK_FUNCTION(4, "CMVREF1"),
7853 + MTK_FUNCTION(5, "SCP_SPI0_CS"),
7854 + MTK_FUNCTION(6, "I2S2_BCK"),
7855 + MTK_FUNCTION(7, "DBG_MON_A9")
7856 + ),
7857 + MTK_PIN(
7858 + 23, "GPIO23",
7859 + MTK_EINT_FUNCTION(0, 23),
7860 + DRV_GRP4,
7861 + MTK_FUNCTION(0, "GPIO23"),
7862 + MTK_FUNCTION(1, "SPI3_MO"),
7863 + MTK_FUNCTION(2, "PWM0"),
7864 + MTK_FUNCTION(3, "KPROW7"),
7865 + MTK_FUNCTION(4, "ANT_SEL3"),
7866 + MTK_FUNCTION(5, "SCP_SPI0_MO"),
7867 + MTK_FUNCTION(6, "I2S2_LRCK"),
7868 + MTK_FUNCTION(7, "DBG_MON_A10")
7869 + ),
7870 + MTK_PIN(
7871 + 24, "GPIO24",
7872 + MTK_EINT_FUNCTION(0, 24),
7873 + DRV_GRP4,
7874 + MTK_FUNCTION(0, "GPIO24"),
7875 + MTK_FUNCTION(1, "SPI3_CLK"),
7876 + MTK_FUNCTION(2, "UDI_TCK"),
7877 + MTK_FUNCTION(3, "IO_JTAG_TCK"),
7878 + MTK_FUNCTION(4, "SSPM_JTAG_TCK"),
7879 + MTK_FUNCTION(5, "SCP_SPI0_CK"),
7880 + MTK_FUNCTION(6, "I2S2_DI"),
7881 + MTK_FUNCTION(7, "DBG_MON_A11")
7882 + ),
7883 + MTK_PIN(
7884 + 25, "GPIO25",
7885 + MTK_EINT_FUNCTION(0, 25),
7886 + DRV_GRP4,
7887 + MTK_FUNCTION(0, "GPIO25"),
7888 + MTK_FUNCTION(1, "SPI1_A_MI"),
7889 + MTK_FUNCTION(2, "UDI_TMS"),
7890 + MTK_FUNCTION(3, "IO_JTAG_TMS"),
7891 + MTK_FUNCTION(4, "SSPM_JTAG_TMS"),
7892 + MTK_FUNCTION(5, "KPROW3"),
7893 + MTK_FUNCTION(6, "I2S1_MCK"),
7894 + MTK_FUNCTION(7, "DBG_MON_A12")
7895 + ),
7896 + MTK_PIN(
7897 + 26, "GPIO26",
7898 + MTK_EINT_FUNCTION(0, 26),
7899 + DRV_GRP4,
7900 + MTK_FUNCTION(0, "GPIO26"),
7901 + MTK_FUNCTION(1, "SPI1_A_CSB"),
7902 + MTK_FUNCTION(2, "UDI_TDI"),
7903 + MTK_FUNCTION(3, "IO_JTAG_TDI"),
7904 + MTK_FUNCTION(4, "SSPM_JTAG_TDI"),
7905 + MTK_FUNCTION(5, "KPROW4"),
7906 + MTK_FUNCTION(6, "I2S1_BCK"),
7907 + MTK_FUNCTION(7, "DBG_MON_A13")
7908 + ),
7909 + MTK_PIN(
7910 + 27, "GPIO27",
7911 + MTK_EINT_FUNCTION(0, 27),
7912 + DRV_GRP4,
7913 + MTK_FUNCTION(0, "GPIO27"),
7914 + MTK_FUNCTION(1, "SPI1_A_MO"),
7915 + MTK_FUNCTION(2, "UDI_TDO"),
7916 + MTK_FUNCTION(3, "IO_JTAG_TDO"),
7917 + MTK_FUNCTION(4, "SSPM_JTAG_TDO"),
7918 + MTK_FUNCTION(5, "KPROW5"),
7919 + MTK_FUNCTION(6, "I2S1_LRCK"),
7920 + MTK_FUNCTION(7, "DBG_MON_A14")
7921 + ),
7922 + MTK_PIN(
7923 + 28, "GPIO28",
7924 + MTK_EINT_FUNCTION(0, 28),
7925 + DRV_GRP4,
7926 + MTK_FUNCTION(0, "GPIO28"),
7927 + MTK_FUNCTION(1, "SPI1_A_CLK"),
7928 + MTK_FUNCTION(2, "UDI_NTRST"),
7929 + MTK_FUNCTION(3, "IO_JTAG_TRSTN"),
7930 + MTK_FUNCTION(4, "SSPM_JTAG_TRSTN"),
7931 + MTK_FUNCTION(5, "KPROW6"),
7932 + MTK_FUNCTION(6, "I2S1_DO"),
7933 + MTK_FUNCTION(7, "DBG_MON_A15")
7934 + ),
7935 + MTK_PIN(
7936 + 29, "GPIO29",
7937 + MTK_EINT_FUNCTION(0, 29),
7938 + DRV_GRP4,
7939 + MTK_FUNCTION(0, "GPIO29"),
7940 + MTK_FUNCTION(1, "MSDC1_CLK"),
7941 + MTK_FUNCTION(2, "IO_JTAG_TCK"),
7942 + MTK_FUNCTION(3, "UDI_TCK"),
7943 + MTK_FUNCTION(4, "CONN_DSP_JCK"),
7944 + MTK_FUNCTION(5, "SSPM_JTAG_TCK"),
7945 + MTK_FUNCTION(6, "CONN_MCU_AICE_TCKC"),
7946 + MTK_FUNCTION(7, "DAP_MD32_SWCK")
7947 + ),
7948 + MTK_PIN(
7949 + 30, "GPIO30",
7950 + MTK_EINT_FUNCTION(0, 30),
7951 + DRV_GRP4,
7952 + MTK_FUNCTION(0, "GPIO30"),
7953 + MTK_FUNCTION(1, "MSDC1_CMD"),
7954 + MTK_FUNCTION(2, "IO_JTAG_TMS"),
7955 + MTK_FUNCTION(3, "UDI_TMS"),
7956 + MTK_FUNCTION(4, "CONN_DSP_JMS"),
7957 + MTK_FUNCTION(5, "SSPM_JTAG_TMS"),
7958 + MTK_FUNCTION(6, "CONN_MCU_AICE_TMSC"),
7959 + MTK_FUNCTION(7, "DAP_MD32_SWD")
7960 + ),
7961 + MTK_PIN(
7962 + 31, "GPIO31",
7963 + MTK_EINT_FUNCTION(0, 31),
7964 + DRV_GRP4,
7965 + MTK_FUNCTION(0, "GPIO31"),
7966 + MTK_FUNCTION(1, "MSDC1_DAT3")
7967 + ),
7968 + MTK_PIN(
7969 + 32, "GPIO32",
7970 + MTK_EINT_FUNCTION(0, 32),
7971 + DRV_GRP4,
7972 + MTK_FUNCTION(0, "GPIO32"),
7973 + MTK_FUNCTION(1, "MSDC1_DAT0"),
7974 + MTK_FUNCTION(2, "IO_JTAG_TDI"),
7975 + MTK_FUNCTION(3, "UDI_TDI"),
7976 + MTK_FUNCTION(4, "CONN_DSP_JDI"),
7977 + MTK_FUNCTION(5, "SSPM_JTAG_TDI")
7978 + ),
7979 + MTK_PIN(
7980 + 33, "GPIO33",
7981 + MTK_EINT_FUNCTION(0, 33),
7982 + DRV_GRP4,
7983 + MTK_FUNCTION(0, "GPIO33"),
7984 + MTK_FUNCTION(1, "MSDC1_DAT2"),
7985 + MTK_FUNCTION(2, "IO_JTAG_TRSTN"),
7986 + MTK_FUNCTION(3, "UDI_NTRST"),
7987 + MTK_FUNCTION(4, "CONN_DSP_JINTP"),
7988 + MTK_FUNCTION(5, "SSPM_JTAG_TRSTN")
7989 + ),
7990 + MTK_PIN(
7991 + 34, "GPIO34",
7992 + MTK_EINT_FUNCTION(0, 34),
7993 + DRV_GRP4,
7994 + MTK_FUNCTION(0, "GPIO34"),
7995 + MTK_FUNCTION(1, "MSDC1_DAT1"),
7996 + MTK_FUNCTION(2, "IO_JTAG_TDO"),
7997 + MTK_FUNCTION(3, "UDI_TDO"),
7998 + MTK_FUNCTION(4, "CONN_DSP_JDO"),
7999 + MTK_FUNCTION(5, "SSPM_JTAG_TDO")
8000 + ),
8001 + MTK_PIN(
8002 + 35, "GPIO35",
8003 + MTK_EINT_FUNCTION(0, 35),
8004 + DRV_GRP4,
8005 + MTK_FUNCTION(0, "GPIO35"),
8006 + MTK_FUNCTION(1, "MD1_SIM2_SIO"),
8007 + MTK_FUNCTION(2, "CCU_JTAG_TDO"),
8008 + MTK_FUNCTION(3, "MD1_SIM1_SIO"),
8009 + MTK_FUNCTION(5, "SCP_JTAG_TDO"),
8010 + MTK_FUNCTION(6, "CONN_DSP_JDO"),
8011 + MTK_FUNCTION(7, "DBG_MON_A16")
8012 + ),
8013 + MTK_PIN(
8014 + 36, "GPIO36",
8015 + MTK_EINT_FUNCTION(0, 36),
8016 + DRV_GRP0,
8017 + MTK_FUNCTION(0, "GPIO36"),
8018 + MTK_FUNCTION(1, "MD1_SIM2_SRST"),
8019 + MTK_FUNCTION(2, "CCU_JTAG_TMS"),
8020 + MTK_FUNCTION(3, "MD1_SIM1_SRST"),
8021 + MTK_FUNCTION(4, "CONN_MCU_AICE_TMSC"),
8022 + MTK_FUNCTION(5, "SCP_JTAG_TMS"),
8023 + MTK_FUNCTION(6, "CONN_DSP_JMS"),
8024 + MTK_FUNCTION(7, "DBG_MON_A17")
8025 + ),
8026 + MTK_PIN(
8027 + 37, "GPIO37",
8028 + MTK_EINT_FUNCTION(0, 37),
8029 + DRV_GRP0,
8030 + MTK_FUNCTION(0, "GPIO37"),
8031 + MTK_FUNCTION(1, "MD1_SIM2_SCLK"),
8032 + MTK_FUNCTION(2, "CCU_JTAG_TDI"),
8033 + MTK_FUNCTION(3, "MD1_SIM1_SCLK"),
8034 + MTK_FUNCTION(5, "SCP_JTAG_TDI"),
8035 + MTK_FUNCTION(6, "CONN_DSP_JDI"),
8036 + MTK_FUNCTION(7, "DBG_MON_A18")
8037 + ),
8038 + MTK_PIN(
8039 + 38, "GPIO38",
8040 + MTK_EINT_FUNCTION(0, 38),
8041 + DRV_GRP0,
8042 + MTK_FUNCTION(0, "GPIO38"),
8043 + MTK_FUNCTION(1, "MD1_SIM1_SCLK"),
8044 + MTK_FUNCTION(3, "MD1_SIM2_SCLK"),
8045 + MTK_FUNCTION(7, "DBG_MON_A19")
8046 + ),
8047 + MTK_PIN(
8048 + 39, "GPIO39",
8049 + MTK_EINT_FUNCTION(0, 39),
8050 + DRV_GRP0,
8051 + MTK_FUNCTION(0, "GPIO39"),
8052 + MTK_FUNCTION(1, "MD1_SIM1_SRST"),
8053 + MTK_FUNCTION(2, "CCU_JTAG_TCK"),
8054 + MTK_FUNCTION(3, "MD1_SIM2_SRST"),
8055 + MTK_FUNCTION(4, "CONN_MCU_AICE_TCKC"),
8056 + MTK_FUNCTION(5, "SCP_JTAG_TCK"),
8057 + MTK_FUNCTION(6, "CONN_DSP_JCK"),
8058 + MTK_FUNCTION(7, "DBG_MON_A20")
8059 + ),
8060 + MTK_PIN(
8061 + 40, "GPIO40",
8062 + MTK_EINT_FUNCTION(0, 40),
8063 + DRV_GRP0,
8064 + MTK_FUNCTION(0, "GPIO40"),
8065 + MTK_FUNCTION(1, "MD1_SIM1_SIO"),
8066 + MTK_FUNCTION(2, "CCU_JTAG_TRST"),
8067 + MTK_FUNCTION(3, "MD1_SIM2_SIO"),
8068 + MTK_FUNCTION(5, "SCP_JTAG_TRSTN"),
8069 + MTK_FUNCTION(6, "CONN_DSP_JINTP"),
8070 + MTK_FUNCTION(7, "DBG_MON_A21")
8071 + ),
8072 + MTK_PIN(
8073 + 41, "GPIO41",
8074 + MTK_EINT_FUNCTION(0, 41),
8075 + DRV_GRP4,
8076 + MTK_FUNCTION(0, "GPIO41"),
8077 + MTK_FUNCTION(1, "IDDIG"),
8078 + MTK_FUNCTION(2, "URXD1"),
8079 + MTK_FUNCTION(3, "UCTS0"),
8080 + MTK_FUNCTION(4, "KPCOL2"),
8081 + MTK_FUNCTION(5, "SSPM_UTXD_AO"),
8082 + MTK_FUNCTION(6, "MD_INT0"),
8083 + MTK_FUNCTION(7, "DBG_MON_A22")
8084 + ),
8085 + MTK_PIN(
8086 + 42, "GPIO42",
8087 + MTK_EINT_FUNCTION(0, 42),
8088 + DRV_GRP4,
8089 + MTK_FUNCTION(0, "GPIO42"),
8090 + MTK_FUNCTION(1, "USB_DRVVBUS"),
8091 + MTK_FUNCTION(2, "UTXD1"),
8092 + MTK_FUNCTION(3, "URTS0"),
8093 + MTK_FUNCTION(4, "KPROW2"),
8094 + MTK_FUNCTION(5, "SSPM_URXD_AO"),
8095 + MTK_FUNCTION(6, "MD_INT1_C2K_UIM0_HOT_PLUG"),
8096 + MTK_FUNCTION(7, "DBG_MON_A23")
8097 + ),
8098 + MTK_PIN(
8099 + 43, "GPIO43",
8100 + MTK_EINT_FUNCTION(0, 43),
8101 + DRV_GRP4,
8102 + MTK_FUNCTION(0, "GPIO43"),
8103 + MTK_FUNCTION(1, "DISP_PWM"),
8104 + MTK_FUNCTION(7, "DBG_MON_A24")
8105 + ),
8106 + MTK_PIN(
8107 + 44, "GPIO44",
8108 + MTK_EINT_FUNCTION(0, 44),
8109 + DRV_GRP4,
8110 + MTK_FUNCTION(0, "GPIO44"),
8111 + MTK_FUNCTION(1, "DSI_TE"),
8112 + MTK_FUNCTION(7, "DBG_MON_A25")
8113 + ),
8114 + MTK_PIN(
8115 + 45, "GPIO45",
8116 + MTK_EINT_FUNCTION(0, 45),
8117 + DRV_GRP4,
8118 + MTK_FUNCTION(0, "GPIO45"),
8119 + MTK_FUNCTION(1, "LCM_RST"),
8120 + MTK_FUNCTION(7, "DBG_MON_A26")
8121 + ),
8122 + MTK_PIN(
8123 + 46, "GPIO46",
8124 + MTK_EINT_FUNCTION(0, 46),
8125 + DRV_GRP4,
8126 + MTK_FUNCTION(0, "GPIO46"),
8127 + MTK_FUNCTION(1, "MD_INT2_C2K_UIM1_HOT_PLUG"),
8128 + MTK_FUNCTION(2, "UCTS0"),
8129 + MTK_FUNCTION(3, "UCTS1"),
8130 + MTK_FUNCTION(4, "IDDIG"),
8131 + MTK_FUNCTION(5, "SCL_6306"),
8132 + MTK_FUNCTION(6, "TP_UCTS1_AO"),
8133 + MTK_FUNCTION(7, "DBG_MON_A27")
8134 + ),
8135 + MTK_PIN(
8136 + 47, "GPIO47",
8137 + MTK_EINT_FUNCTION(0, 47),
8138 + DRV_GRP4,
8139 + MTK_FUNCTION(0, "GPIO47"),
8140 + MTK_FUNCTION(1, "MD_INT1_C2K_UIM0_HOT_PLUG"),
8141 + MTK_FUNCTION(2, "URTS0"),
8142 + MTK_FUNCTION(3, "URTS1"),
8143 + MTK_FUNCTION(4, "USB_DRVVBUS"),
8144 + MTK_FUNCTION(5, "SDA_6306"),
8145 + MTK_FUNCTION(6, "TP_URTS1_AO"),
8146 + MTK_FUNCTION(7, "DBG_MON_A28")
8147 + ),
8148 + MTK_PIN(
8149 + 48, "GPIO48",
8150 + MTK_EINT_FUNCTION(0, 48),
8151 + DRV_GRP4,
8152 + MTK_FUNCTION(0, "GPIO48"),
8153 + MTK_FUNCTION(1, "SCL5"),
8154 + MTK_FUNCTION(7, "DBG_MON_A29")
8155 + ),
8156 + MTK_PIN(
8157 + 49, "GPIO49",
8158 + MTK_EINT_FUNCTION(0, 49),
8159 + DRV_GRP4,
8160 + MTK_FUNCTION(0, "GPIO49"),
8161 + MTK_FUNCTION(1, "SDA5"),
8162 + MTK_FUNCTION(7, "DBG_MON_A30")
8163 + ),
8164 + MTK_PIN(
8165 + 50, "GPIO50",
8166 + MTK_EINT_FUNCTION(0, 50),
8167 + DRV_GRP4,
8168 + MTK_FUNCTION(0, "GPIO50"),
8169 + MTK_FUNCTION(1, "SCL3"),
8170 + MTK_FUNCTION(2, "URXD1"),
8171 + MTK_FUNCTION(3, "MD_URXD1"),
8172 + MTK_FUNCTION(4, "SSPM_URXD_AO"),
8173 + MTK_FUNCTION(5, "IDDIG"),
8174 + MTK_FUNCTION(6, "TP_URXD1_AO"),
8175 + MTK_FUNCTION(7, "DBG_MON_A31")
8176 + ),
8177 + MTK_PIN(
8178 + 51, "GPIO51",
8179 + MTK_EINT_FUNCTION(0, 51),
8180 + DRV_GRP4,
8181 + MTK_FUNCTION(0, "GPIO51"),
8182 + MTK_FUNCTION(1, "SDA3"),
8183 + MTK_FUNCTION(2, "UTXD1"),
8184 + MTK_FUNCTION(3, "MD_UTXD1"),
8185 + MTK_FUNCTION(4, "SSPM_UTXD_AO"),
8186 + MTK_FUNCTION(5, "USB_DRVVBUS"),
8187 + MTK_FUNCTION(6, "TP_UTXD1_AO"),
8188 + MTK_FUNCTION(7, "DBG_MON_A32")
8189 + ),
8190 + MTK_PIN(
8191 + 52, "GPIO52",
8192 + MTK_EINT_FUNCTION(0, 52),
8193 + DRV_GRP4,
8194 + MTK_FUNCTION(0, "GPIO52"),
8195 + MTK_FUNCTION(1, "BPI_BUS15")
8196 + ),
8197 + MTK_PIN(
8198 + 53, "GPIO53",
8199 + MTK_EINT_FUNCTION(0, 53),
8200 + DRV_GRP4,
8201 + MTK_FUNCTION(0, "GPIO53"),
8202 + MTK_FUNCTION(1, "BPI_BUS13")
8203 + ),
8204 + MTK_PIN(
8205 + 54, "GPIO54",
8206 + MTK_EINT_FUNCTION(0, 54),
8207 + DRV_GRP4,
8208 + MTK_FUNCTION(0, "GPIO54"),
8209 + MTK_FUNCTION(1, "BPI_BUS12")
8210 + ),
8211 + MTK_PIN(
8212 + 55, "GPIO55",
8213 + MTK_EINT_FUNCTION(0, 55),
8214 + DRV_GRP4,
8215 + MTK_FUNCTION(0, "GPIO55"),
8216 + MTK_FUNCTION(1, "BPI_BUS8")
8217 + ),
8218 + MTK_PIN(
8219 + 56, "GPIO56",
8220 + MTK_EINT_FUNCTION(0, 56),
8221 + DRV_GRP4,
8222 + MTK_FUNCTION(0, "GPIO56"),
8223 + MTK_FUNCTION(1, "BPI_BUS9"),
8224 + MTK_FUNCTION(2, "SCL_6306")
8225 + ),
8226 + MTK_PIN(
8227 + 57, "GPIO57",
8228 + MTK_EINT_FUNCTION(0, 57),
8229 + DRV_GRP4,
8230 + MTK_FUNCTION(0, "GPIO57"),
8231 + MTK_FUNCTION(1, "BPI_BUS10"),
8232 + MTK_FUNCTION(2, "SDA_6306")
8233 + ),
8234 + MTK_PIN(
8235 + 58, "GPIO58",
8236 + MTK_EINT_FUNCTION(0, 58),
8237 + DRV_GRP4,
8238 + MTK_FUNCTION(0, "GPIO58"),
8239 + MTK_FUNCTION(1, "RFIC0_BSI_D2")
8240 + ),
8241 + MTK_PIN(
8242 + 59, "GPIO59",
8243 + MTK_EINT_FUNCTION(0, 59),
8244 + DRV_GRP4,
8245 + MTK_FUNCTION(0, "GPIO59"),
8246 + MTK_FUNCTION(1, "RFIC0_BSI_D1")
8247 + ),
8248 + MTK_PIN(
8249 + 60, "GPIO60",
8250 + MTK_EINT_FUNCTION(0, 60),
8251 + DRV_GRP4,
8252 + MTK_FUNCTION(0, "GPIO60"),
8253 + MTK_FUNCTION(1, "RFIC0_BSI_D0")
8254 + ),
8255 + MTK_PIN(
8256 + 61, "GPIO61",
8257 + MTK_EINT_FUNCTION(0, 61),
8258 + DRV_GRP4,
8259 + MTK_FUNCTION(0, "GPIO61"),
8260 + MTK_FUNCTION(1, "MIPI1_SDATA")
8261 + ),
8262 + MTK_PIN(
8263 + 62, "GPIO62",
8264 + MTK_EINT_FUNCTION(0, 62),
8265 + DRV_GRP4,
8266 + MTK_FUNCTION(0, "GPIO62"),
8267 + MTK_FUNCTION(1, "MIPI1_SCLK")
8268 + ),
8269 + MTK_PIN(
8270 + 63, "GPIO63",
8271 + MTK_EINT_FUNCTION(0, 63),
8272 + DRV_GRP4,
8273 + MTK_FUNCTION(0, "GPIO63"),
8274 + MTK_FUNCTION(1, "MIPI0_SDATA")
8275 + ),
8276 + MTK_PIN(
8277 + 64, "GPIO64",
8278 + MTK_EINT_FUNCTION(0, 64),
8279 + DRV_GRP4,
8280 + MTK_FUNCTION(0, "GPIO64"),
8281 + MTK_FUNCTION(1, "MIPI0_SCLK")
8282 + ),
8283 + MTK_PIN(
8284 + 65, "GPIO65",
8285 + MTK_EINT_FUNCTION(0, 65),
8286 + DRV_GRP4,
8287 + MTK_FUNCTION(0, "GPIO65"),
8288 + MTK_FUNCTION(1, "MIPI3_SDATA"),
8289 + MTK_FUNCTION(2, "BPI_BUS16")
8290 + ),
8291 + MTK_PIN(
8292 + 66, "GPIO66",
8293 + MTK_EINT_FUNCTION(0, 66),
8294 + DRV_GRP4,
8295 + MTK_FUNCTION(0, "GPIO66"),
8296 + MTK_FUNCTION(1, "MIPI3_SCLK"),
8297 + MTK_FUNCTION(2, "BPI_BUS17")
8298 + ),
8299 + MTK_PIN(
8300 + 67, "GPIO67",
8301 + MTK_EINT_FUNCTION(0, 67),
8302 + DRV_GRP4,
8303 + MTK_FUNCTION(0, "GPIO67"),
8304 + MTK_FUNCTION(1, "MIPI2_SDATA")
8305 + ),
8306 + MTK_PIN(
8307 + 68, "GPIO68",
8308 + MTK_EINT_FUNCTION(0, 68),
8309 + DRV_GRP4,
8310 + MTK_FUNCTION(0, "GPIO68"),
8311 + MTK_FUNCTION(1, "MIPI2_SCLK")
8312 + ),
8313 + MTK_PIN(
8314 + 69, "GPIO69",
8315 + MTK_EINT_FUNCTION(0, 69),
8316 + DRV_GRP4,
8317 + MTK_FUNCTION(0, "GPIO69"),
8318 + MTK_FUNCTION(1, "BPI_BUS7")
8319 + ),
8320 + MTK_PIN(
8321 + 70, "GPIO70",
8322 + MTK_EINT_FUNCTION(0, 70),
8323 + DRV_GRP4,
8324 + MTK_FUNCTION(0, "GPIO70"),
8325 + MTK_FUNCTION(1, "BPI_BUS6")
8326 + ),
8327 + MTK_PIN(
8328 + 71, "GPIO71",
8329 + MTK_EINT_FUNCTION(0, 71),
8330 + DRV_GRP4,
8331 + MTK_FUNCTION(0, "GPIO71"),
8332 + MTK_FUNCTION(1, "BPI_BUS5")
8333 + ),
8334 + MTK_PIN(
8335 + 72, "GPIO72",
8336 + MTK_EINT_FUNCTION(0, 72),
8337 + DRV_GRP4,
8338 + MTK_FUNCTION(0, "GPIO72"),
8339 + MTK_FUNCTION(1, "BPI_BUS4")
8340 + ),
8341 + MTK_PIN(
8342 + 73, "GPIO73",
8343 + MTK_EINT_FUNCTION(0, 73),
8344 + DRV_GRP4,
8345 + MTK_FUNCTION(0, "GPIO73"),
8346 + MTK_FUNCTION(1, "BPI_BUS3")
8347 + ),
8348 + MTK_PIN(
8349 + 74, "GPIO74",
8350 + MTK_EINT_FUNCTION(0, 74),
8351 + DRV_GRP4,
8352 + MTK_FUNCTION(0, "GPIO74"),
8353 + MTK_FUNCTION(1, "BPI_BUS2")
8354 + ),
8355 + MTK_PIN(
8356 + 75, "GPIO75",
8357 + MTK_EINT_FUNCTION(0, 75),
8358 + DRV_GRP4,
8359 + MTK_FUNCTION(0, "GPIO75"),
8360 + MTK_FUNCTION(1, "BPI_BUS1")
8361 + ),
8362 + MTK_PIN(
8363 + 76, "GPIO76",
8364 + MTK_EINT_FUNCTION(0, 76),
8365 + DRV_GRP4,
8366 + MTK_FUNCTION(0, "GPIO76"),
8367 + MTK_FUNCTION(1, "BPI_BUS0")
8368 + ),
8369 + MTK_PIN(
8370 + 77, "GPIO77",
8371 + MTK_EINT_FUNCTION(0, 77),
8372 + DRV_GRP4,
8373 + MTK_FUNCTION(0, "GPIO77"),
8374 + MTK_FUNCTION(1, "BPI_BUS14")
8375 + ),
8376 + MTK_PIN(
8377 + 78, "GPIO78",
8378 + MTK_EINT_FUNCTION(0, 78),
8379 + DRV_GRP4,
8380 + MTK_FUNCTION(0, "GPIO78"),
8381 + MTK_FUNCTION(1, "BPI_BUS11")
8382 + ),
8383 + MTK_PIN(
8384 + 79, "GPIO79",
8385 + MTK_EINT_FUNCTION(0, 79),
8386 + DRV_GRP4,
8387 + MTK_FUNCTION(0, "GPIO79"),
8388 + MTK_FUNCTION(1, "BPI_PA_VM1"),
8389 + MTK_FUNCTION(2, "MIPI4_SDATA")
8390 + ),
8391 + MTK_PIN(
8392 + 80, "GPIO80",
8393 + MTK_EINT_FUNCTION(0, 80),
8394 + DRV_GRP4,
8395 + MTK_FUNCTION(0, "GPIO80"),
8396 + MTK_FUNCTION(1, "BPI_PA_VM0"),
8397 + MTK_FUNCTION(2, "MIPI4_SCLK")
8398 + ),
8399 + MTK_PIN(
8400 + 81, "GPIO81",
8401 + MTK_EINT_FUNCTION(0, 81),
8402 + DRV_GRP4,
8403 + MTK_FUNCTION(0, "GPIO81"),
8404 + MTK_FUNCTION(1, "SDA1"),
8405 + MTK_FUNCTION(7, "DBG_MON_B0")
8406 + ),
8407 + MTK_PIN(
8408 + 82, "GPIO82",
8409 + MTK_EINT_FUNCTION(0, 82),
8410 + DRV_GRP4,
8411 + MTK_FUNCTION(0, "GPIO82"),
8412 + MTK_FUNCTION(1, "SDA0"),
8413 + MTK_FUNCTION(7, "DBG_MON_B1")
8414 + ),
8415 + MTK_PIN(
8416 + 83, "GPIO83",
8417 + MTK_EINT_FUNCTION(0, 83),
8418 + DRV_GRP4,
8419 + MTK_FUNCTION(0, "GPIO83"),
8420 + MTK_FUNCTION(1, "SCL0"),
8421 + MTK_FUNCTION(7, "DBG_MON_B2")
8422 + ),
8423 + MTK_PIN(
8424 + 84, "GPIO84",
8425 + MTK_EINT_FUNCTION(0, 84),
8426 + DRV_GRP4,
8427 + MTK_FUNCTION(0, "GPIO84"),
8428 + MTK_FUNCTION(1, "SCL1"),
8429 + MTK_FUNCTION(7, "DBG_MON_B3")
8430 + ),
8431 + MTK_PIN(
8432 + 85, "GPIO85",
8433 + MTK_EINT_FUNCTION(0, 85),
8434 + DRV_GRP4,
8435 + MTK_FUNCTION(0, "GPIO85"),
8436 + MTK_FUNCTION(1, "RFIC0_BSI_EN")
8437 + ),
8438 + MTK_PIN(
8439 + 86, "GPIO86",
8440 + MTK_EINT_FUNCTION(0, 86),
8441 + DRV_GRP4,
8442 + MTK_FUNCTION(0, "GPIO86"),
8443 + MTK_FUNCTION(1, "RFIC0_BSI_CK")
8444 + ),
8445 + MTK_PIN(
8446 + 87, "GPIO87",
8447 + MTK_EINT_FUNCTION(0, 87),
8448 + DRV_GRP4,
8449 + MTK_FUNCTION(0, "GPIO87"),
8450 + MTK_FUNCTION(2, "MD_INT1_C2K_UIM0_HOT_PLUG"),
8451 + MTK_FUNCTION(3, "CMVREF0"),
8452 + MTK_FUNCTION(4, "MD_URXD0"),
8453 + MTK_FUNCTION(5, "AGPS_SYNC"),
8454 + MTK_FUNCTION(6, "EXT_FRAME_SYNC")
8455 + ),
8456 + MTK_PIN(
8457 + 88, "GPIO88",
8458 + MTK_EINT_FUNCTION(0, 88),
8459 + DRV_GRP4,
8460 + MTK_FUNCTION(0, "GPIO88"),
8461 + MTK_FUNCTION(1, "CMMCLK3"),
8462 + MTK_FUNCTION(2, "MD_INT2_C2K_UIM1_HOT_PLUG"),
8463 + MTK_FUNCTION(3, "CMVREF1"),
8464 + MTK_FUNCTION(4, "MD_UTXD0"),
8465 + MTK_FUNCTION(5, "AGPS_SYNC"),
8466 + MTK_FUNCTION(6, "DVFSRC_EXT_REQ")
8467 + ),
8468 + MTK_PIN(
8469 + 89, "GPIO89",
8470 + MTK_EINT_FUNCTION(0, 89),
8471 + DRV_GRP4,
8472 + MTK_FUNCTION(0, "GPIO89"),
8473 + MTK_FUNCTION(1, "SRCLKENAI0"),
8474 + MTK_FUNCTION(2, "PWM2"),
8475 + MTK_FUNCTION(3, "MD_INT0"),
8476 + MTK_FUNCTION(4, "USB_DRVVBUS"),
8477 + MTK_FUNCTION(5, "SCL_6306"),
8478 + MTK_FUNCTION(6, "TP_GPIO4_AO"),
8479 + MTK_FUNCTION(7, "DBG_MON_B21")
8480 + ),
8481 + MTK_PIN(
8482 + 90, "GPIO90",
8483 + MTK_EINT_FUNCTION(0, 90),
8484 + DRV_GRP4,
8485 + MTK_FUNCTION(0, "GPIO90"),
8486 + MTK_FUNCTION(1, "URXD1"),
8487 + MTK_FUNCTION(2, "PWM0"),
8488 + MTK_FUNCTION(3, "MD_INT2_C2K_UIM1_HOT_PLUG"),
8489 + MTK_FUNCTION(4, "ANT_SEL4"),
8490 + MTK_FUNCTION(5, "USB_DRVVBUS"),
8491 + MTK_FUNCTION(6, "I2S2_BCK"),
8492 + MTK_FUNCTION(7, "DBG_MON_B4")
8493 + ),
8494 + MTK_PIN(
8495 + 91, "GPIO91",
8496 + MTK_EINT_FUNCTION(0, 91),
8497 + DRV_GRP4,
8498 + MTK_FUNCTION(0, "GPIO91"),
8499 + MTK_FUNCTION(1, "KPROW1"),
8500 + MTK_FUNCTION(2, "PWM2"),
8501 + MTK_FUNCTION(3, "MD_INT0"),
8502 + MTK_FUNCTION(4, "ANT_SEL5"),
8503 + MTK_FUNCTION(5, "IDDIG"),
8504 + MTK_FUNCTION(6, "I2S2_LRCK"),
8505 + MTK_FUNCTION(7, "DBG_MON_B5")
8506 + ),
8507 + MTK_PIN(
8508 + 92, "GPIO92",
8509 + MTK_EINT_FUNCTION(0, 92),
8510 + DRV_GRP4,
8511 + MTK_FUNCTION(0, "GPIO92"),
8512 + MTK_FUNCTION(1, "KPROW0"),
8513 + MTK_FUNCTION(5, "DVFSRC_EXT_REQ"),
8514 + MTK_FUNCTION(6, "I2S2_DI"),
8515 + MTK_FUNCTION(7, "DBG_MON_B6")
8516 + ),
8517 + MTK_PIN(
8518 + 93, "GPIO93",
8519 + MTK_EINT_FUNCTION(0, 93),
8520 + DRV_GRP4,
8521 + MTK_FUNCTION(0, "GPIO93"),
8522 + MTK_FUNCTION(1, "KPCOL0"),
8523 + MTK_FUNCTION(7, "DBG_MON_B7")
8524 + ),
8525 + MTK_PIN(
8526 + 94, "GPIO94",
8527 + MTK_EINT_FUNCTION(0, 94),
8528 + DRV_GRP4,
8529 + MTK_FUNCTION(0, "GPIO94"),
8530 + MTK_FUNCTION(1, "KPCOL1"),
8531 + MTK_FUNCTION(5, "CMFLASH"),
8532 + MTK_FUNCTION(6, "CMVREF0"),
8533 + MTK_FUNCTION(7, "DBG_MON_B8")
8534 + ),
8535 + MTK_PIN(
8536 + 95, "GPIO95",
8537 + MTK_EINT_FUNCTION(0, 95),
8538 + DRV_GRP4,
8539 + MTK_FUNCTION(0, "GPIO95"),
8540 + MTK_FUNCTION(1, "URXD0"),
8541 + MTK_FUNCTION(2, "UTXD0"),
8542 + MTK_FUNCTION(3, "MD_URXD0"),
8543 + MTK_FUNCTION(4, "PTA_RXD"),
8544 + MTK_FUNCTION(5, "SSPM_URXD_AO"),
8545 + MTK_FUNCTION(6, "WIFI_RXD")
8546 + ),
8547 + MTK_PIN(
8548 + 96, "GPIO96",
8549 + MTK_EINT_FUNCTION(0, 96),
8550 + DRV_GRP4,
8551 + MTK_FUNCTION(0, "GPIO96"),
8552 + MTK_FUNCTION(1, "UTXD0"),
8553 + MTK_FUNCTION(2, "URXD0"),
8554 + MTK_FUNCTION(3, "MD_UTXD0"),
8555 + MTK_FUNCTION(4, "PTA_TXD"),
8556 + MTK_FUNCTION(5, "SSPM_UTXD_AO"),
8557 + MTK_FUNCTION(6, "WIFI_TXD")
8558 + ),
8559 + MTK_PIN(
8560 + 97, "GPIO97",
8561 + MTK_EINT_FUNCTION(0, 97),
8562 + DRV_GRP4,
8563 + MTK_FUNCTION(0, "GPIO97"),
8564 + MTK_FUNCTION(1, "UCTS0"),
8565 + MTK_FUNCTION(2, "I2S1_MCK"),
8566 + MTK_FUNCTION(3, "CONN_MCU_TDO"),
8567 + MTK_FUNCTION(4, "SPI5_MI"),
8568 + MTK_FUNCTION(5, "SCL_6306"),
8569 + MTK_FUNCTION(6, "MCUPM_JTAG_TDO"),
8570 + MTK_FUNCTION(7, "DBG_MON_B15")
8571 + ),
8572 + MTK_PIN(
8573 + 98, "GPIO98",
8574 + MTK_EINT_FUNCTION(0, 98),
8575 + DRV_GRP4,
8576 + MTK_FUNCTION(0, "GPIO98"),
8577 + MTK_FUNCTION(1, "URTS0"),
8578 + MTK_FUNCTION(2, "I2S1_BCK"),
8579 + MTK_FUNCTION(3, "CONN_MCU_TMS"),
8580 + MTK_FUNCTION(4, "SPI5_CSB"),
8581 + MTK_FUNCTION(6, "MCUPM_JTAG_TMS"),
8582 + MTK_FUNCTION(7, "DBG_MON_B16")
8583 + ),
8584 + MTK_PIN(
8585 + 99, "GPIO99",
8586 + MTK_EINT_FUNCTION(0, 99),
8587 + DRV_GRP4,
8588 + MTK_FUNCTION(0, "GPIO99"),
8589 + MTK_FUNCTION(1, "CMMCLK0"),
8590 + MTK_FUNCTION(4, "AUXIF_CLK"),
8591 + MTK_FUNCTION(5, "PTA_RXD"),
8592 + MTK_FUNCTION(6, "CONN_UART0_RXD"),
8593 + MTK_FUNCTION(7, "DBG_MON_B17")
8594 + ),
8595 +
8596 + MTK_PIN(
8597 + 100, "GPIO100",
8598 + MTK_EINT_FUNCTION(0, 100),
8599 + DRV_GRP4,
8600 + MTK_FUNCTION(0, "GPIO100"),
8601 + MTK_FUNCTION(1, "CMMCLK1"),
8602 + MTK_FUNCTION(4, "AUXIF_ST"),
8603 + MTK_FUNCTION(5, "PTA_TXD"),
8604 + MTK_FUNCTION(6, "CONN_UART0_TXD"),
8605 + MTK_FUNCTION(7, "DBG_MON_B18")
8606 + ),
8607 + MTK_PIN(
8608 + 101, "GPIO101",
8609 + MTK_EINT_FUNCTION(0, 101),
8610 + DRV_GRP4,
8611 + MTK_FUNCTION(0, "GPIO101"),
8612 + MTK_FUNCTION(1, "CMFLASH"),
8613 + MTK_FUNCTION(2, "I2S1_LRCK"),
8614 + MTK_FUNCTION(3, "CONN_MCU_TCK"),
8615 + MTK_FUNCTION(4, "SPI5_MO"),
8616 + MTK_FUNCTION(6, "MCUPM_JTAG_TCK"),
8617 + MTK_FUNCTION(7, "DBG_MON_B19")
8618 + ),
8619 + MTK_PIN(
8620 + 102, "GPIO102",
8621 + MTK_EINT_FUNCTION(0, 102),
8622 + DRV_GRP4,
8623 + MTK_FUNCTION(0, "GPIO102"),
8624 + MTK_FUNCTION(1, "CMVREF0"),
8625 + MTK_FUNCTION(2, "I2S1_DO"),
8626 + MTK_FUNCTION(3, "CONN_MCU_TDI"),
8627 + MTK_FUNCTION(4, "SPI5_CLK"),
8628 + MTK_FUNCTION(5, "AGPS_SYNC"),
8629 + MTK_FUNCTION(6, "MCUPM_JTAG_TDI"),
8630 + MTK_FUNCTION(7, "DBG_MON_B20")
8631 + ),
8632 + MTK_PIN(
8633 + 103, "GPIO103",
8634 + MTK_EINT_FUNCTION(0, 103),
8635 + DRV_GRP4,
8636 + MTK_FUNCTION(0, "GPIO103"),
8637 + MTK_FUNCTION(1, "SCL2"),
8638 + MTK_FUNCTION(2, "TP_UTXD1_AO"),
8639 + MTK_FUNCTION(3, "MD_UTXD0"),
8640 + MTK_FUNCTION(4, "MD_UTXD1"),
8641 + MTK_FUNCTION(5, "TP_URTS2_AO"),
8642 + MTK_FUNCTION(6, "WIFI_TXD"),
8643 + MTK_FUNCTION(7, "DBG_MON_B25")
8644 + ),
8645 + MTK_PIN(
8646 + 104, "GPIO104",
8647 + MTK_EINT_FUNCTION(0, 104),
8648 + DRV_GRP4,
8649 + MTK_FUNCTION(0, "GPIO104"),
8650 + MTK_FUNCTION(1, "SDA2"),
8651 + MTK_FUNCTION(2, "TP_URXD1_AO"),
8652 + MTK_FUNCTION(3, "MD_URXD0"),
8653 + MTK_FUNCTION(4, "MD_URXD1"),
8654 + MTK_FUNCTION(5, "TP_UCTS2_AO"),
8655 + MTK_FUNCTION(6, "WIFI_RXD"),
8656 + MTK_FUNCTION(7, "DBG_MON_B26")
8657 + ),
8658 + MTK_PIN(
8659 + 105, "GPIO105",
8660 + MTK_EINT_FUNCTION(0, 105),
8661 + DRV_GRP4,
8662 + MTK_FUNCTION(0, "GPIO105"),
8663 + MTK_FUNCTION(1, "SCL4"),
8664 + MTK_FUNCTION(3, "MD_UTXD1"),
8665 + MTK_FUNCTION(4, "MD_UTXD0"),
8666 + MTK_FUNCTION(5, "TP_UTXD2_AO"),
8667 + MTK_FUNCTION(6, "PTA_TXD"),
8668 + MTK_FUNCTION(7, "DBG_MON_B27")
8669 + ),
8670 + MTK_PIN(
8671 + 106, "GPIO106",
8672 + MTK_EINT_FUNCTION(0, 106),
8673 + DRV_GRP4,
8674 + MTK_FUNCTION(0, "GPIO106"),
8675 + MTK_FUNCTION(1, "SDA4"),
8676 + MTK_FUNCTION(3, "MD_URXD1"),
8677 + MTK_FUNCTION(4, "MD_URXD0"),
8678 + MTK_FUNCTION(5, "TP_URXD2_AO"),
8679 + MTK_FUNCTION(6, "PTA_RXD"),
8680 + MTK_FUNCTION(7, "DBG_MON_B28")
8681 + ),
8682 + MTK_PIN(
8683 + 107, "GPIO107",
8684 + MTK_EINT_FUNCTION(0, 107),
8685 + DRV_GRP4,
8686 + MTK_FUNCTION(0, "GPIO107"),
8687 + MTK_FUNCTION(1, "UTXD1"),
8688 + MTK_FUNCTION(2, "MD_UTXD0"),
8689 + MTK_FUNCTION(3, "SDA_6306"),
8690 + MTK_FUNCTION(4, "KPCOL3"),
8691 + MTK_FUNCTION(5, "CMVREF0"),
8692 + MTK_FUNCTION(6, "URTS0"),
8693 + MTK_FUNCTION(7, "DBG_MON_B29")
8694 + ),
8695 + MTK_PIN(
8696 + 108, "GPIO108",
8697 + MTK_EINT_FUNCTION(0, 108),
8698 + DRV_GRP4,
8699 + MTK_FUNCTION(0, "GPIO108"),
8700 + MTK_FUNCTION(1, "CMMCLK2"),
8701 + MTK_FUNCTION(2, "MD_INT0"),
8702 + MTK_FUNCTION(3, "CONN_MCU_DBGACK_N"),
8703 + MTK_FUNCTION(4, "KPCOL4"),
8704 + MTK_FUNCTION(6, "I2S3_MCK"),
8705 + MTK_FUNCTION(7, "DBG_MON_B30")
8706 + ),
8707 + MTK_PIN(
8708 + 109, "GPIO109",
8709 + MTK_EINT_FUNCTION(0, 109),
8710 + DRV_GRP4,
8711 + MTK_FUNCTION(0, "GPIO109"),
8712 + MTK_FUNCTION(1, "URXD1"),
8713 + MTK_FUNCTION(2, "MD_URXD0"),
8714 + MTK_FUNCTION(3, "ANT_SEL7"),
8715 + MTK_FUNCTION(4, "KPCOL5"),
8716 + MTK_FUNCTION(5, "CMVREF1"),
8717 + MTK_FUNCTION(6, "UCTS0"),
8718 + MTK_FUNCTION(7, "DBG_MON_B31")
8719 + ),
8720 + MTK_PIN(
8721 + 110, "GPIO110",
8722 + MTK_EINT_FUNCTION(0, 110),
8723 + DRV_GRP4,
8724 + MTK_FUNCTION(0, "GPIO110"),
8725 + MTK_FUNCTION(1, "ANT_SEL0"),
8726 + MTK_FUNCTION(2, "CLKM0"),
8727 + MTK_FUNCTION(3, "PWM3"),
8728 + MTK_FUNCTION(4, "MD_INT0"),
8729 + MTK_FUNCTION(5, "IDDIG"),
8730 + MTK_FUNCTION(6, "I2S3_BCK"),
8731 + MTK_FUNCTION(7, "DBG_MON_B13")
8732 + ),
8733 + MTK_PIN(
8734 + 111, "GPIO111",
8735 + MTK_EINT_FUNCTION(0, 111),
8736 + DRV_GRP4,
8737 + MTK_FUNCTION(0, "GPIO111"),
8738 + MTK_FUNCTION(1, "ANT_SEL1"),
8739 + MTK_FUNCTION(2, "CLKM1"),
8740 + MTK_FUNCTION(3, "PWM4"),
8741 + MTK_FUNCTION(4, "PTA_RXD"),
8742 + MTK_FUNCTION(5, "CMVREF0"),
8743 + MTK_FUNCTION(6, "I2S3_LRCK"),
8744 + MTK_FUNCTION(7, "DBG_MON_B14")
8745 + ),
8746 + MTK_PIN(
8747 + 112, "GPIO112",
8748 + MTK_EINT_FUNCTION(0, 112),
8749 + DRV_GRP4,
8750 + MTK_FUNCTION(0, "GPIO112"),
8751 + MTK_FUNCTION(1, "ANT_SEL2"),
8752 + MTK_FUNCTION(2, "CLKM2"),
8753 + MTK_FUNCTION(3, "PWM5"),
8754 + MTK_FUNCTION(4, "PTA_TXD"),
8755 + MTK_FUNCTION(5, "CMVREF1"),
8756 + MTK_FUNCTION(6, "I2S3_DO")
8757 + ),
8758 + MTK_PIN(
8759 + 113, "GPIO113",
8760 + MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT),
8761 + DRV_GRP4,
8762 + MTK_FUNCTION(0, "GPIO113"),
8763 + MTK_FUNCTION(1, "CONN_TOP_CLK")
8764 + ),
8765 + MTK_PIN(
8766 + 114, "GPIO114",
8767 + MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT),
8768 + DRV_GRP4,
8769 + MTK_FUNCTION(0, "GPIO114"),
8770 + MTK_FUNCTION(1, "CONN_TOP_DATA")
8771 + ),
8772 + MTK_PIN(
8773 + 115, "GPIO115",
8774 + MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT),
8775 + DRV_GRP4,
8776 + MTK_FUNCTION(0, "GPIO115"),
8777 + MTK_FUNCTION(1, "CONN_BT_CLK")
8778 + ),
8779 + MTK_PIN(
8780 + 116, "GPIO116",
8781 + MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT),
8782 + DRV_GRP4,
8783 + MTK_FUNCTION(0, "GPIO116"),
8784 + MTK_FUNCTION(1, "CONN_BT_DATA")
8785 + ),
8786 + MTK_PIN(
8787 + 117, "GPIO117",
8788 + MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT),
8789 + DRV_GRP4,
8790 + MTK_FUNCTION(0, "GPIO117"),
8791 + MTK_FUNCTION(1, "CONN_WF_CTRL0")
8792 + ),
8793 + MTK_PIN(
8794 + 118, "GPIO118",
8795 + MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT),
8796 + DRV_GRP4,
8797 + MTK_FUNCTION(0, "GPIO118"),
8798 + MTK_FUNCTION(1, "CONN_WF_CTRL1")
8799 + ),
8800 + MTK_PIN(
8801 + 119, "GPIO119",
8802 + MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT),
8803 + DRV_GRP4,
8804 + MTK_FUNCTION(0, "GPIO119"),
8805 + MTK_FUNCTION(1, "CONN_WF_CTRL2")
8806 + ),
8807 + MTK_PIN(
8808 + 120, "GPIO120",
8809 + MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT),
8810 + DRV_GRP4,
8811 + MTK_FUNCTION(0, "GPIO120"),
8812 + MTK_FUNCTION(1, "CONN_WB_PTA")
8813 + ),
8814 + MTK_PIN(
8815 + 121, "GPIO121",
8816 + MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT),
8817 + DRV_GRP4,
8818 + MTK_FUNCTION(0, "GPIO121"),
8819 + MTK_FUNCTION(1, "CONN_HRST_B")
8820 + ),
8821 + MTK_PIN(
8822 + 122, "GPIO122",
8823 + MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT),
8824 + DRV_GRP4,
8825 + MTK_FUNCTION(0, "GPIO122"),
8826 + MTK_FUNCTION(1, "MSDC0_CMD"),
8827 + MTK_FUNCTION(2, "MSDC0_CMD")
8828 + ),
8829 + MTK_PIN(
8830 + 123, "GPIO123",
8831 + MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT),
8832 + DRV_GRP4,
8833 + MTK_FUNCTION(0, "GPIO123"),
8834 + MTK_FUNCTION(1, "MSDC0_DAT0"),
8835 + MTK_FUNCTION(2, "MSDC0_DAT4")
8836 + ),
8837 + MTK_PIN(
8838 + 124, "GPIO124",
8839 + MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT),
8840 + DRV_GRP4,
8841 + MTK_FUNCTION(0, "GPIO124"),
8842 + MTK_FUNCTION(1, "MSDC0_CLK"),
8843 + MTK_FUNCTION(2, "MSDC0_CLK")
8844 + ),
8845 + MTK_PIN(
8846 + 125, "GPIO125",
8847 + MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT),
8848 + DRV_GRP4,
8849 + MTK_FUNCTION(0, "GPIO125"),
8850 + MTK_FUNCTION(1, "MSDC0_DAT2"),
8851 + MTK_FUNCTION(2, "MSDC0_DAT5")
8852 + ),
8853 + MTK_PIN(
8854 + 126, "GPIO126",
8855 + MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT),
8856 + DRV_GRP4,
8857 + MTK_FUNCTION(0, "GPIO126"),
8858 + MTK_FUNCTION(1, "MSDC0_DAT4"),
8859 + MTK_FUNCTION(2, "MSDC0_DAT2")
8860 + ),
8861 + MTK_PIN(
8862 + 127, "GPIO127",
8863 + MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT),
8864 + DRV_GRP4,
8865 + MTK_FUNCTION(0, "GPIO127"),
8866 + MTK_FUNCTION(1, "MSDC0_DAT6"),
8867 + MTK_FUNCTION(2, "MSDC0_DAT1")
8868 + ),
8869 + MTK_PIN(
8870 + 128, "GPIO128",
8871 + MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT),
8872 + DRV_GRP4,
8873 + MTK_FUNCTION(0, "GPIO128"),
8874 + MTK_FUNCTION(1, "MSDC0_DAT1"),
8875 + MTK_FUNCTION(2, "MSDC0_DAT6")
8876 + ),
8877 + MTK_PIN(
8878 + 129, "GPIO129",
8879 + MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT),
8880 + DRV_GRP4,
8881 + MTK_FUNCTION(0, "GPIO129"),
8882 + MTK_FUNCTION(1, "MSDC0_DAT5"),
8883 + MTK_FUNCTION(2, "MSDC0_DAT0")
8884 + ),
8885 + MTK_PIN(
8886 + 130, "GPIO130",
8887 + MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT),
8888 + DRV_GRP4,
8889 + MTK_FUNCTION(0, "GPIO130"),
8890 + MTK_FUNCTION(1, "MSDC0_DAT7"),
8891 + MTK_FUNCTION(2, "MSDC0_DAT7")
8892 + ),
8893 + MTK_PIN(
8894 + 131, "GPIO131",
8895 + MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT),
8896 + DRV_GRP4,
8897 + MTK_FUNCTION(0, "GPIO131"),
8898 + MTK_FUNCTION(1, "MSDC0_DSL"),
8899 + MTK_FUNCTION(2, "MSDC0_DSL")
8900 + ),
8901 + MTK_PIN(
8902 + 132, "GPIO132",
8903 + MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT),
8904 + DRV_GRP4,
8905 + MTK_FUNCTION(0, "GPIO132"),
8906 + MTK_FUNCTION(1, "MSDC0_DAT3"),
8907 + MTK_FUNCTION(2, "MSDC0_DAT3")
8908 + ),
8909 + MTK_PIN(
8910 + 133, "GPIO133",
8911 + MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT),
8912 + DRV_GRP4,
8913 + MTK_FUNCTION(0, "GPIO133"),
8914 + MTK_FUNCTION(1, "MSDC0_RSTB"),
8915 + MTK_FUNCTION(2, "MSDC0_RSTB")
8916 + ),
8917 + MTK_PIN(
8918 + 134, "GPIO134",
8919 + MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT),
8920 + DRV_GRP4,
8921 + MTK_FUNCTION(0, "GPIO134"),
8922 + MTK_FUNCTION(1, "RTC32K_CK")
8923 + ),
8924 + MTK_PIN(
8925 + 135, "GPIO135",
8926 + MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT),
8927 + DRV_GRP4,
8928 + MTK_FUNCTION(0, "GPIO135"),
8929 + MTK_FUNCTION(1, "WATCHDOG")
8930 + ),
8931 + MTK_PIN(
8932 + 136, "GPIO136",
8933 + MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT),
8934 + DRV_GRP4,
8935 + MTK_FUNCTION(0, "GPIO136"),
8936 + MTK_FUNCTION(1, "AUD_CLK_MOSI"),
8937 + MTK_FUNCTION(2, "AUD_CLK_MISO"),
8938 + MTK_FUNCTION(3, "I2S1_MCK")
8939 + ),
8940 + MTK_PIN(
8941 + 137, "GPIO137",
8942 + MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT),
8943 + DRV_GRP4,
8944 + MTK_FUNCTION(0, "GPIO137"),
8945 + MTK_FUNCTION(1, "AUD_SYNC_MOSI"),
8946 + MTK_FUNCTION(2, "AUD_SYNC_MISO"),
8947 + MTK_FUNCTION(3, "I2S1_BCK")
8948 + ),
8949 + MTK_PIN(
8950 + 138, "GPIO138",
8951 + MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT),
8952 + DRV_GRP4,
8953 + MTK_FUNCTION(0, "GPIO138"),
8954 + MTK_FUNCTION(1, "AUD_DAT_MOSI0"),
8955 + MTK_FUNCTION(2, "AUD_DAT_MISO0"),
8956 + MTK_FUNCTION(3, "I2S1_LRCK")
8957 + ),
8958 + MTK_PIN(
8959 + 139, "GPIO139",
8960 + MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT),
8961 + DRV_GRP4,
8962 + MTK_FUNCTION(0, "GPIO139"),
8963 + MTK_FUNCTION(1, "AUD_DAT_MOSI1"),
8964 + MTK_FUNCTION(2, "AUD_DAT_MISO1"),
8965 + MTK_FUNCTION(3, "I2S1_DO")
8966 + ),
8967 + MTK_PIN(
8968 + 140, "GPIO140",
8969 + MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT),
8970 + DRV_GRP4,
8971 + MTK_FUNCTION(0, "GPIO140"),
8972 + MTK_FUNCTION(1, "AUD_CLK_MISO"),
8973 + MTK_FUNCTION(2, "AUD_CLK_MOSI"),
8974 + MTK_FUNCTION(3, "I2S2_MCK")
8975 + ),
8976 + MTK_PIN(
8977 + 141, "GPIO141",
8978 + MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT),
8979 + DRV_GRP4,
8980 + MTK_FUNCTION(0, "GPIO141"),
8981 + MTK_FUNCTION(1, "AUD_SYNC_MISO"),
8982 + MTK_FUNCTION(2, "AUD_SYNC_MOSI"),
8983 + MTK_FUNCTION(3, "I2S2_BCK")
8984 + ),
8985 + MTK_PIN(
8986 + 142, "GPIO142",
8987 + MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT),
8988 + DRV_GRP4,
8989 + MTK_FUNCTION(0, "GPIO142"),
8990 + MTK_FUNCTION(1, "AUD_DAT_MISO0"),
8991 + MTK_FUNCTION(2, "AUD_DAT_MOSI0"),
8992 + MTK_FUNCTION(3, "I2S2_LRCK")
8993 + ),
8994 + MTK_PIN(
8995 + 143, "GPIO143",
8996 + MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT),
8997 + DRV_GRP4,
8998 + MTK_FUNCTION(0, "GPIO143"),
8999 + MTK_FUNCTION(1, "AUD_DAT_MISO1"),
9000 + MTK_FUNCTION(2, "AUD_DAT_MOSI1"),
9001 + MTK_FUNCTION(3, "I2S2_DI")
9002 + ),
9003 + MTK_PIN(
9004 + 144, "GPIO144",
9005 + MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT),
9006 + DRV_GRP4,
9007 + MTK_FUNCTION(0, "GPIO144"),
9008 + MTK_FUNCTION(1, "PWRAP_SPI0_MI"),
9009 + MTK_FUNCTION(2, "PWRAP_SPI0_MO")
9010 + ),
9011 + MTK_PIN(
9012 + 145, "GPIO145",
9013 + MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT),
9014 + DRV_GRP4,
9015 + MTK_FUNCTION(0, "GPIO145"),
9016 + MTK_FUNCTION(1, "PWRAP_SPI0_CSN")
9017 + ),
9018 + MTK_PIN(
9019 + 146, "GPIO146",
9020 + MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT),
9021 + DRV_GRP4,
9022 + MTK_FUNCTION(0, "GPIO146"),
9023 + MTK_FUNCTION(1, "PWRAP_SPI0_MO"),
9024 + MTK_FUNCTION(2, "PWRAP_SPI0_MI")
9025 + ),
9026 + MTK_PIN(
9027 + 147, "GPIO147",
9028 + MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT),
9029 + DRV_GRP4,
9030 + MTK_FUNCTION(0, "GPIO147"),
9031 + MTK_FUNCTION(1, "PWRAP_SPI0_CK")
9032 + ),
9033 + MTK_PIN(
9034 + 148, "GPIO148",
9035 + MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT),
9036 + DRV_GRP4,
9037 + MTK_FUNCTION(0, "GPIO148"),
9038 + MTK_FUNCTION(1, "SRCLKENA0")
9039 + ),
9040 + MTK_PIN(
9041 + 149, "GPIO149",
9042 + MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT),
9043 + DRV_GRP4,
9044 + MTK_FUNCTION(0, "GPIO149"),
9045 + MTK_FUNCTION(1, "SRCLKENA1")
9046 + ),
9047 + MTK_PIN(
9048 + 150, "GPIO150",
9049 + MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT),
9050 + DRV_GRP4,
9051 + MTK_FUNCTION(0, "GPIO150"),
9052 + MTK_FUNCTION(1, "PWM0"),
9053 + MTK_FUNCTION(2, "CMFLASH"),
9054 + MTK_FUNCTION(3, "ANT_SEL3"),
9055 + MTK_FUNCTION(5, "MD_URXD0"),
9056 + MTK_FUNCTION(6, "TP_URXD2_AO")
9057 + ),
9058 + MTK_PIN(
9059 + 151, "GPIO151",
9060 + MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT),
9061 + DRV_GRP4,
9062 + MTK_FUNCTION(0, "GPIO151"),
9063 + MTK_FUNCTION(1, "PWM1"),
9064 + MTK_FUNCTION(2, "CMVREF0"),
9065 + MTK_FUNCTION(3, "ANT_SEL4"),
9066 + MTK_FUNCTION(5, "MD_UTXD0"),
9067 + MTK_FUNCTION(6, "TP_UTXD2_AO")
9068 + ),
9069 + MTK_PIN(
9070 + 152, "GPIO152",
9071 + MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT),
9072 + DRV_GRP4,
9073 + MTK_FUNCTION(0, "GPIO152"),
9074 + MTK_FUNCTION(1, "PWM2"),
9075 + MTK_FUNCTION(2, "CMVREF1"),
9076 + MTK_FUNCTION(3, "ANT_SEL5"),
9077 + MTK_FUNCTION(5, "MD_URXD1"),
9078 + MTK_FUNCTION(6, "TP_UCTS1_AO")
9079 + ),
9080 + MTK_PIN(
9081 + 153, "GPIO153",
9082 + MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT),
9083 + DRV_GRP4,
9084 + MTK_FUNCTION(0, "GPIO153"),
9085 + MTK_FUNCTION(1, "PWM3"),
9086 + MTK_FUNCTION(2, "CLKM0"),
9087 + MTK_FUNCTION(3, "ANT_SEL6"),
9088 + MTK_FUNCTION(5, "MD_UTXD1"),
9089 + MTK_FUNCTION(6, "TP_URTS1_AO")
9090 + ),
9091 + MTK_PIN(
9092 + 154, "GPIO154",
9093 + MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT),
9094 + DRV_GRP4,
9095 + MTK_FUNCTION(0, "GPIO154"),
9096 + MTK_FUNCTION(1, "PWM5"),
9097 + MTK_FUNCTION(2, "CLKM2"),
9098 + MTK_FUNCTION(3, "USB_DRVVBUS"),
9099 + MTK_FUNCTION(5, "PTA_TXD"),
9100 + MTK_FUNCTION(6, "CONN_UART0_TXD")
9101 + ),
9102 + MTK_PIN(
9103 + 155, "GPIO155",
9104 + MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT),
9105 + DRV_GRP4,
9106 + MTK_FUNCTION(0, "GPIO155"),
9107 + MTK_FUNCTION(1, "SPI0_MI"),
9108 + MTK_FUNCTION(2, "IDDIG"),
9109 + MTK_FUNCTION(3, "AGPS_SYNC"),
9110 + MTK_FUNCTION(4, "TP_GPIO0_AO"),
9111 + MTK_FUNCTION(5, "MFG_JTAG_TDO"),
9112 + MTK_FUNCTION(6, "DFD_TDO"),
9113 + MTK_FUNCTION(7, "JTDO_SEL1")
9114 + ),
9115 + MTK_PIN(
9116 + 156, "GPIO156",
9117 + MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT),
9118 + DRV_GRP4,
9119 + MTK_FUNCTION(0, "GPIO156"),
9120 + MTK_FUNCTION(1, "SPI0_CSB"),
9121 + MTK_FUNCTION(2, "USB_DRVVBUS"),
9122 + MTK_FUNCTION(3, "DVFSRC_EXT_REQ"),
9123 + MTK_FUNCTION(4, "TP_GPIO1_AO"),
9124 + MTK_FUNCTION(5, "MFG_JTAG_TMS"),
9125 + MTK_FUNCTION(6, "DFD_TMS"),
9126 + MTK_FUNCTION(7, "JTMS_SEL1")
9127 + ),
9128 + MTK_PIN(
9129 + 157, "GPIO157",
9130 + MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT),
9131 + DRV_GRP4,
9132 + MTK_FUNCTION(0, "GPIO157"),
9133 + MTK_FUNCTION(1, "SPI0_MO"),
9134 + MTK_FUNCTION(2, "MD_INT1_C2K_UIM0_HOT_PLUG"),
9135 + MTK_FUNCTION(3, "CLKM0"),
9136 + MTK_FUNCTION(4, "TP_GPIO2_AO"),
9137 + MTK_FUNCTION(5, "MFG_JTAG_TDI"),
9138 + MTK_FUNCTION(6, "DFD_TDI"),
9139 + MTK_FUNCTION(7, "JTDI_SEL1")
9140 + ),
9141 + MTK_PIN(
9142 + 158, "GPIO158",
9143 + MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT),
9144 + DRV_GRP4,
9145 + MTK_FUNCTION(0, "GPIO158"),
9146 + MTK_FUNCTION(1, "SPI0_CLK"),
9147 + MTK_FUNCTION(2, "MD_INT2_C2K_UIM1_HOT_PLUG"),
9148 + MTK_FUNCTION(3, "EXT_FRAME_SYNC"),
9149 + MTK_FUNCTION(4, "TP_GPIO3_AO"),
9150 + MTK_FUNCTION(5, "MFG_JTAG_TCK"),
9151 + MTK_FUNCTION(6, "DFD_TCK_XI"),
9152 + MTK_FUNCTION(7, "JTCK_SEL1")
9153 + ),
9154 + MTK_PIN(
9155 + 159, "GPIO159",
9156 + MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT),
9157 + DRV_GRP4,
9158 + MTK_FUNCTION(0, "GPIO159"),
9159 + MTK_FUNCTION(1, "PWM4"),
9160 + MTK_FUNCTION(2, "CLKM1"),
9161 + MTK_FUNCTION(3, "ANT_SEL7"),
9162 + MTK_FUNCTION(5, "PTA_RXD"),
9163 + MTK_FUNCTION(6, "CONN_UART0_RXD")
9164 + ),
9165 + MTK_PIN(
9166 + 160, "GPIO160",
9167 + MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT),
9168 + DRV_GRP4,
9169 + MTK_FUNCTION(0, "GPIO160"),
9170 + MTK_FUNCTION(1, "CLKM0"),
9171 + MTK_FUNCTION(2, "PWM2"),
9172 + MTK_FUNCTION(3, "EXT_FRAME_SYNC"),
9173 + MTK_FUNCTION(4, "TP_GPIO5_AO"),
9174 + MTK_FUNCTION(5, "AGPS_SYNC"),
9175 + MTK_FUNCTION(6, "DVFSRC_EXT_REQ")
9176 + ),
9177 + MTK_PIN(
9178 + 161, "GPIO161",
9179 + MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT),
9180 + DRV_GRP4,
9181 + MTK_FUNCTION(0, "GPIO161"),
9182 + MTK_FUNCTION(1, "SCL6"),
9183 + MTK_FUNCTION(2, "SCL_6306"),
9184 + MTK_FUNCTION(3, "TP_GPIO6_AO"),
9185 + MTK_FUNCTION(4, "KPCOL6"),
9186 + MTK_FUNCTION(5, "PTA_RXD"),
9187 + MTK_FUNCTION(6, "CONN_UART0_RXD")
9188 + ),
9189 + MTK_PIN(
9190 + 162, "GPIO162",
9191 + MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT),
9192 + DRV_GRP4,
9193 + MTK_FUNCTION(0, "GPIO162"),
9194 + MTK_FUNCTION(1, "SDA6"),
9195 + MTK_FUNCTION(2, "SDA_6306"),
9196 + MTK_FUNCTION(3, "TP_GPIO7_AO"),
9197 + MTK_FUNCTION(4, "KPCOL7"),
9198 + MTK_FUNCTION(5, "PTA_TXD"),
9199 + MTK_FUNCTION(6, "CONN_UART0_TXD")
9200 + ),
9201 + MTK_PIN(
9202 + 163, "GPIO163",
9203 + MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT),
9204 + DRV_GRP4,
9205 + MTK_FUNCTION(0, "GPIO163")
9206 + ),
9207 + MTK_PIN(
9208 + 164, "GPIO164",
9209 + MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT),
9210 + DRV_GRP4,
9211 + MTK_FUNCTION(0, "GPIO164")
9212 + ),
9213 + MTK_PIN(
9214 + 165, "GPIO165",
9215 + MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT),
9216 + DRV_GRP4,
9217 + MTK_FUNCTION(0, "GPIO165")
9218 + ),
9219 + MTK_PIN(
9220 + 166, "GPIO166",
9221 + MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT),
9222 + DRV_GRP4,
9223 + MTK_FUNCTION(0, "GPIO166")
9224 + ),
9225 + MTK_PIN(
9226 + 167, "GPIO167",
9227 + MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT),
9228 + DRV_GRP4,
9229 + MTK_FUNCTION(0, "GPIO167")
9230 + ),
9231 + MTK_PIN(
9232 + 168, "GPIO168",
9233 + MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT),
9234 + DRV_GRP4,
9235 + MTK_FUNCTION(0, "GPIO168")
9236 + ),
9237 + MTK_PIN(
9238 + 169, "GPIO169",
9239 + MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT),
9240 + DRV_GRP4,
9241 + MTK_FUNCTION(0, "GPIO169")
9242 + ),
9243 + MTK_PIN(
9244 + 170, "GPIO170",
9245 + MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT),
9246 + DRV_GRP4,
9247 + MTK_FUNCTION(0, "GPIO170")
9248 + ),
9249 + MTK_PIN(
9250 + 171, "GPIO171",
9251 + MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT),
9252 + DRV_GRP4,
9253 + MTK_FUNCTION(0, "GPIO171")
9254 + ),
9255 + MTK_PIN(
9256 + 172, "GPIO172",
9257 + MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT),
9258 + DRV_GRP4,
9259 + MTK_FUNCTION(0, "GPIO172")
9260 + ),
9261 + MTK_PIN(
9262 + 173, "GPIO173",
9263 + MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT),
9264 + DRV_GRP4,
9265 + MTK_FUNCTION(0, "GPIO173")
9266 + ),
9267 + MTK_PIN(
9268 + 174, "GPIO174",
9269 + MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT),
9270 + DRV_GRP4,
9271 + MTK_FUNCTION(0, "GPIO174")
9272 + ),
9273 + MTK_PIN(
9274 + 175, "GPIO175",
9275 + MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT),
9276 + DRV_GRP4,
9277 + MTK_FUNCTION(0, "GPIO175")
9278 + ),
9279 + MTK_PIN(
9280 + 176, "GPIO176",
9281 + MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT),
9282 + DRV_GRP4,
9283 + MTK_FUNCTION(0, "GPIO176")
9284 + ),
9285 + MTK_PIN(
9286 + 177, "GPIO177",
9287 + MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT),
9288 + DRV_GRP4,
9289 + MTK_FUNCTION(0, "GPIO177")
9290 + ),
9291 + MTK_PIN(
9292 + 178, "GPIO178",
9293 + MTK_EINT_FUNCTION(0, NO_EINT_SUPPORT),
9294 + DRV_GRP4,
9295 + MTK_FUNCTION(0, "GPIO178")
9296 + ),
9297 + MTK_PIN(
9298 + 179, "GPIO179",
9299 + MTK_EINT_FUNCTION(0, 151),
9300 + DRV_GRP4,
9301 + MTK_FUNCTION(0, "GPIO179")
9302 + ),
9303 +};
9304 +
9305 +#endif /* __PINCTRL_MTK_MT6765_H */
9306 --- /dev/null
9307 +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-mt6797.h
9308 @@ -0,0 +1,2429 @@
9309 +/* SPDX-License-Identifier: GPL-2.0 */
9310 +/*
9311 + * Based on pinctrl-mtk-mt6765.h
9312 + *
9313 + * Copyright (C) 2018 MediaTek Inc.
9314 + *
9315 + * Author: ZH Chen <zh.chen@mediatek.com>
9316 + *
9317 + * Copyright (c) 2018 Manivannan Sadhasivam
9318 + */
9319 +
9320 +#ifndef __PINCTRL_MTK_MT6797_H
9321 +#define __PINCTRL_MTK_MT6797_H
9322 +
9323 +#include "pinctrl-paris.h"
9324 +
9325 +static const struct mtk_pin_desc mtk_pins_mt6797[] = {
9326 + MTK_PIN(
9327 + 0, "GPIO0",
9328 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
9329 + DRV_GRP3,
9330 + MTK_FUNCTION(0, "GPIO0"),
9331 + MTK_FUNCTION(1, "CSI0A_L0P_T0A")
9332 + ),
9333 + MTK_PIN(
9334 + 1, "GPIO1",
9335 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
9336 + DRV_GRP3,
9337 + MTK_FUNCTION(0, "GPIO1"),
9338 + MTK_FUNCTION(1, "CSI0A_L0N_T0B")
9339 + ),
9340 + MTK_PIN(
9341 + 2, "GPIO2",
9342 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
9343 + DRV_GRP3,
9344 + MTK_FUNCTION(0, "GPIO2"),
9345 + MTK_FUNCTION(1, "CSI0A_L1P_T0C")
9346 + ),
9347 + MTK_PIN(
9348 + 3, "GPIO3",
9349 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
9350 + DRV_GRP3,
9351 + MTK_FUNCTION(0, "GPIO3"),
9352 + MTK_FUNCTION(1, "CSI0A_L1N_T1A")
9353 + ),
9354 + MTK_PIN(
9355 + 4, "GPIO4",
9356 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
9357 + DRV_GRP3,
9358 + MTK_FUNCTION(0, "GPIO4"),
9359 + MTK_FUNCTION(1, "CSI0A_L2P_T1B")
9360 + ),
9361 + MTK_PIN(
9362 + 5, "GPIO5",
9363 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
9364 + DRV_GRP3,
9365 + MTK_FUNCTION(0, "GPIO5"),
9366 + MTK_FUNCTION(1, "CSI0A_L2N_T1C")
9367 + ),
9368 + MTK_PIN(
9369 + 6, "GPIO6",
9370 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
9371 + DRV_GRP3,
9372 + MTK_FUNCTION(0, "GPIO6"),
9373 + MTK_FUNCTION(1, "CSI0B_L0P_T0A")
9374 + ),
9375 + MTK_PIN(
9376 + 7, "GPIO7",
9377 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
9378 + DRV_GRP3,
9379 + MTK_FUNCTION(0, "GPIO7"),
9380 + MTK_FUNCTION(1, "CSI0B_L0N_T0B")
9381 + ),
9382 + MTK_PIN(
9383 + 8, "GPIO8",
9384 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
9385 + DRV_GRP3,
9386 + MTK_FUNCTION(0, "GPIO8"),
9387 + MTK_FUNCTION(1, "CSI0B_L1P_T0C")
9388 + ),
9389 + MTK_PIN(
9390 + 9, "GPIO9",
9391 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
9392 + DRV_GRP3,
9393 + MTK_FUNCTION(0, "GPIO9"),
9394 + MTK_FUNCTION(1, "CSI0B_L1N_T1A")
9395 + ),
9396 + MTK_PIN(
9397 + 10, "GPIO10",
9398 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
9399 + DRV_GRP3,
9400 + MTK_FUNCTION(0, "GPIO10"),
9401 + MTK_FUNCTION(1, "CSI1A_L0P_T0A")
9402 + ),
9403 + MTK_PIN(
9404 + 11, "GPIO11",
9405 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
9406 + DRV_GRP3,
9407 + MTK_FUNCTION(0, "GPIO11"),
9408 + MTK_FUNCTION(1, "CSI1A_L0N_T0B")
9409 + ),
9410 + MTK_PIN(
9411 + 12, "GPIO12",
9412 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
9413 + DRV_GRP3,
9414 + MTK_FUNCTION(0, "GPIO12"),
9415 + MTK_FUNCTION(1, "CSI1A_L1P_T0C")
9416 + ),
9417 + MTK_PIN(
9418 + 13, "GPIO13",
9419 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
9420 + DRV_GRP3,
9421 + MTK_FUNCTION(0, "GPIO13"),
9422 + MTK_FUNCTION(1, "CSI1A_L1N_T1A")
9423 + ),
9424 + MTK_PIN(
9425 + 14, "GPIO14",
9426 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
9427 + DRV_GRP3,
9428 + MTK_FUNCTION(0, "GPIO14"),
9429 + MTK_FUNCTION(1, "CSI1A_L2P_T1B")
9430 + ),
9431 + MTK_PIN(
9432 + 15, "GPIO15",
9433 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
9434 + DRV_GRP3,
9435 + MTK_FUNCTION(0, "GPIO15"),
9436 + MTK_FUNCTION(1, "CSI1A_L2N_T1C")
9437 + ),
9438 + MTK_PIN(
9439 + 16, "GPIO16",
9440 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
9441 + DRV_GRP3,
9442 + MTK_FUNCTION(0, "GPIO16"),
9443 + MTK_FUNCTION(1, "CSI1B_L0P_T0A")
9444 + ),
9445 + MTK_PIN(
9446 + 17, "GPIO17",
9447 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
9448 + DRV_GRP3,
9449 + MTK_FUNCTION(0, "GPIO17"),
9450 + MTK_FUNCTION(1, "CSI1B_L0N_T0B")
9451 + ),
9452 + MTK_PIN(
9453 + 18, "GPIO18",
9454 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
9455 + DRV_GRP3,
9456 + MTK_FUNCTION(0, "GPIO18"),
9457 + MTK_FUNCTION(1, "CSI1B_L1P_T0C")
9458 + ),
9459 + MTK_PIN(
9460 + 19, "GPIO19",
9461 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
9462 + DRV_GRP3,
9463 + MTK_FUNCTION(0, "GPIO19"),
9464 + MTK_FUNCTION(1, "CSI1B_L1N_T1A")
9465 + ),
9466 + MTK_PIN(
9467 + 20, "GPIO20",
9468 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
9469 + DRV_GRP3,
9470 + MTK_FUNCTION(0, "GPIO20"),
9471 + MTK_FUNCTION(1, "CSI1B_L2P_T1B")
9472 + ),
9473 + MTK_PIN(
9474 + 21, "GPIO21",
9475 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
9476 + DRV_GRP3,
9477 + MTK_FUNCTION(0, "GPIO21"),
9478 + MTK_FUNCTION(1, "CSI1B_L2N_T1C")
9479 + ),
9480 + MTK_PIN(
9481 + 22, "GPIO22",
9482 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
9483 + DRV_GRP3,
9484 + MTK_FUNCTION(0, "GPIO22"),
9485 + MTK_FUNCTION(1, "CSI2_L0P_T0A")
9486 + ),
9487 + MTK_PIN(
9488 + 23, "GPIO23",
9489 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
9490 + DRV_GRP3,
9491 + MTK_FUNCTION(0, "GPIO23"),
9492 + MTK_FUNCTION(1, "CSI2_L0N_T0B")
9493 + ),
9494 + MTK_PIN(
9495 + 24, "GPIO24",
9496 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
9497 + DRV_GRP3,
9498 + MTK_FUNCTION(0, "GPIO24"),
9499 + MTK_FUNCTION(1, "CSI2_L1P_T0C")
9500 + ),
9501 + MTK_PIN(
9502 + 25, "GPIO25",
9503 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
9504 + DRV_GRP3,
9505 + MTK_FUNCTION(0, "GPIO25"),
9506 + MTK_FUNCTION(1, "CSI2_L1N_T1A")
9507 + ),
9508 + MTK_PIN(
9509 + 26, "GPIO26",
9510 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
9511 + DRV_GRP3,
9512 + MTK_FUNCTION(0, "GPIO26"),
9513 + MTK_FUNCTION(1, "CSI2_L2P_T1B")
9514 + ),
9515 + MTK_PIN(
9516 + 27, "GPIO27",
9517 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
9518 + DRV_GRP3,
9519 + MTK_FUNCTION(0, "GPIO27"),
9520 + MTK_FUNCTION(1, "CSI2_L2N_T1C")
9521 + ),
9522 + MTK_PIN(
9523 + 28, "GPIO28",
9524 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
9525 + DRV_GRP3,
9526 + MTK_FUNCTION(0, "GPIO28"),
9527 + MTK_FUNCTION(1, "SPI5_CLK_A"),
9528 + MTK_FUNCTION(2, "IRTX_OUT"),
9529 + MTK_FUNCTION(3, "UDI_TDO"),
9530 + MTK_FUNCTION(4, "SCP_JTAG_TDO"),
9531 + MTK_FUNCTION(5, "CONN_MCU_TDO"),
9532 + MTK_FUNCTION(6, "PWM_A"),
9533 + MTK_FUNCTION(7, "C2K_DM_OTDO")
9534 + ),
9535 + MTK_PIN(
9536 + 29, "GPIO29",
9537 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
9538 + DRV_GRP3,
9539 + MTK_FUNCTION(0, "GPIO29"),
9540 + MTK_FUNCTION(1, "SPI5_MI_A"),
9541 + MTK_FUNCTION(2, "DAP_SIB1_SWD"),
9542 + MTK_FUNCTION(3, "UDI_TMS"),
9543 + MTK_FUNCTION(4, "SCP_JTAG_TMS"),
9544 + MTK_FUNCTION(5, "CONN_MCU_TMS"),
9545 + MTK_FUNCTION(6, "CONN_MCU_AICE_TMSC"),
9546 + MTK_FUNCTION(7, "C2K_DM_OTMS")
9547 + ),
9548 + MTK_PIN(
9549 + 30, "GPIO30",
9550 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
9551 + DRV_GRP3,
9552 + MTK_FUNCTION(0, "GPIO30"),
9553 + MTK_FUNCTION(1, "CMMCLK0"),
9554 + MTK_FUNCTION(7, "MD_CLKM0")
9555 + ),
9556 + MTK_PIN(
9557 + 31, "GPIO31",
9558 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
9559 + DRV_GRP3,
9560 + MTK_FUNCTION(0, "GPIO31"),
9561 + MTK_FUNCTION(1, "CMMCLK1"),
9562 + MTK_FUNCTION(7, "MD_CLKM1")
9563 + ),
9564 + MTK_PIN(
9565 + 32, "GPIO32",
9566 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
9567 + DRV_GRP3,
9568 + MTK_FUNCTION(0, "GPIO32"),
9569 + MTK_FUNCTION(1, "SPI5_CS_A"),
9570 + MTK_FUNCTION(2, "DAP_SIB1_SWCK"),
9571 + MTK_FUNCTION(3, "UDI_TCK_XI"),
9572 + MTK_FUNCTION(4, "SCP_JTAG_TCK"),
9573 + MTK_FUNCTION(5, "CONN_MCU_TCK"),
9574 + MTK_FUNCTION(6, "CONN_MCU_AICE_TCKC"),
9575 + MTK_FUNCTION(7, "C2K_DM_OTCK")
9576 + ),
9577 + MTK_PIN(
9578 + 33, "GPIO33",
9579 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
9580 + DRV_GRP3,
9581 + MTK_FUNCTION(0, "GPIO33"),
9582 + MTK_FUNCTION(1, "SPI5_MO_A"),
9583 + MTK_FUNCTION(2, "CMFLASH"),
9584 + MTK_FUNCTION(3, "UDI_TDI"),
9585 + MTK_FUNCTION(4, "SCP_JTAG_TDI"),
9586 + MTK_FUNCTION(5, "CONN_MCU_TDI"),
9587 + MTK_FUNCTION(6, "MD_URXD0"),
9588 + MTK_FUNCTION(7, "C2K_DM_OTDI")
9589 + ),
9590 + MTK_PIN(
9591 + 34, "GPIO34",
9592 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
9593 + DRV_GRP3,
9594 + MTK_FUNCTION(0, "GPIO34"),
9595 + MTK_FUNCTION(1, "CMFLASH"),
9596 + MTK_FUNCTION(2, "CLKM0"),
9597 + MTK_FUNCTION(3, "UDI_NTRST"),
9598 + MTK_FUNCTION(4, "SCP_JTAG_TRSTN"),
9599 + MTK_FUNCTION(5, "CONN_MCU_TRST_B"),
9600 + MTK_FUNCTION(6, "MD_UTXD0"),
9601 + MTK_FUNCTION(7, "C2K_DM_JTINTP")
9602 + ),
9603 + MTK_PIN(
9604 + 35, "GPIO35",
9605 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
9606 + DRV_GRP3,
9607 + MTK_FUNCTION(0, "GPIO35"),
9608 + MTK_FUNCTION(1, "CMMCLK3"),
9609 + MTK_FUNCTION(2, "CLKM1"),
9610 + MTK_FUNCTION(3, "MD_URXD1"),
9611 + MTK_FUNCTION(4, "PTA_RXD"),
9612 + MTK_FUNCTION(5, "CONN_MCU_DBGACK_N"),
9613 + MTK_FUNCTION(6, "PWM_B"),
9614 + MTK_FUNCTION(7, "PCC_PPC_IO")
9615 + ),
9616 + MTK_PIN(
9617 + 36, "GPIO36",
9618 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
9619 + DRV_GRP3,
9620 + MTK_FUNCTION(0, "GPIO36"),
9621 + MTK_FUNCTION(1, "CMMCLK2"),
9622 + MTK_FUNCTION(2, "CLKM2"),
9623 + MTK_FUNCTION(3, "MD_UTXD1"),
9624 + MTK_FUNCTION(4, "PTA_TXD"),
9625 + MTK_FUNCTION(5, "CONN_MCU_DBGI_N"),
9626 + MTK_FUNCTION(6, "PWM_C"),
9627 + MTK_FUNCTION(7, "EXT_FRAME_SYNC")
9628 + ),
9629 + MTK_PIN(
9630 + 37, "GPIO37",
9631 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
9632 + DRV_GRP3,
9633 + MTK_FUNCTION(0, "GPIO37"),
9634 + MTK_FUNCTION(1, "SCL0_0")
9635 + ),
9636 + MTK_PIN(
9637 + 38, "GPIO38",
9638 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
9639 + DRV_GRP3,
9640 + MTK_FUNCTION(0, "GPIO38"),
9641 + MTK_FUNCTION(1, "SDA0_0")
9642 + ),
9643 + MTK_PIN(
9644 + 39, "GPIO39",
9645 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
9646 + DRV_GRP3,
9647 + MTK_FUNCTION(0, "GPIO39"),
9648 + MTK_FUNCTION(1, "DPI_D0"),
9649 + MTK_FUNCTION(2, "SPI1_CLK_A"),
9650 + MTK_FUNCTION(3, "PCM0_SYNC"),
9651 + MTK_FUNCTION(4, "I2S0_LRCK"),
9652 + MTK_FUNCTION(5, "CONN_MCU_TRST_B"),
9653 + MTK_FUNCTION(6, "URXD3"),
9654 + MTK_FUNCTION(7, "C2K_NTRST")
9655 + ),
9656 + MTK_PIN(
9657 + 40, "GPIO40",
9658 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
9659 + DRV_GRP3,
9660 + MTK_FUNCTION(0, "GPIO40"),
9661 + MTK_FUNCTION(1, "DPI_D1"),
9662 + MTK_FUNCTION(2, "SPI1_MI_A"),
9663 + MTK_FUNCTION(3, "PCM0_CLK"),
9664 + MTK_FUNCTION(4, "I2S0_BCK"),
9665 + MTK_FUNCTION(5, "CONN_MCU_TDO"),
9666 + MTK_FUNCTION(6, "UTXD3"),
9667 + MTK_FUNCTION(7, "C2K_TCK")
9668 + ),
9669 + MTK_PIN(
9670 + 41, "GPIO41",
9671 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
9672 + DRV_GRP3,
9673 + MTK_FUNCTION(0, "GPIO41"),
9674 + MTK_FUNCTION(1, "DPI_D2"),
9675 + MTK_FUNCTION(2, "SPI1_CS_A"),
9676 + MTK_FUNCTION(3, "PCM0_DO"),
9677 + MTK_FUNCTION(4, "I2S3_DO"),
9678 + MTK_FUNCTION(5, "CONN_MCU_DBGACK_N"),
9679 + MTK_FUNCTION(6, "URTS3"),
9680 + MTK_FUNCTION(7, "C2K_TDI")
9681 + ),
9682 + MTK_PIN(
9683 + 42, "GPIO42",
9684 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
9685 + DRV_GRP3,
9686 + MTK_FUNCTION(0, "GPIO42"),
9687 + MTK_FUNCTION(1, "DPI_D3"),
9688 + MTK_FUNCTION(2, "SPI1_MO_A"),
9689 + MTK_FUNCTION(3, "PCM0_DI"),
9690 + MTK_FUNCTION(4, "I2S0_DI"),
9691 + MTK_FUNCTION(5, "CONN_MCU_TDI"),
9692 + MTK_FUNCTION(6, "UCTS3"),
9693 + MTK_FUNCTION(7, "C2K_TMS")
9694 + ),
9695 + MTK_PIN(
9696 + 43, "GPIO43",
9697 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
9698 + DRV_GRP3,
9699 + MTK_FUNCTION(0, "GPIO43"),
9700 + MTK_FUNCTION(1, "DPI_D4"),
9701 + MTK_FUNCTION(2, "SPI2_CLK_A"),
9702 + MTK_FUNCTION(3, "PCM1_SYNC"),
9703 + MTK_FUNCTION(4, "I2S2_LRCK"),
9704 + MTK_FUNCTION(5, "CONN_MCU_TMS"),
9705 + MTK_FUNCTION(6, "CONN_MCU_AICE_TMSC"),
9706 + MTK_FUNCTION(7, "C2K_TDO")
9707 + ),
9708 + MTK_PIN(
9709 + 44, "GPIO44",
9710 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
9711 + DRV_GRP3,
9712 + MTK_FUNCTION(0, "GPIO44"),
9713 + MTK_FUNCTION(1, "DPI_D5"),
9714 + MTK_FUNCTION(2, "SPI2_MI_A"),
9715 + MTK_FUNCTION(3, "PCM1_CLK"),
9716 + MTK_FUNCTION(4, "I2S2_BCK"),
9717 + MTK_FUNCTION(5, "CONN_MCU_TCK"),
9718 + MTK_FUNCTION(6, "CONN_MCU_AICE_TCKC"),
9719 + MTK_FUNCTION(7, "C2K_RTCK")
9720 + ),
9721 + MTK_PIN(
9722 + 45, "GPIO45",
9723 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
9724 + DRV_GRP3,
9725 + MTK_FUNCTION(0, "GPIO45"),
9726 + MTK_FUNCTION(1, "DPI_D6"),
9727 + MTK_FUNCTION(2, "SPI2_CS_A"),
9728 + MTK_FUNCTION(3, "PCM1_DI"),
9729 + MTK_FUNCTION(4, "I2S2_DI"),
9730 + MTK_FUNCTION(5, "CONN_MCU_DBGI_N"),
9731 + MTK_FUNCTION(6, "MD_URXD0")
9732 + ),
9733 + MTK_PIN(
9734 + 46, "GPIO46",
9735 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
9736 + DRV_GRP3,
9737 + MTK_FUNCTION(0, "GPIO46"),
9738 + MTK_FUNCTION(1, "DPI_D7"),
9739 + MTK_FUNCTION(2, "SPI2_MO_A"),
9740 + MTK_FUNCTION(3, "PCM1_DO0"),
9741 + MTK_FUNCTION(4, "I2S1_DO"),
9742 + MTK_FUNCTION(5, "ANT_SEL0"),
9743 + MTK_FUNCTION(6, "MD_UTXD0")
9744 + ),
9745 + MTK_PIN(
9746 + 47, "GPIO47",
9747 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
9748 + DRV_GRP3,
9749 + MTK_FUNCTION(0, "GPIO47"),
9750 + MTK_FUNCTION(1, "DPI_D8"),
9751 + MTK_FUNCTION(2, "CLKM0"),
9752 + MTK_FUNCTION(3, "PCM1_DO1"),
9753 + MTK_FUNCTION(4, "I2S0_MCK"),
9754 + MTK_FUNCTION(5, "ANT_SEL1"),
9755 + MTK_FUNCTION(6, "PTA_RXD"),
9756 + MTK_FUNCTION(7, "C2K_URXD0")
9757 + ),
9758 + MTK_PIN(
9759 + 48, "GPIO48",
9760 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
9761 + DRV_GRP3,
9762 + MTK_FUNCTION(0, "GPIO48"),
9763 + MTK_FUNCTION(1, "DPI_D9"),
9764 + MTK_FUNCTION(2, "CLKM1"),
9765 + MTK_FUNCTION(3, "CMFLASH"),
9766 + MTK_FUNCTION(4, "I2S2_MCK"),
9767 + MTK_FUNCTION(5, "ANT_SEL2"),
9768 + MTK_FUNCTION(6, "PTA_TXD"),
9769 + MTK_FUNCTION(7, "C2K_UTXD0")
9770 + ),
9771 + MTK_PIN(
9772 + 49, "GPIO49",
9773 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
9774 + DRV_GRP3,
9775 + MTK_FUNCTION(0, "GPIO49"),
9776 + MTK_FUNCTION(1, "DPI_D10"),
9777 + MTK_FUNCTION(2, "MD_INT1_C2K_UIM1_HOT_PLUG_IN"),
9778 + MTK_FUNCTION(3, "PWM_C"),
9779 + MTK_FUNCTION(4, "IRTX_OUT"),
9780 + MTK_FUNCTION(5, "ANT_SEL3"),
9781 + MTK_FUNCTION(6, "MD_URXD1")
9782 + ),
9783 + MTK_PIN(
9784 + 50, "GPIO50",
9785 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
9786 + DRV_GRP3,
9787 + MTK_FUNCTION(0, "GPIO50"),
9788 + MTK_FUNCTION(1, "DPI_D11"),
9789 + MTK_FUNCTION(2, "MD_INT2"),
9790 + MTK_FUNCTION(3, "PWM_D"),
9791 + MTK_FUNCTION(4, "CLKM2"),
9792 + MTK_FUNCTION(5, "ANT_SEL4"),
9793 + MTK_FUNCTION(6, "MD_UTXD1")
9794 + ),
9795 + MTK_PIN(
9796 + 51, "GPIO51",
9797 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
9798 + DRV_GRP3,
9799 + MTK_FUNCTION(0, "GPIO51"),
9800 + MTK_FUNCTION(1, "DPI_DE"),
9801 + MTK_FUNCTION(2, "SPI4_CLK_A"),
9802 + MTK_FUNCTION(3, "IRTX_OUT"),
9803 + MTK_FUNCTION(4, "SCL0_1"),
9804 + MTK_FUNCTION(5, "ANT_SEL5"),
9805 + MTK_FUNCTION(7, "C2K_UTXD1")
9806 + ),
9807 + MTK_PIN(
9808 + 52, "GPIO52",
9809 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
9810 + DRV_GRP3,
9811 + MTK_FUNCTION(0, "GPIO52"),
9812 + MTK_FUNCTION(1, "DPI_CK"),
9813 + MTK_FUNCTION(2, "SPI4_MI_A"),
9814 + MTK_FUNCTION(3, "SPI4_MO_A"),
9815 + MTK_FUNCTION(4, "SDA0_1"),
9816 + MTK_FUNCTION(5, "ANT_SEL6"),
9817 + MTK_FUNCTION(7, "C2K_URXD1")
9818 + ),
9819 + MTK_PIN(
9820 + 53, "GPIO53",
9821 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
9822 + DRV_GRP3,
9823 + MTK_FUNCTION(0, "GPIO53"),
9824 + MTK_FUNCTION(1, "DPI_HSYNC"),
9825 + MTK_FUNCTION(2, "SPI4_CS_A"),
9826 + MTK_FUNCTION(3, "CMFLASH"),
9827 + MTK_FUNCTION(4, "SCL1_1"),
9828 + MTK_FUNCTION(5, "ANT_SEL7"),
9829 + MTK_FUNCTION(6, "MD_URXD2"),
9830 + MTK_FUNCTION(7, "PCC_PPC_IO")
9831 + ),
9832 + MTK_PIN(
9833 + 54, "GPIO54",
9834 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
9835 + DRV_GRP3,
9836 + MTK_FUNCTION(0, "GPIO54"),
9837 + MTK_FUNCTION(1, "DPI_VSYNC"),
9838 + MTK_FUNCTION(2, "SPI4_MO_A"),
9839 + MTK_FUNCTION(3, "SPI4_MI_A"),
9840 + MTK_FUNCTION(4, "SDA1_1"),
9841 + MTK_FUNCTION(5, "PWM_A"),
9842 + MTK_FUNCTION(6, "MD_UTXD2"),
9843 + MTK_FUNCTION(7, "EXT_FRAME_SYNC")
9844 + ),
9845 + MTK_PIN(
9846 + 55, "GPIO55",
9847 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
9848 + DRV_GRP3,
9849 + MTK_FUNCTION(0, "GPIO55"),
9850 + MTK_FUNCTION(1, "SCL1_0")
9851 + ),
9852 + MTK_PIN(
9853 + 56, "GPIO56",
9854 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
9855 + DRV_GRP3,
9856 + MTK_FUNCTION(0, "GPIO56"),
9857 + MTK_FUNCTION(1, "SDA1_0")
9858 + ),
9859 + MTK_PIN(
9860 + 57, "GPIO57",
9861 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
9862 + DRV_GRP3,
9863 + MTK_FUNCTION(0, "GPIO57"),
9864 + MTK_FUNCTION(1, "SPI0_CLK"),
9865 + MTK_FUNCTION(2, "SCL0_2"),
9866 + MTK_FUNCTION(3, "PWM_B"),
9867 + MTK_FUNCTION(4, "UTXD3"),
9868 + MTK_FUNCTION(5, "PCM0_SYNC")
9869 + ),
9870 + MTK_PIN(
9871 + 58, "GPIO58",
9872 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
9873 + DRV_GRP3,
9874 + MTK_FUNCTION(0, "GPIO58"),
9875 + MTK_FUNCTION(1, "SPI0_MI"),
9876 + MTK_FUNCTION(2, "SPI0_MO"),
9877 + MTK_FUNCTION(3, "SDA1_2"),
9878 + MTK_FUNCTION(4, "URXD3"),
9879 + MTK_FUNCTION(5, "PCM0_CLK")
9880 + ),
9881 + MTK_PIN(
9882 + 59, "GPIO59",
9883 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
9884 + DRV_GRP3,
9885 + MTK_FUNCTION(0, "GPIO59"),
9886 + MTK_FUNCTION(1, "SPI0_MO"),
9887 + MTK_FUNCTION(2, "SPI0_MI"),
9888 + MTK_FUNCTION(3, "PWM_C"),
9889 + MTK_FUNCTION(4, "URTS3"),
9890 + MTK_FUNCTION(5, "PCM0_DO")
9891 + ),
9892 + MTK_PIN(
9893 + 60, "GPIO60",
9894 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
9895 + DRV_GRP3,
9896 + MTK_FUNCTION(0, "GPIO60"),
9897 + MTK_FUNCTION(1, "SPI0_CS"),
9898 + MTK_FUNCTION(2, "SDA0_2"),
9899 + MTK_FUNCTION(3, "SCL1_2"),
9900 + MTK_FUNCTION(4, "UCTS3"),
9901 + MTK_FUNCTION(5, "PCM0_DI")
9902 + ),
9903 + MTK_PIN(
9904 + 61, "GPIO61",
9905 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
9906 + DRV_GRP3,
9907 + MTK_FUNCTION(0, "GPIO61"),
9908 + MTK_FUNCTION(1, "EINT0"),
9909 + MTK_FUNCTION(2, "IDDIG"),
9910 + MTK_FUNCTION(3, "SPI4_CLK_B"),
9911 + MTK_FUNCTION(4, "I2S0_LRCK"),
9912 + MTK_FUNCTION(5, "PCM0_SYNC"),
9913 + MTK_FUNCTION(7, "C2K_EINT0")
9914 + ),
9915 + MTK_PIN(
9916 + 62, "GPIO62",
9917 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
9918 + DRV_GRP3,
9919 + MTK_FUNCTION(0, "GPIO62"),
9920 + MTK_FUNCTION(1, "EINT1"),
9921 + MTK_FUNCTION(2, "USB_DRVVBUS"),
9922 + MTK_FUNCTION(3, "SPI4_MI_B"),
9923 + MTK_FUNCTION(4, "I2S0_BCK"),
9924 + MTK_FUNCTION(5, "PCM0_CLK"),
9925 + MTK_FUNCTION(7, "C2K_EINT1")
9926 + ),
9927 + MTK_PIN(
9928 + 63, "GPIO63",
9929 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
9930 + DRV_GRP3,
9931 + MTK_FUNCTION(0, "GPIO63"),
9932 + MTK_FUNCTION(1, "EINT2"),
9933 + MTK_FUNCTION(2, "IRTX_OUT"),
9934 + MTK_FUNCTION(3, "SPI4_MO_B"),
9935 + MTK_FUNCTION(4, "I2S0_MCK"),
9936 + MTK_FUNCTION(5, "PCM0_DI"),
9937 + MTK_FUNCTION(7, "C2K_DM_EINT0")
9938 + ),
9939 + MTK_PIN(
9940 + 64, "GPIO64",
9941 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
9942 + DRV_GRP3,
9943 + MTK_FUNCTION(0, "GPIO64"),
9944 + MTK_FUNCTION(1, "EINT3"),
9945 + MTK_FUNCTION(2, "CMFLASH"),
9946 + MTK_FUNCTION(3, "SPI4_CS_B"),
9947 + MTK_FUNCTION(4, "I2S0_DI"),
9948 + MTK_FUNCTION(5, "PCM0_DO"),
9949 + MTK_FUNCTION(7, "C2K_DM_EINT1")
9950 + ),
9951 + MTK_PIN(
9952 + 65, "GPIO65",
9953 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
9954 + DRV_GRP3,
9955 + MTK_FUNCTION(0, "GPIO65"),
9956 + MTK_FUNCTION(1, "EINT4"),
9957 + MTK_FUNCTION(2, "CLKM0"),
9958 + MTK_FUNCTION(3, "SPI5_CLK_B"),
9959 + MTK_FUNCTION(4, "I2S1_LRCK"),
9960 + MTK_FUNCTION(5, "PWM_A"),
9961 + MTK_FUNCTION(7, "C2K_DM_EINT2")
9962 + ),
9963 + MTK_PIN(
9964 + 66, "GPIO66",
9965 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
9966 + DRV_GRP3,
9967 + MTK_FUNCTION(0, "GPIO66"),
9968 + MTK_FUNCTION(1, "EINT5"),
9969 + MTK_FUNCTION(2, "CLKM1"),
9970 + MTK_FUNCTION(3, "SPI5_MI_B"),
9971 + MTK_FUNCTION(4, "I2S1_BCK"),
9972 + MTK_FUNCTION(5, "PWM_B"),
9973 + MTK_FUNCTION(7, "C2K_DM_EINT3")
9974 + ),
9975 + MTK_PIN(
9976 + 67, "GPIO67",
9977 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
9978 + DRV_GRP3,
9979 + MTK_FUNCTION(0, "GPIO67"),
9980 + MTK_FUNCTION(1, "EINT6"),
9981 + MTK_FUNCTION(2, "CLKM2"),
9982 + MTK_FUNCTION(3, "SPI5_MO_B"),
9983 + MTK_FUNCTION(4, "I2S1_MCK"),
9984 + MTK_FUNCTION(5, "PWM_C"),
9985 + MTK_FUNCTION(7, "DBG_MON_A0")
9986 + ),
9987 + MTK_PIN(
9988 + 68, "GPIO68",
9989 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
9990 + DRV_GRP3,
9991 + MTK_FUNCTION(0, "GPIO68"),
9992 + MTK_FUNCTION(1, "EINT7"),
9993 + MTK_FUNCTION(2, "CLKM3"),
9994 + MTK_FUNCTION(3, "SPI5_CS_B"),
9995 + MTK_FUNCTION(4, "I2S1_DO"),
9996 + MTK_FUNCTION(5, "PWM_D"),
9997 + MTK_FUNCTION(7, "DBG_MON_A1")
9998 + ),
9999 + MTK_PIN(
10000 + 69, "GPIO69",
10001 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
10002 + DRV_GRP3,
10003 + MTK_FUNCTION(0, "GPIO69"),
10004 + MTK_FUNCTION(1, "I2S0_LRCK"),
10005 + MTK_FUNCTION(2, "I2S3_LRCK"),
10006 + MTK_FUNCTION(3, "I2S1_LRCK"),
10007 + MTK_FUNCTION(4, "I2S2_LRCK"),
10008 + MTK_FUNCTION(7, "DBG_MON_A2")
10009 + ),
10010 + MTK_PIN(
10011 + 70, "GPIO70",
10012 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
10013 + DRV_GRP3,
10014 + MTK_FUNCTION(0, "GPIO70"),
10015 + MTK_FUNCTION(1, "I2S0_BCK"),
10016 + MTK_FUNCTION(2, "I2S3_BCK"),
10017 + MTK_FUNCTION(3, "I2S1_BCK"),
10018 + MTK_FUNCTION(4, "I2S2_BCK"),
10019 + MTK_FUNCTION(7, "DBG_MON_A3")
10020 + ),
10021 + MTK_PIN(
10022 + 71, "GPIO71",
10023 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
10024 + DRV_GRP3,
10025 + MTK_FUNCTION(0, "GPIO71"),
10026 + MTK_FUNCTION(1, "I2S0_MCK"),
10027 + MTK_FUNCTION(2, "I2S3_MCK"),
10028 + MTK_FUNCTION(3, "I2S1_MCK"),
10029 + MTK_FUNCTION(4, "I2S2_MCK"),
10030 + MTK_FUNCTION(7, "DBG_MON_A4")
10031 + ),
10032 + MTK_PIN(
10033 + 72, "GPIO72",
10034 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
10035 + DRV_GRP3,
10036 + MTK_FUNCTION(0, "GPIO72"),
10037 + MTK_FUNCTION(1, "I2S0_DI"),
10038 + MTK_FUNCTION(2, "I2S0_DI"),
10039 + MTK_FUNCTION(3, "I2S2_DI"),
10040 + MTK_FUNCTION(4, "I2S2_DI"),
10041 + MTK_FUNCTION(7, "DBG_MON_A5")
10042 + ),
10043 + MTK_PIN(
10044 + 73, "GPIO73",
10045 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
10046 + DRV_GRP3,
10047 + MTK_FUNCTION(0, "GPIO73"),
10048 + MTK_FUNCTION(1, "I2S3_DO"),
10049 + MTK_FUNCTION(2, "I2S3_DO"),
10050 + MTK_FUNCTION(3, "I2S1_DO"),
10051 + MTK_FUNCTION(4, "I2S1_DO"),
10052 + MTK_FUNCTION(7, "DBG_MON_A6")
10053 + ),
10054 + MTK_PIN(
10055 + 74, "GPIO74",
10056 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
10057 + DRV_GRP3,
10058 + MTK_FUNCTION(0, "GPIO74"),
10059 + MTK_FUNCTION(1, "SCL3_0"),
10060 + MTK_FUNCTION(7, "AUXIF_CLK1")
10061 + ),
10062 + MTK_PIN(
10063 + 75, "GPIO75",
10064 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
10065 + DRV_GRP3,
10066 + MTK_FUNCTION(0, "GPIO75"),
10067 + MTK_FUNCTION(1, "SDA3_0"),
10068 + MTK_FUNCTION(7, "AUXIF_ST1")
10069 + ),
10070 + MTK_PIN(
10071 + 76, "GPIO76",
10072 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
10073 + DRV_GRP3,
10074 + MTK_FUNCTION(0, "GPIO76"),
10075 + MTK_FUNCTION(1, "CONN_HRST_B"),
10076 + MTK_FUNCTION(7, "C2K_DM_EINT0")
10077 + ),
10078 + MTK_PIN(
10079 + 77, "GPIO77",
10080 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
10081 + DRV_GRP3,
10082 + MTK_FUNCTION(0, "GPIO77"),
10083 + MTK_FUNCTION(1, "CONN_TOP_CLK"),
10084 + MTK_FUNCTION(7, "C2K_DM_EINT1")
10085 + ),
10086 + MTK_PIN(
10087 + 78, "GPIO78",
10088 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
10089 + DRV_GRP3,
10090 + MTK_FUNCTION(0, "GPIO78"),
10091 + MTK_FUNCTION(1, "CONN_TOP_DATA"),
10092 + MTK_FUNCTION(7, "C2K_DM_EINT2")
10093 + ),
10094 + MTK_PIN(
10095 + 79, "GPIO79",
10096 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
10097 + DRV_GRP3,
10098 + MTK_FUNCTION(0, "GPIO79"),
10099 + MTK_FUNCTION(1, "CONN_WB_PTA"),
10100 + MTK_FUNCTION(7, "C2K_DM_EINT3")
10101 + ),
10102 + MTK_PIN(
10103 + 80, "GPIO80",
10104 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
10105 + DRV_GRP3,
10106 + MTK_FUNCTION(0, "GPIO80"),
10107 + MTK_FUNCTION(1, "CONN_WF_HB0"),
10108 + MTK_FUNCTION(7, "C2K_EINT0")
10109 + ),
10110 + MTK_PIN(
10111 + 81, "GPIO81",
10112 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
10113 + DRV_GRP3,
10114 + MTK_FUNCTION(0, "GPIO81"),
10115 + MTK_FUNCTION(1, "CONN_WF_HB1"),
10116 + MTK_FUNCTION(7, "C2K_EINT1")
10117 + ),
10118 + MTK_PIN(
10119 + 82, "GPIO82",
10120 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
10121 + DRV_GRP3,
10122 + MTK_FUNCTION(0, "GPIO82"),
10123 + MTK_FUNCTION(1, "CONN_WF_HB2"),
10124 + MTK_FUNCTION(7, "MD_CLKM0")
10125 + ),
10126 + MTK_PIN(
10127 + 83, "GPIO83",
10128 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
10129 + DRV_GRP3,
10130 + MTK_FUNCTION(0, "GPIO83"),
10131 + MTK_FUNCTION(1, "CONN_BT_CLK"),
10132 + MTK_FUNCTION(7, "MD_CLKM1")
10133 + ),
10134 + MTK_PIN(
10135 + 84, "GPIO84",
10136 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
10137 + DRV_GRP3,
10138 + MTK_FUNCTION(0, "GPIO84"),
10139 + MTK_FUNCTION(1, "CONN_BT_DATA")
10140 + ),
10141 + MTK_PIN(
10142 + 85, "GPIO85",
10143 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
10144 + DRV_GRP3,
10145 + MTK_FUNCTION(0, "GPIO85"),
10146 + MTK_FUNCTION(1, "EINT8"),
10147 + MTK_FUNCTION(2, "I2S1_LRCK"),
10148 + MTK_FUNCTION(3, "I2S2_LRCK"),
10149 + MTK_FUNCTION(4, "URXD1"),
10150 + MTK_FUNCTION(5, "MD_URXD0"),
10151 + MTK_FUNCTION(7, "DBG_MON_A7")
10152 + ),
10153 + MTK_PIN(
10154 + 86, "GPIO86",
10155 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
10156 + DRV_GRP3,
10157 + MTK_FUNCTION(0, "GPIO86"),
10158 + MTK_FUNCTION(1, "EINT9"),
10159 + MTK_FUNCTION(2, "I2S1_BCK"),
10160 + MTK_FUNCTION(3, "I2S2_BCK"),
10161 + MTK_FUNCTION(4, "UTXD1"),
10162 + MTK_FUNCTION(5, "MD_UTXD0"),
10163 + MTK_FUNCTION(7, "DBG_MON_A8")
10164 + ),
10165 + MTK_PIN(
10166 + 87, "GPIO87",
10167 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
10168 + DRV_GRP3,
10169 + MTK_FUNCTION(0, "GPIO87"),
10170 + MTK_FUNCTION(1, "EINT10"),
10171 + MTK_FUNCTION(2, "I2S1_MCK"),
10172 + MTK_FUNCTION(3, "I2S2_MCK"),
10173 + MTK_FUNCTION(4, "URTS1"),
10174 + MTK_FUNCTION(5, "MD_URXD1"),
10175 + MTK_FUNCTION(7, "DBG_MON_A9")
10176 + ),
10177 + MTK_PIN(
10178 + 88, "GPIO88",
10179 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
10180 + DRV_GRP3,
10181 + MTK_FUNCTION(0, "GPIO88"),
10182 + MTK_FUNCTION(1, "EINT11"),
10183 + MTK_FUNCTION(2, "I2S1_DO"),
10184 + MTK_FUNCTION(3, "I2S2_DI"),
10185 + MTK_FUNCTION(4, "UCTS1"),
10186 + MTK_FUNCTION(5, "MD_UTXD1"),
10187 + MTK_FUNCTION(7, "DBG_MON_A10")
10188 + ),
10189 + MTK_PIN(
10190 + 89, "GPIO89",
10191 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
10192 + DRV_GRP3,
10193 + MTK_FUNCTION(0, "GPIO89"),
10194 + MTK_FUNCTION(1, "EINT12"),
10195 + MTK_FUNCTION(2, "IRTX_OUT"),
10196 + MTK_FUNCTION(3, "CLKM0"),
10197 + MTK_FUNCTION(4, "PCM1_SYNC"),
10198 + MTK_FUNCTION(5, "URTS0"),
10199 + MTK_FUNCTION(7, "DBG_MON_A11")
10200 + ),
10201 + MTK_PIN(
10202 + 90, "GPIO90",
10203 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
10204 + DRV_GRP3,
10205 + MTK_FUNCTION(0, "GPIO90"),
10206 + MTK_FUNCTION(1, "EINT13"),
10207 + MTK_FUNCTION(2, "CMFLASH"),
10208 + MTK_FUNCTION(3, "CLKM1"),
10209 + MTK_FUNCTION(4, "PCM1_CLK"),
10210 + MTK_FUNCTION(5, "UCTS0"),
10211 + MTK_FUNCTION(7, "C2K_DM_EINT0")
10212 + ),
10213 + MTK_PIN(
10214 + 91, "GPIO91",
10215 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
10216 + DRV_GRP3,
10217 + MTK_FUNCTION(0, "GPIO91"),
10218 + MTK_FUNCTION(1, "EINT14"),
10219 + MTK_FUNCTION(2, "PWM_A"),
10220 + MTK_FUNCTION(3, "CLKM2"),
10221 + MTK_FUNCTION(4, "PCM1_DI"),
10222 + MTK_FUNCTION(5, "SDA0_3"),
10223 + MTK_FUNCTION(7, "C2K_DM_EINT1")
10224 + ),
10225 + MTK_PIN(
10226 + 92, "GPIO92",
10227 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
10228 + DRV_GRP3,
10229 + MTK_FUNCTION(0, "GPIO92"),
10230 + MTK_FUNCTION(1, "EINT15"),
10231 + MTK_FUNCTION(2, "PWM_B"),
10232 + MTK_FUNCTION(3, "CLKM3"),
10233 + MTK_FUNCTION(4, "PCM1_DO0"),
10234 + MTK_FUNCTION(5, "SCL0_3")
10235 + ),
10236 + MTK_PIN(
10237 + 93, "GPIO93",
10238 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
10239 + DRV_GRP3,
10240 + MTK_FUNCTION(0, "GPIO93"),
10241 + MTK_FUNCTION(1, "EINT16"),
10242 + MTK_FUNCTION(2, "IDDIG"),
10243 + MTK_FUNCTION(3, "CLKM4"),
10244 + MTK_FUNCTION(4, "PCM1_DO1"),
10245 + MTK_FUNCTION(5, "MD_INT2"),
10246 + MTK_FUNCTION(7, "DROP_ZONE")
10247 + ),
10248 + MTK_PIN(
10249 + 94, "GPIO94",
10250 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
10251 + DRV_GRP3,
10252 + MTK_FUNCTION(0, "GPIO94"),
10253 + MTK_FUNCTION(1, "USB_DRVVBUS"),
10254 + MTK_FUNCTION(2, "PWM_C"),
10255 + MTK_FUNCTION(3, "CLKM5")
10256 + ),
10257 + MTK_PIN(
10258 + 95, "GPIO95",
10259 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
10260 + DRV_GRP3,
10261 + MTK_FUNCTION(0, "GPIO95"),
10262 + MTK_FUNCTION(1, "SDA2_0"),
10263 + MTK_FUNCTION(7, "AUXIF_ST0")
10264 + ),
10265 + MTK_PIN(
10266 + 96, "GPIO96",
10267 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
10268 + DRV_GRP3,
10269 + MTK_FUNCTION(0, "GPIO96"),
10270 + MTK_FUNCTION(1, "SCL2_0"),
10271 + MTK_FUNCTION(7, "AUXIF_CLK0")
10272 + ),
10273 + MTK_PIN(
10274 + 97, "GPIO97",
10275 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
10276 + DRV_GRP3,
10277 + MTK_FUNCTION(0, "GPIO97"),
10278 + MTK_FUNCTION(1, "URXD0"),
10279 + MTK_FUNCTION(2, "UTXD0"),
10280 + MTK_FUNCTION(3, "MD_URXD0"),
10281 + MTK_FUNCTION(4, "MD_URXD1"),
10282 + MTK_FUNCTION(5, "MD_URXD2"),
10283 + MTK_FUNCTION(6, "C2K_URXD0"),
10284 + MTK_FUNCTION(7, "C2K_URXD1")
10285 + ),
10286 + MTK_PIN(
10287 + 98, "GPIO98",
10288 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
10289 + DRV_GRP3,
10290 + MTK_FUNCTION(0, "GPIO98"),
10291 + MTK_FUNCTION(1, "UTXD0"),
10292 + MTK_FUNCTION(2, "URXD0"),
10293 + MTK_FUNCTION(3, "MD_UTXD0"),
10294 + MTK_FUNCTION(4, "MD_UTXD1"),
10295 + MTK_FUNCTION(5, "MD_UTXD2"),
10296 + MTK_FUNCTION(6, "C2K_UTXD0"),
10297 + MTK_FUNCTION(7, "C2K_UTXD1")
10298 + ),
10299 + MTK_PIN(
10300 + 99, "GPIO99",
10301 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
10302 + DRV_GRP3,
10303 + MTK_FUNCTION(0, "GPIO99"),
10304 + MTK_FUNCTION(1, "RTC32K_CK")
10305 + ),
10306 + MTK_PIN(
10307 + 100, "GPIO100",
10308 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
10309 + DRV_GRP3,
10310 + MTK_FUNCTION(0, "GPIO100"),
10311 + MTK_FUNCTION(1, "SRCLKENAI0")
10312 + ),
10313 + MTK_PIN(
10314 + 101, "GPIO101",
10315 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
10316 + DRV_GRP3,
10317 + MTK_FUNCTION(0, "GPIO101"),
10318 + MTK_FUNCTION(1, "SRCLKENAI1")
10319 + ),
10320 + MTK_PIN(
10321 + 102, "GPIO102",
10322 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
10323 + DRV_GRP3,
10324 + MTK_FUNCTION(0, "GPIO102"),
10325 + MTK_FUNCTION(1, "SRCLKENA0")
10326 + ),
10327 + MTK_PIN(
10328 + 103, "GPIO103",
10329 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
10330 + DRV_GRP3,
10331 + MTK_FUNCTION(0, "GPIO103"),
10332 + MTK_FUNCTION(1, "SRCLKENA1")
10333 + ),
10334 + MTK_PIN(
10335 + 104, "GPIO104",
10336 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
10337 + DRV_GRP3,
10338 + MTK_FUNCTION(0, "GPIO104"),
10339 + MTK_FUNCTION(1, "SYSRSTB")
10340 + ),
10341 + MTK_PIN(
10342 + 105, "GPIO105",
10343 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
10344 + DRV_GRP3,
10345 + MTK_FUNCTION(0, "GPIO105"),
10346 + MTK_FUNCTION(1, "WATCHDOG")
10347 + ),
10348 + MTK_PIN(
10349 + 106, "GPIO106",
10350 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
10351 + DRV_GRP3,
10352 + MTK_FUNCTION(0, "GPIO106"),
10353 + MTK_FUNCTION(1, "KPROW0"),
10354 + MTK_FUNCTION(2, "CMFLASH"),
10355 + MTK_FUNCTION(3, "CLKM4"),
10356 + MTK_FUNCTION(4, "TP_GPIO0_AO"),
10357 + MTK_FUNCTION(5, "IRTX_OUT")
10358 + ),
10359 + MTK_PIN(
10360 + 107, "GPIO107",
10361 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
10362 + DRV_GRP3,
10363 + MTK_FUNCTION(0, "GPIO107"),
10364 + MTK_FUNCTION(1, "KPROW1"),
10365 + MTK_FUNCTION(2, "IDDIG"),
10366 + MTK_FUNCTION(3, "CLKM5"),
10367 + MTK_FUNCTION(4, "TP_GPIO1_AO"),
10368 + MTK_FUNCTION(5, "I2S1_BCK"),
10369 + MTK_FUNCTION(7, "DAP_SIB1_SWD")
10370 + ),
10371 + MTK_PIN(
10372 + 108, "GPIO108",
10373 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
10374 + DRV_GRP3,
10375 + MTK_FUNCTION(0, "GPIO108"),
10376 + MTK_FUNCTION(1, "KPROW2"),
10377 + MTK_FUNCTION(2, "USB_DRVVBUS"),
10378 + MTK_FUNCTION(3, "PWM_A"),
10379 + MTK_FUNCTION(4, "CMFLASH"),
10380 + MTK_FUNCTION(5, "I2S1_LRCK"),
10381 + MTK_FUNCTION(7, "DAP_SIB1_SWCK")
10382 + ),
10383 + MTK_PIN(
10384 + 109, "GPIO109",
10385 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
10386 + DRV_GRP3,
10387 + MTK_FUNCTION(0, "GPIO109"),
10388 + MTK_FUNCTION(1, "KPCOL0")
10389 + ),
10390 + MTK_PIN(
10391 + 110, "GPIO110",
10392 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
10393 + DRV_GRP3,
10394 + MTK_FUNCTION(0, "GPIO110"),
10395 + MTK_FUNCTION(1, "KPCOL1"),
10396 + MTK_FUNCTION(2, "SDA1_3"),
10397 + MTK_FUNCTION(3, "PWM_B"),
10398 + MTK_FUNCTION(4, "CLKM0"),
10399 + MTK_FUNCTION(5, "I2S1_DO"),
10400 + MTK_FUNCTION(7, "C2K_DM_EINT3")
10401 + ),
10402 + MTK_PIN(
10403 + 111, "GPIO111",
10404 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
10405 + DRV_GRP3,
10406 + MTK_FUNCTION(0, "GPIO111"),
10407 + MTK_FUNCTION(1, "KPCOL2"),
10408 + MTK_FUNCTION(2, "SCL1_3"),
10409 + MTK_FUNCTION(3, "PWM_C"),
10410 + MTK_FUNCTION(4, "DISP_PWM"),
10411 + MTK_FUNCTION(5, "I2S1_MCK"),
10412 + MTK_FUNCTION(7, "C2K_DM_EINT2")
10413 + ),
10414 + MTK_PIN(
10415 + 112, "GPIO112",
10416 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
10417 + DRV_GRP3,
10418 + MTK_FUNCTION(0, "GPIO112"),
10419 + MTK_FUNCTION(1, "MD_INT1_C2K_UIM1_HOT_PLUG_IN"),
10420 + MTK_FUNCTION(7, "C2K_DM_EINT1")
10421 + ),
10422 + MTK_PIN(
10423 + 113, "GPIO113",
10424 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
10425 + DRV_GRP3,
10426 + MTK_FUNCTION(0, "GPIO113"),
10427 + MTK_FUNCTION(1, "MD_INT0_C2K_UIM0_HOT_PLUG_IN"),
10428 + MTK_FUNCTION(7, "C2K_DM_EINT0")
10429 + ),
10430 + MTK_PIN(
10431 + 114, "GPIO114",
10432 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
10433 + DRV_GRP3,
10434 + MTK_FUNCTION(0, "GPIO114"),
10435 + MTK_FUNCTION(1, "MSDC0_DAT0")
10436 + ),
10437 + MTK_PIN(
10438 + 115, "GPIO115",
10439 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
10440 + DRV_GRP3,
10441 + MTK_FUNCTION(0, "GPIO115"),
10442 + MTK_FUNCTION(1, "MSDC0_DAT1")
10443 + ),
10444 + MTK_PIN(
10445 + 116, "GPIO116",
10446 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
10447 + DRV_GRP3,
10448 + MTK_FUNCTION(0, "GPIO116"),
10449 + MTK_FUNCTION(1, "MSDC0_DAT2")
10450 + ),
10451 + MTK_PIN(
10452 + 117, "GPIO117",
10453 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
10454 + DRV_GRP3,
10455 + MTK_FUNCTION(0, "GPIO117"),
10456 + MTK_FUNCTION(1, "MSDC0_DAT3")
10457 + ),
10458 + MTK_PIN(
10459 + 118, "GPIO118",
10460 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
10461 + DRV_GRP3,
10462 + MTK_FUNCTION(0, "GPIO118"),
10463 + MTK_FUNCTION(1, "MSDC0_DAT4")
10464 + ),
10465 + MTK_PIN(
10466 + 119, "GPIO119",
10467 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
10468 + DRV_GRP3,
10469 + MTK_FUNCTION(0, "GPIO119"),
10470 + MTK_FUNCTION(1, "MSDC0_DAT5")
10471 + ),
10472 + MTK_PIN(
10473 + 120, "GPIO120",
10474 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
10475 + DRV_GRP3,
10476 + MTK_FUNCTION(0, "GPIO120"),
10477 + MTK_FUNCTION(1, "MSDC0_DAT6")
10478 + ),
10479 + MTK_PIN(
10480 + 121, "GPIO121",
10481 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
10482 + DRV_GRP3,
10483 + MTK_FUNCTION(0, "GPIO121"),
10484 + MTK_FUNCTION(1, "MSDC0_DAT7")
10485 + ),
10486 + MTK_PIN(
10487 + 122, "GPIO122",
10488 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
10489 + DRV_GRP3,
10490 + MTK_FUNCTION(0, "GPIO122"),
10491 + MTK_FUNCTION(1, "MSDC0_CMD")
10492 + ),
10493 + MTK_PIN(
10494 + 123, "GPIO123",
10495 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
10496 + DRV_GRP3,
10497 + MTK_FUNCTION(0, "GPIO123"),
10498 + MTK_FUNCTION(1, "MSDC0_CLK")
10499 + ),
10500 + MTK_PIN(
10501 + 124, "GPIO124",
10502 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
10503 + DRV_GRP3,
10504 + MTK_FUNCTION(0, "GPIO124"),
10505 + MTK_FUNCTION(1, "MSDC0_DSL")
10506 + ),
10507 + MTK_PIN(
10508 + 125, "GPIO125",
10509 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
10510 + DRV_GRP3,
10511 + MTK_FUNCTION(0, "GPIO125"),
10512 + MTK_FUNCTION(1, "MSDC0_RSTB")
10513 + ),
10514 + MTK_PIN(
10515 + 126, "GPIO126",
10516 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
10517 + DRV_GRP3,
10518 + MTK_FUNCTION(0, "GPIO126"),
10519 + MTK_FUNCTION(1, "MD1_SIM1_SCLK"),
10520 + MTK_FUNCTION(2, "MD1_SIM2_SCLK"),
10521 + MTK_FUNCTION(3, "C2K_UIM0_CLK"),
10522 + MTK_FUNCTION(4, "C2K_UIM1_CLK")
10523 + ),
10524 + MTK_PIN(
10525 + 127, "GPIO127",
10526 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
10527 + DRV_GRP3,
10528 + MTK_FUNCTION(0, "GPIO127"),
10529 + MTK_FUNCTION(1, "MD1_SIM1_SRST"),
10530 + MTK_FUNCTION(2, "MD1_SIM2_SRST"),
10531 + MTK_FUNCTION(3, "C2K_UIM0_RST"),
10532 + MTK_FUNCTION(4, "C2K_UIM1_RST")
10533 + ),
10534 + MTK_PIN(
10535 + 128, "GPIO128",
10536 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
10537 + DRV_GRP3,
10538 + MTK_FUNCTION(0, "GPIO128"),
10539 + MTK_FUNCTION(1, "MD1_SIM1_SIO"),
10540 + MTK_FUNCTION(2, "MD1_SIM2_SIO"),
10541 + MTK_FUNCTION(3, "C2K_UIM0_IO"),
10542 + MTK_FUNCTION(4, "C2K_UIM1_IO")
10543 + ),
10544 + MTK_PIN(
10545 + 129, "GPIO129",
10546 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
10547 + DRV_GRP3,
10548 + MTK_FUNCTION(0, "GPIO129"),
10549 + MTK_FUNCTION(1, "MSDC1_CMD"),
10550 + MTK_FUNCTION(2, "CONN_DSP_JMS"),
10551 + MTK_FUNCTION(3, "LTE_JTAG_TMS"),
10552 + MTK_FUNCTION(4, "UDI_TMS"),
10553 + MTK_FUNCTION(5, "C2K_TMS")
10554 + ),
10555 + MTK_PIN(
10556 + 130, "GPIO130",
10557 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
10558 + DRV_GRP3,
10559 + MTK_FUNCTION(0, "GPIO130"),
10560 + MTK_FUNCTION(1, "MSDC1_DAT0"),
10561 + MTK_FUNCTION(2, "CONN_DSP_JDI"),
10562 + MTK_FUNCTION(3, "LTE_JTAG_TDI"),
10563 + MTK_FUNCTION(4, "UDI_TDI"),
10564 + MTK_FUNCTION(5, "C2K_TDI")
10565 + ),
10566 + MTK_PIN(
10567 + 131, "GPIO131",
10568 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
10569 + DRV_GRP3,
10570 + MTK_FUNCTION(0, "GPIO131"),
10571 + MTK_FUNCTION(1, "MSDC1_DAT1"),
10572 + MTK_FUNCTION(2, "CONN_DSP_JDO"),
10573 + MTK_FUNCTION(3, "LTE_JTAG_TDO"),
10574 + MTK_FUNCTION(4, "UDI_TDO"),
10575 + MTK_FUNCTION(5, "C2K_TDO")
10576 + ),
10577 + MTK_PIN(
10578 + 132, "GPIO132",
10579 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
10580 + DRV_GRP3,
10581 + MTK_FUNCTION(0, "GPIO132"),
10582 + MTK_FUNCTION(1, "MSDC1_DAT2"),
10583 + MTK_FUNCTION(5, "C2K_RTCK")
10584 + ),
10585 + MTK_PIN(
10586 + 133, "GPIO133",
10587 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
10588 + DRV_GRP3,
10589 + MTK_FUNCTION(0, "GPIO133"),
10590 + MTK_FUNCTION(1, "MSDC1_DAT3"),
10591 + MTK_FUNCTION(2, "CONN_DSP_JINTP"),
10592 + MTK_FUNCTION(3, "LTE_JTAG_TRSTN"),
10593 + MTK_FUNCTION(4, "UDI_NTRST"),
10594 + MTK_FUNCTION(5, "C2K_NTRST")
10595 + ),
10596 + MTK_PIN(
10597 + 134, "GPIO134",
10598 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
10599 + DRV_GRP3,
10600 + MTK_FUNCTION(0, "GPIO134"),
10601 + MTK_FUNCTION(1, "MSDC1_CLK"),
10602 + MTK_FUNCTION(2, "CONN_DSP_JCK"),
10603 + MTK_FUNCTION(3, "LTE_JTAG_TCK"),
10604 + MTK_FUNCTION(4, "UDI_TCK_XI"),
10605 + MTK_FUNCTION(5, "C2K_TCK")
10606 + ),
10607 + MTK_PIN(
10608 + 135, "GPIO135",
10609 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
10610 + DRV_GRP3,
10611 + MTK_FUNCTION(0, "GPIO135"),
10612 + MTK_FUNCTION(1, "TDM_LRCK"),
10613 + MTK_FUNCTION(2, "I2S0_LRCK"),
10614 + MTK_FUNCTION(3, "CLKM0"),
10615 + MTK_FUNCTION(4, "PCM1_SYNC"),
10616 + MTK_FUNCTION(5, "PWM_A"),
10617 + MTK_FUNCTION(7, "DBG_MON_A12")
10618 + ),
10619 + MTK_PIN(
10620 + 136, "GPIO136",
10621 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
10622 + DRV_GRP3,
10623 + MTK_FUNCTION(0, "GPIO136"),
10624 + MTK_FUNCTION(1, "TDM_BCK"),
10625 + MTK_FUNCTION(2, "I2S0_BCK"),
10626 + MTK_FUNCTION(3, "CLKM1"),
10627 + MTK_FUNCTION(4, "PCM1_CLK"),
10628 + MTK_FUNCTION(5, "PWM_B"),
10629 + MTK_FUNCTION(7, "DBG_MON_A13")
10630 + ),
10631 + MTK_PIN(
10632 + 137, "GPIO137",
10633 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
10634 + DRV_GRP3,
10635 + MTK_FUNCTION(0, "GPIO137"),
10636 + MTK_FUNCTION(1, "TDM_MCK"),
10637 + MTK_FUNCTION(2, "I2S0_MCK"),
10638 + MTK_FUNCTION(3, "CLKM2"),
10639 + MTK_FUNCTION(4, "PCM1_DI"),
10640 + MTK_FUNCTION(5, "IRTX_OUT"),
10641 + MTK_FUNCTION(7, "DBG_MON_A14")
10642 + ),
10643 + MTK_PIN(
10644 + 138, "GPIO138",
10645 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
10646 + DRV_GRP3,
10647 + MTK_FUNCTION(0, "GPIO138"),
10648 + MTK_FUNCTION(1, "TDM_DATA0"),
10649 + MTK_FUNCTION(2, "I2S0_DI"),
10650 + MTK_FUNCTION(3, "CLKM3"),
10651 + MTK_FUNCTION(4, "PCM1_DO0"),
10652 + MTK_FUNCTION(5, "PWM_C"),
10653 + MTK_FUNCTION(6, "SDA3_1"),
10654 + MTK_FUNCTION(7, "DBG_MON_A15")
10655 + ),
10656 + MTK_PIN(
10657 + 139, "GPIO139",
10658 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
10659 + DRV_GRP3,
10660 + MTK_FUNCTION(0, "GPIO139"),
10661 + MTK_FUNCTION(1, "TDM_DATA1"),
10662 + MTK_FUNCTION(2, "I2S3_DO"),
10663 + MTK_FUNCTION(3, "CLKM4"),
10664 + MTK_FUNCTION(4, "PCM1_DO1"),
10665 + MTK_FUNCTION(5, "ANT_SEL2"),
10666 + MTK_FUNCTION(6, "SCL3_1"),
10667 + MTK_FUNCTION(7, "DBG_MON_A16")
10668 + ),
10669 + MTK_PIN(
10670 + 140, "GPIO140",
10671 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
10672 + DRV_GRP3,
10673 + MTK_FUNCTION(0, "GPIO140"),
10674 + MTK_FUNCTION(1, "TDM_DATA2"),
10675 + MTK_FUNCTION(2, "DISP_PWM"),
10676 + MTK_FUNCTION(3, "CLKM5"),
10677 + MTK_FUNCTION(4, "SDA1_4"),
10678 + MTK_FUNCTION(5, "ANT_SEL1"),
10679 + MTK_FUNCTION(6, "URXD3"),
10680 + MTK_FUNCTION(7, "DBG_MON_A17")
10681 + ),
10682 + MTK_PIN(
10683 + 141, "GPIO141",
10684 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
10685 + DRV_GRP3,
10686 + MTK_FUNCTION(0, "GPIO141"),
10687 + MTK_FUNCTION(1, "TDM_DATA3"),
10688 + MTK_FUNCTION(2, "CMFLASH"),
10689 + MTK_FUNCTION(3, "IRTX_OUT"),
10690 + MTK_FUNCTION(4, "SCL1_4"),
10691 + MTK_FUNCTION(5, "ANT_SEL0"),
10692 + MTK_FUNCTION(6, "UTXD3"),
10693 + MTK_FUNCTION(7, "DBG_MON_A18")
10694 + ),
10695 + MTK_PIN(
10696 + 142, "GPIO142",
10697 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
10698 + DRV_GRP3,
10699 + MTK_FUNCTION(0, "GPIO142"),
10700 + MTK_FUNCTION(1, "PWRAP_SPI0_MI"),
10701 + MTK_FUNCTION(2, "PWRAP_SPI0_MO")
10702 + ),
10703 + MTK_PIN(
10704 + 143, "GPIO143",
10705 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
10706 + DRV_GRP3,
10707 + MTK_FUNCTION(0, "GPIO143"),
10708 + MTK_FUNCTION(1, "PWRAP_SPI0_MO"),
10709 + MTK_FUNCTION(2, "PWRAP_SPI0_MI")
10710 + ),
10711 + MTK_PIN(
10712 + 144, "GPIO144",
10713 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
10714 + DRV_GRP3,
10715 + MTK_FUNCTION(0, "GPIO144"),
10716 + MTK_FUNCTION(1, "PWRAP_SPI0_CK")
10717 + ),
10718 + MTK_PIN(
10719 + 145, "GPIO145",
10720 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
10721 + DRV_GRP3,
10722 + MTK_FUNCTION(0, "GPIO145"),
10723 + MTK_FUNCTION(1, "PWRAP_SPI0_CSN")
10724 + ),
10725 + MTK_PIN(
10726 + 146, "GPIO146",
10727 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
10728 + DRV_GRP3,
10729 + MTK_FUNCTION(0, "GPIO146"),
10730 + MTK_FUNCTION(1, "AUD_CLK_MOSI")
10731 + ),
10732 + MTK_PIN(
10733 + 147, "GPIO147",
10734 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
10735 + DRV_GRP3,
10736 + MTK_FUNCTION(0, "GPIO147"),
10737 + MTK_FUNCTION(1, "AUD_DAT_MISO"),
10738 + MTK_FUNCTION(2, "AUD_DAT_MOSI"),
10739 + MTK_FUNCTION(3, "VOW_DAT_MISO")
10740 + ),
10741 + MTK_PIN(
10742 + 148, "GPIO148",
10743 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
10744 + DRV_GRP3,
10745 + MTK_FUNCTION(0, "GPIO148"),
10746 + MTK_FUNCTION(1, "AUD_DAT_MOSI"),
10747 + MTK_FUNCTION(2, "AUD_DAT_MISO")
10748 + ),
10749 + MTK_PIN(
10750 + 149, "GPIO149",
10751 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
10752 + DRV_GRP3,
10753 + MTK_FUNCTION(0, "GPIO149"),
10754 + MTK_FUNCTION(1, "VOW_CLK_MISO")
10755 + ),
10756 + MTK_PIN(
10757 + 150, "GPIO150",
10758 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
10759 + DRV_GRP3,
10760 + MTK_FUNCTION(0, "GPIO150"),
10761 + MTK_FUNCTION(1, "ANC_DAT_MOSI")
10762 + ),
10763 + MTK_PIN(
10764 + 151, "GPIO151",
10765 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
10766 + DRV_GRP3,
10767 + MTK_FUNCTION(0, "GPIO151"),
10768 + MTK_FUNCTION(1, "SCL6_0")
10769 + ),
10770 + MTK_PIN(
10771 + 152, "GPIO152",
10772 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
10773 + DRV_GRP3,
10774 + MTK_FUNCTION(0, "GPIO152"),
10775 + MTK_FUNCTION(1, "SDA6_0")
10776 + ),
10777 + MTK_PIN(
10778 + 153, "GPIO153",
10779 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
10780 + DRV_GRP3,
10781 + MTK_FUNCTION(0, "GPIO153"),
10782 + MTK_FUNCTION(1, "SCL7_0")
10783 + ),
10784 + MTK_PIN(
10785 + 154, "GPIO154",
10786 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
10787 + DRV_GRP3,
10788 + MTK_FUNCTION(0, "GPIO154"),
10789 + MTK_FUNCTION(1, "SDA7_0")
10790 + ),
10791 + MTK_PIN(
10792 + 155, "GPIO155",
10793 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
10794 + DRV_GRP3,
10795 + MTK_FUNCTION(0, "GPIO155"),
10796 + MTK_FUNCTION(1, "MD1_SIM2_SCLK"),
10797 + MTK_FUNCTION(2, "MD1_SIM1_SCLK"),
10798 + MTK_FUNCTION(3, "C2K_UIM0_CLK"),
10799 + MTK_FUNCTION(4, "C2K_UIM1_CLK")
10800 + ),
10801 + MTK_PIN(
10802 + 156, "GPIO156",
10803 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
10804 + DRV_GRP3,
10805 + MTK_FUNCTION(0, "GPIO156"),
10806 + MTK_FUNCTION(1, "MD1_SIM2_SRST"),
10807 + MTK_FUNCTION(2, "MD1_SIM1_SRST"),
10808 + MTK_FUNCTION(3, "C2K_UIM0_RST"),
10809 + MTK_FUNCTION(4, "C2K_UIM1_RST")
10810 + ),
10811 + MTK_PIN(
10812 + 157, "GPIO157",
10813 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
10814 + DRV_GRP3,
10815 + MTK_FUNCTION(0, "GPIO157"),
10816 + MTK_FUNCTION(1, "MD1_SIM2_SIO"),
10817 + MTK_FUNCTION(2, "MD1_SIM1_SIO"),
10818 + MTK_FUNCTION(3, "C2K_UIM0_IO"),
10819 + MTK_FUNCTION(4, "C2K_UIM1_IO")
10820 + ),
10821 + MTK_PIN(
10822 + 158, "GPIO158",
10823 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
10824 + DRV_GRP3,
10825 + MTK_FUNCTION(0, "GPIO158"),
10826 + MTK_FUNCTION(1, "MIPI_TDP0")
10827 + ),
10828 + MTK_PIN(
10829 + 159, "GPIO159",
10830 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
10831 + DRV_GRP3,
10832 + MTK_FUNCTION(0, "GPIO159"),
10833 + MTK_FUNCTION(1, "MIPI_TDN0")
10834 + ),
10835 + MTK_PIN(
10836 + 160, "GPIO160",
10837 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
10838 + DRV_GRP3,
10839 + MTK_FUNCTION(0, "GPIO160"),
10840 + MTK_FUNCTION(1, "MIPI_TDP1")
10841 + ),
10842 + MTK_PIN(
10843 + 161, "GPIO161",
10844 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
10845 + DRV_GRP3,
10846 + MTK_FUNCTION(0, "GPIO161"),
10847 + MTK_FUNCTION(1, "MIPI_TDN1")
10848 + ),
10849 + MTK_PIN(
10850 + 162, "GPIO162",
10851 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
10852 + DRV_GRP3,
10853 + MTK_FUNCTION(0, "GPIO162"),
10854 + MTK_FUNCTION(1, "MIPI_TCP")
10855 + ),
10856 + MTK_PIN(
10857 + 163, "GPIO163",
10858 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
10859 + DRV_GRP3,
10860 + MTK_FUNCTION(0, "GPIO163"),
10861 + MTK_FUNCTION(1, "MIPI_TCN")
10862 + ),
10863 + MTK_PIN(
10864 + 164, "GPIO164",
10865 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
10866 + DRV_GRP3,
10867 + MTK_FUNCTION(0, "GPIO164"),
10868 + MTK_FUNCTION(1, "MIPI_TDP2")
10869 + ),
10870 + MTK_PIN(
10871 + 165, "GPIO165",
10872 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
10873 + DRV_GRP3,
10874 + MTK_FUNCTION(0, "GPIO165"),
10875 + MTK_FUNCTION(1, "MIPI_TDN2")
10876 + ),
10877 + MTK_PIN(
10878 + 166, "GPIO166",
10879 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
10880 + DRV_GRP3,
10881 + MTK_FUNCTION(0, "GPIO166"),
10882 + MTK_FUNCTION(1, "MIPI_TDP3")
10883 + ),
10884 + MTK_PIN(
10885 + 167, "GPIO167",
10886 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
10887 + DRV_GRP3,
10888 + MTK_FUNCTION(0, "GPIO167"),
10889 + MTK_FUNCTION(1, "MIPI_TDN3")
10890 + ),
10891 + MTK_PIN(
10892 + 168, "GPIO168",
10893 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
10894 + DRV_GRP3,
10895 + MTK_FUNCTION(0, "GPIO168"),
10896 + MTK_FUNCTION(1, "MIPI_TDP0_A")
10897 + ),
10898 + MTK_PIN(
10899 + 169, "GPIO169",
10900 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
10901 + DRV_GRP3,
10902 + MTK_FUNCTION(0, "GPIO169"),
10903 + MTK_FUNCTION(1, "MIPI_TDN0_A")
10904 + ),
10905 + MTK_PIN(
10906 + 170, "GPIO170",
10907 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
10908 + DRV_GRP3,
10909 + MTK_FUNCTION(0, "GPIO170"),
10910 + MTK_FUNCTION(1, "MIPI_TDP1_A")
10911 + ),
10912 + MTK_PIN(
10913 + 171, "GPIO171",
10914 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
10915 + DRV_GRP3,
10916 + MTK_FUNCTION(0, "GPIO171"),
10917 + MTK_FUNCTION(1, "MIPI_TDN1_A")
10918 + ),
10919 + MTK_PIN(
10920 + 172, "GPIO172",
10921 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
10922 + DRV_GRP3,
10923 + MTK_FUNCTION(0, "GPIO172"),
10924 + MTK_FUNCTION(1, "MIPI_TCP_A")
10925 + ),
10926 + MTK_PIN(
10927 + 173, "GPIO173",
10928 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
10929 + DRV_GRP3,
10930 + MTK_FUNCTION(0, "GPIO173"),
10931 + MTK_FUNCTION(1, "MIPI_TCN_A")
10932 + ),
10933 + MTK_PIN(
10934 + 174, "GPIO174",
10935 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
10936 + DRV_GRP3,
10937 + MTK_FUNCTION(0, "GPIO174"),
10938 + MTK_FUNCTION(1, "MIPI_TDP2_A")
10939 + ),
10940 + MTK_PIN(
10941 + 175, "GPIO175",
10942 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
10943 + DRV_GRP3,
10944 + MTK_FUNCTION(0, "GPIO175"),
10945 + MTK_FUNCTION(1, "MIPI_TDN2_A")
10946 + ),
10947 + MTK_PIN(
10948 + 176, "GPIO176",
10949 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
10950 + DRV_GRP3,
10951 + MTK_FUNCTION(0, "GPIO176"),
10952 + MTK_FUNCTION(1, "MIPI_TDP3_A")
10953 + ),
10954 + MTK_PIN(
10955 + 177, "GPIO177",
10956 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
10957 + DRV_GRP3,
10958 + MTK_FUNCTION(0, "GPIO177"),
10959 + MTK_FUNCTION(1, "MIPI_TDN3_A")
10960 + ),
10961 + MTK_PIN(
10962 + 178, "GPIO178",
10963 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
10964 + DRV_GRP3,
10965 + MTK_FUNCTION(0, "GPIO178"),
10966 + MTK_FUNCTION(1, "DISP_PWM"),
10967 + MTK_FUNCTION(2, "PWM_D"),
10968 + MTK_FUNCTION(3, "CLKM5"),
10969 + MTK_FUNCTION(7, "DBG_MON_A19")
10970 + ),
10971 + MTK_PIN(
10972 + 179, "GPIO179",
10973 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
10974 + DRV_GRP3,
10975 + MTK_FUNCTION(0, "GPIO179"),
10976 + MTK_FUNCTION(1, "DSI_TE0"),
10977 + MTK_FUNCTION(7, "DBG_MON_A20")
10978 + ),
10979 + MTK_PIN(
10980 + 180, "GPIO180",
10981 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
10982 + DRV_GRP3,
10983 + MTK_FUNCTION(0, "GPIO180"),
10984 + MTK_FUNCTION(1, "LCM_RST"),
10985 + MTK_FUNCTION(2, "DSI_TE1"),
10986 + MTK_FUNCTION(7, "DBG_MON_A21")
10987 + ),
10988 + MTK_PIN(
10989 + 181, "GPIO181",
10990 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
10991 + DRV_GRP3,
10992 + MTK_FUNCTION(0, "GPIO181"),
10993 + MTK_FUNCTION(1, "IDDIG"),
10994 + MTK_FUNCTION(2, "DSI_TE1"),
10995 + MTK_FUNCTION(7, "DBG_MON_A22")
10996 + ),
10997 + MTK_PIN(
10998 + 182, "GPIO182",
10999 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
11000 + DRV_GRP3,
11001 + MTK_FUNCTION(0, "GPIO182"),
11002 + MTK_FUNCTION(1, "TESTMODE")
11003 + ),
11004 + MTK_PIN(
11005 + 183, "GPIO183",
11006 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
11007 + DRV_GRP3,
11008 + MTK_FUNCTION(0, "GPIO183"),
11009 + MTK_FUNCTION(1, "RFIC0_BSI_CK"),
11010 + MTK_FUNCTION(2, "SPM_BSI_CK"),
11011 + MTK_FUNCTION(7, "DBG_MON_B27")
11012 + ),
11013 + MTK_PIN(
11014 + 184, "GPIO184",
11015 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
11016 + DRV_GRP3,
11017 + MTK_FUNCTION(0, "GPIO184"),
11018 + MTK_FUNCTION(1, "RFIC0_BSI_EN"),
11019 + MTK_FUNCTION(2, "SPM_BSI_EN"),
11020 + MTK_FUNCTION(7, "DBG_MON_B28")
11021 + ),
11022 + MTK_PIN(
11023 + 185, "GPIO185",
11024 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
11025 + DRV_GRP3,
11026 + MTK_FUNCTION(0, "GPIO185"),
11027 + MTK_FUNCTION(1, "RFIC0_BSI_D0"),
11028 + MTK_FUNCTION(2, "SPM_BSI_D0"),
11029 + MTK_FUNCTION(7, "DBG_MON_B29")
11030 + ),
11031 + MTK_PIN(
11032 + 186, "GPIO186",
11033 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
11034 + DRV_GRP3,
11035 + MTK_FUNCTION(0, "GPIO186"),
11036 + MTK_FUNCTION(1, "RFIC0_BSI_D1"),
11037 + MTK_FUNCTION(2, "SPM_BSI_D1"),
11038 + MTK_FUNCTION(7, "DBG_MON_B30")
11039 + ),
11040 + MTK_PIN(
11041 + 187, "GPIO187",
11042 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
11043 + DRV_GRP3,
11044 + MTK_FUNCTION(0, "GPIO187"),
11045 + MTK_FUNCTION(1, "RFIC0_BSI_D2"),
11046 + MTK_FUNCTION(2, "SPM_BSI_D2"),
11047 + MTK_FUNCTION(7, "DBG_MON_B31")
11048 + ),
11049 + MTK_PIN(
11050 + 188, "GPIO188",
11051 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
11052 + DRV_GRP3,
11053 + MTK_FUNCTION(0, "GPIO188"),
11054 + MTK_FUNCTION(1, "MIPI0_SCLK"),
11055 + MTK_FUNCTION(7, "DBG_MON_B32")
11056 + ),
11057 + MTK_PIN(
11058 + 189, "GPIO189",
11059 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
11060 + DRV_GRP3,
11061 + MTK_FUNCTION(0, "GPIO189"),
11062 + MTK_FUNCTION(1, "MIPI0_SDATA")
11063 + ),
11064 + MTK_PIN(
11065 + 190, "GPIO190",
11066 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
11067 + DRV_GRP3,
11068 + MTK_FUNCTION(0, "GPIO190"),
11069 + MTK_FUNCTION(1, "MIPI1_SCLK")
11070 + ),
11071 + MTK_PIN(
11072 + 191, "GPIO191",
11073 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
11074 + DRV_GRP3,
11075 + MTK_FUNCTION(0, "GPIO191"),
11076 + MTK_FUNCTION(1, "MIPI1_SDATA")
11077 + ),
11078 + MTK_PIN(
11079 + 192, "GPIO192",
11080 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
11081 + DRV_GRP3,
11082 + MTK_FUNCTION(0, "GPIO192"),
11083 + MTK_FUNCTION(1, "BPI_BUS4")
11084 + ),
11085 + MTK_PIN(
11086 + 193, "GPIO193",
11087 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
11088 + DRV_GRP3,
11089 + MTK_FUNCTION(0, "GPIO193"),
11090 + MTK_FUNCTION(1, "BPI_BUS5"),
11091 + MTK_FUNCTION(7, "DBG_MON_B0")
11092 + ),
11093 + MTK_PIN(
11094 + 194, "GPIO194",
11095 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
11096 + DRV_GRP3,
11097 + MTK_FUNCTION(0, "GPIO194"),
11098 + MTK_FUNCTION(1, "BPI_BUS6"),
11099 + MTK_FUNCTION(7, "DBG_MON_B1")
11100 + ),
11101 + MTK_PIN(
11102 + 195, "GPIO195",
11103 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
11104 + DRV_GRP3,
11105 + MTK_FUNCTION(0, "GPIO195"),
11106 + MTK_FUNCTION(1, "BPI_BUS7"),
11107 + MTK_FUNCTION(7, "DBG_MON_B2")
11108 + ),
11109 + MTK_PIN(
11110 + 196, "GPIO196",
11111 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
11112 + DRV_GRP3,
11113 + MTK_FUNCTION(0, "GPIO196"),
11114 + MTK_FUNCTION(1, "BPI_BUS8"),
11115 + MTK_FUNCTION(7, "DBG_MON_B3")
11116 + ),
11117 + MTK_PIN(
11118 + 197, "GPIO197",
11119 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
11120 + DRV_GRP3,
11121 + MTK_FUNCTION(0, "GPIO197"),
11122 + MTK_FUNCTION(1, "BPI_BUS9"),
11123 + MTK_FUNCTION(7, "DBG_MON_B4")
11124 + ),
11125 + MTK_PIN(
11126 + 198, "GPIO198",
11127 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
11128 + DRV_GRP3,
11129 + MTK_FUNCTION(0, "GPIO198"),
11130 + MTK_FUNCTION(1, "BPI_BUS10"),
11131 + MTK_FUNCTION(7, "DBG_MON_B5")
11132 + ),
11133 + MTK_PIN(
11134 + 199, "GPIO199",
11135 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
11136 + DRV_GRP3,
11137 + MTK_FUNCTION(0, "GPIO199"),
11138 + MTK_FUNCTION(1, "BPI_BUS11"),
11139 + MTK_FUNCTION(7, "DBG_MON_B6")
11140 + ),
11141 + MTK_PIN(
11142 + 200, "GPIO200",
11143 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
11144 + DRV_GRP3,
11145 + MTK_FUNCTION(0, "GPIO200"),
11146 + MTK_FUNCTION(1, "BPI_BUS12"),
11147 + MTK_FUNCTION(7, "DBG_MON_B7")
11148 + ),
11149 + MTK_PIN(
11150 + 201, "GPIO201",
11151 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
11152 + DRV_GRP3,
11153 + MTK_FUNCTION(0, "GPIO201"),
11154 + MTK_FUNCTION(1, "BPI_BUS13"),
11155 + MTK_FUNCTION(7, "DBG_MON_B8")
11156 + ),
11157 + MTK_PIN(
11158 + 202, "GPIO202",
11159 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
11160 + DRV_GRP3,
11161 + MTK_FUNCTION(0, "GPIO202"),
11162 + MTK_FUNCTION(1, "BPI_BUS14"),
11163 + MTK_FUNCTION(7, "DBG_MON_B9")
11164 + ),
11165 + MTK_PIN(
11166 + 203, "GPIO203",
11167 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
11168 + DRV_GRP3,
11169 + MTK_FUNCTION(0, "GPIO203"),
11170 + MTK_FUNCTION(1, "BPI_BUS15"),
11171 + MTK_FUNCTION(7, "DBG_MON_B10")
11172 + ),
11173 + MTK_PIN(
11174 + 204, "GPIO204",
11175 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
11176 + DRV_GRP3,
11177 + MTK_FUNCTION(0, "GPIO204"),
11178 + MTK_FUNCTION(1, "BPI_BUS16"),
11179 + MTK_FUNCTION(2, "PA_VM0"),
11180 + MTK_FUNCTION(7, "DBG_MON_B11")
11181 + ),
11182 + MTK_PIN(
11183 + 205, "GPIO205",
11184 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
11185 + DRV_GRP3,
11186 + MTK_FUNCTION(0, "GPIO205"),
11187 + MTK_FUNCTION(1, "BPI_BUS17"),
11188 + MTK_FUNCTION(2, "PA_VM1"),
11189 + MTK_FUNCTION(7, "DBG_MON_B12")
11190 + ),
11191 + MTK_PIN(
11192 + 206, "GPIO206",
11193 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
11194 + DRV_GRP3,
11195 + MTK_FUNCTION(0, "GPIO206"),
11196 + MTK_FUNCTION(1, "BPI_BUS18"),
11197 + MTK_FUNCTION(2, "TX_SWAP0"),
11198 + MTK_FUNCTION(7, "DBG_MON_B13")
11199 + ),
11200 + MTK_PIN(
11201 + 207, "GPIO207",
11202 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
11203 + DRV_GRP3,
11204 + MTK_FUNCTION(0, "GPIO207"),
11205 + MTK_FUNCTION(1, "BPI_BUS19"),
11206 + MTK_FUNCTION(2, "TX_SWAP1"),
11207 + MTK_FUNCTION(7, "DBG_MON_B14")
11208 + ),
11209 + MTK_PIN(
11210 + 208, "GPIO208",
11211 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
11212 + DRV_GRP3,
11213 + MTK_FUNCTION(0, "GPIO208"),
11214 + MTK_FUNCTION(1, "BPI_BUS20"),
11215 + MTK_FUNCTION(2, "TX_SWAP2"),
11216 + MTK_FUNCTION(7, "DBG_MON_B15")
11217 + ),
11218 + MTK_PIN(
11219 + 209, "GPIO209",
11220 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
11221 + DRV_GRP3,
11222 + MTK_FUNCTION(0, "GPIO209"),
11223 + MTK_FUNCTION(1, "BPI_BUS21"),
11224 + MTK_FUNCTION(2, "TX_SWAP3"),
11225 + MTK_FUNCTION(7, "DBG_MON_B16")
11226 + ),
11227 + MTK_PIN(
11228 + 210, "GPIO210",
11229 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
11230 + DRV_GRP3,
11231 + MTK_FUNCTION(0, "GPIO210"),
11232 + MTK_FUNCTION(1, "BPI_BUS22"),
11233 + MTK_FUNCTION(2, "DET_BPI0"),
11234 + MTK_FUNCTION(7, "DBG_MON_B17")
11235 + ),
11236 + MTK_PIN(
11237 + 211, "GPIO211",
11238 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
11239 + DRV_GRP3,
11240 + MTK_FUNCTION(0, "GPIO211"),
11241 + MTK_FUNCTION(1, "BPI_BUS23"),
11242 + MTK_FUNCTION(2, "DET_BPI1"),
11243 + MTK_FUNCTION(7, "DBG_MON_B18")
11244 + ),
11245 + MTK_PIN(
11246 + 212, "GPIO212",
11247 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
11248 + DRV_GRP3,
11249 + MTK_FUNCTION(0, "GPIO212"),
11250 + MTK_FUNCTION(1, "BPI_BUS0"),
11251 + MTK_FUNCTION(7, "DBG_MON_B19")
11252 + ),
11253 + MTK_PIN(
11254 + 213, "GPIO213",
11255 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
11256 + DRV_GRP3,
11257 + MTK_FUNCTION(0, "GPIO213"),
11258 + MTK_FUNCTION(1, "BPI_BUS1"),
11259 + MTK_FUNCTION(7, "DBG_MON_B20")
11260 + ),
11261 + MTK_PIN(
11262 + 214, "GPIO214",
11263 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
11264 + DRV_GRP3,
11265 + MTK_FUNCTION(0, "GPIO214"),
11266 + MTK_FUNCTION(1, "BPI_BUS2"),
11267 + MTK_FUNCTION(7, "DBG_MON_B21")
11268 + ),
11269 + MTK_PIN(
11270 + 215, "GPIO215",
11271 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
11272 + DRV_GRP3,
11273 + MTK_FUNCTION(0, "GPIO215"),
11274 + MTK_FUNCTION(1, "BPI_BUS3"),
11275 + MTK_FUNCTION(7, "DBG_MON_B22")
11276 + ),
11277 + MTK_PIN(
11278 + 216, "GPIO216",
11279 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
11280 + DRV_GRP3,
11281 + MTK_FUNCTION(0, "GPIO216"),
11282 + MTK_FUNCTION(1, "MIPI2_SCLK"),
11283 + MTK_FUNCTION(7, "DBG_MON_B23")
11284 + ),
11285 + MTK_PIN(
11286 + 217, "GPIO217",
11287 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
11288 + DRV_GRP3,
11289 + MTK_FUNCTION(0, "GPIO217"),
11290 + MTK_FUNCTION(1, "MIPI2_SDATA"),
11291 + MTK_FUNCTION(7, "DBG_MON_B24")
11292 + ),
11293 + MTK_PIN(
11294 + 218, "GPIO218",
11295 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
11296 + DRV_GRP3,
11297 + MTK_FUNCTION(0, "GPIO218"),
11298 + MTK_FUNCTION(1, "MIPI3_SCLK"),
11299 + MTK_FUNCTION(7, "DBG_MON_B25")
11300 + ),
11301 + MTK_PIN(
11302 + 219, "GPIO219",
11303 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
11304 + DRV_GRP3,
11305 + MTK_FUNCTION(0, "GPIO219"),
11306 + MTK_FUNCTION(1, "MIPI3_SDATA"),
11307 + MTK_FUNCTION(7, "DBG_MON_B26")
11308 + ),
11309 + MTK_PIN(
11310 + 220, "GPIO220",
11311 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
11312 + DRV_GRP3,
11313 + MTK_FUNCTION(0, "GPIO220"),
11314 + MTK_FUNCTION(1, "CONN_WF_IP")
11315 + ),
11316 + MTK_PIN(
11317 + 221, "GPIO221",
11318 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
11319 + DRV_GRP3,
11320 + MTK_FUNCTION(0, "GPIO221"),
11321 + MTK_FUNCTION(1, "CONN_WF_IN")
11322 + ),
11323 + MTK_PIN(
11324 + 222, "GPIO222",
11325 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
11326 + DRV_GRP3,
11327 + MTK_FUNCTION(0, "GPIO222"),
11328 + MTK_FUNCTION(1, "CONN_WF_QP")
11329 + ),
11330 + MTK_PIN(
11331 + 223, "GPIO223",
11332 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
11333 + DRV_GRP3,
11334 + MTK_FUNCTION(0, "GPIO223"),
11335 + MTK_FUNCTION(1, "CONN_WF_QN")
11336 + ),
11337 + MTK_PIN(
11338 + 224, "GPIO224",
11339 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
11340 + DRV_GRP3,
11341 + MTK_FUNCTION(0, "GPIO224"),
11342 + MTK_FUNCTION(1, "CONN_BT_IP")
11343 + ),
11344 + MTK_PIN(
11345 + 225, "GPIO225",
11346 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
11347 + DRV_GRP3,
11348 + MTK_FUNCTION(0, "GPIO225"),
11349 + MTK_FUNCTION(1, "CONN_BT_IN")
11350 + ),
11351 + MTK_PIN(
11352 + 226, "GPIO226",
11353 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
11354 + DRV_GRP3,
11355 + MTK_FUNCTION(0, "GPIO226"),
11356 + MTK_FUNCTION(1, "CONN_BT_QP")
11357 + ),
11358 + MTK_PIN(
11359 + 227, "GPIO227",
11360 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
11361 + DRV_GRP3,
11362 + MTK_FUNCTION(0, "GPIO227"),
11363 + MTK_FUNCTION(1, "CONN_BT_QN")
11364 + ),
11365 + MTK_PIN(
11366 + 228, "GPIO228",
11367 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
11368 + DRV_GRP3,
11369 + MTK_FUNCTION(0, "GPIO228"),
11370 + MTK_FUNCTION(1, "CONN_GPS_IP")
11371 + ),
11372 + MTK_PIN(
11373 + 229, "GPIO229",
11374 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
11375 + DRV_GRP3,
11376 + MTK_FUNCTION(0, "GPIO229"),
11377 + MTK_FUNCTION(1, "CONN_GPS_IN")
11378 + ),
11379 + MTK_PIN(
11380 + 230, "GPIO230",
11381 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
11382 + DRV_GRP3,
11383 + MTK_FUNCTION(0, "GPIO230"),
11384 + MTK_FUNCTION(1, "CONN_GPS_QP")
11385 + ),
11386 + MTK_PIN(
11387 + 231, "GPIO231",
11388 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
11389 + DRV_GRP3,
11390 + MTK_FUNCTION(0, "GPIO231"),
11391 + MTK_FUNCTION(1, "CONN_GPS_QN")
11392 + ),
11393 + MTK_PIN(
11394 + 232, "GPIO232",
11395 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
11396 + DRV_GRP3,
11397 + MTK_FUNCTION(0, "GPIO232"),
11398 + MTK_FUNCTION(1, "URXD1"),
11399 + MTK_FUNCTION(2, "UTXD1"),
11400 + MTK_FUNCTION(3, "MD_URXD0"),
11401 + MTK_FUNCTION(4, "MD_URXD1"),
11402 + MTK_FUNCTION(5, "MD_URXD2"),
11403 + MTK_FUNCTION(6, "C2K_URXD0"),
11404 + MTK_FUNCTION(7, "C2K_URXD1")
11405 + ),
11406 + MTK_PIN(
11407 + 233, "GPIO233",
11408 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
11409 + DRV_GRP3,
11410 + MTK_FUNCTION(0, "GPIO233"),
11411 + MTK_FUNCTION(1, "UTXD1"),
11412 + MTK_FUNCTION(2, "URXD1"),
11413 + MTK_FUNCTION(3, "MD_UTXD0"),
11414 + MTK_FUNCTION(4, "MD_UTXD1"),
11415 + MTK_FUNCTION(5, "MD_UTXD2"),
11416 + MTK_FUNCTION(6, "C2K_UTXD0"),
11417 + MTK_FUNCTION(7, "C2K_UTXD1")
11418 + ),
11419 + MTK_PIN(
11420 + 234, "GPIO234",
11421 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
11422 + DRV_GRP3,
11423 + MTK_FUNCTION(0, "GPIO234"),
11424 + MTK_FUNCTION(1, "SPI1_CLK_B"),
11425 + MTK_FUNCTION(2, "TP_UTXD1_AO"),
11426 + MTK_FUNCTION(3, "SCL4_1"),
11427 + MTK_FUNCTION(4, "UTXD0"),
11428 + MTK_FUNCTION(6, "PWM_A"),
11429 + MTK_FUNCTION(7, "DBG_MON_A23")
11430 + ),
11431 + MTK_PIN(
11432 + 235, "GPIO235",
11433 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
11434 + DRV_GRP3,
11435 + MTK_FUNCTION(0, "GPIO235"),
11436 + MTK_FUNCTION(1, "SPI1_MI_B"),
11437 + MTK_FUNCTION(2, "SPI1_MO_B"),
11438 + MTK_FUNCTION(3, "SDA4_1"),
11439 + MTK_FUNCTION(4, "URXD0"),
11440 + MTK_FUNCTION(6, "CLKM0"),
11441 + MTK_FUNCTION(7, "DBG_MON_A24")
11442 + ),
11443 + MTK_PIN(
11444 + 236, "GPIO236",
11445 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
11446 + DRV_GRP3,
11447 + MTK_FUNCTION(0, "GPIO236"),
11448 + MTK_FUNCTION(1, "SPI1_MO_B"),
11449 + MTK_FUNCTION(2, "SPI1_MI_B"),
11450 + MTK_FUNCTION(3, "SCL5_1"),
11451 + MTK_FUNCTION(4, "URTS0"),
11452 + MTK_FUNCTION(6, "PWM_B"),
11453 + MTK_FUNCTION(7, "DBG_MON_A25")
11454 + ),
11455 + MTK_PIN(
11456 + 237, "GPIO237",
11457 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
11458 + DRV_GRP3,
11459 + MTK_FUNCTION(0, "GPIO237"),
11460 + MTK_FUNCTION(1, "SPI1_CS_B"),
11461 + MTK_FUNCTION(2, "TP_URXD1_AO"),
11462 + MTK_FUNCTION(3, "SDA5_1"),
11463 + MTK_FUNCTION(4, "UCTS0"),
11464 + MTK_FUNCTION(6, "CLKM1"),
11465 + MTK_FUNCTION(7, "DBG_MON_A26")
11466 + ),
11467 + MTK_PIN(
11468 + 238, "GPIO238",
11469 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
11470 + DRV_GRP3,
11471 + MTK_FUNCTION(0, "GPIO238"),
11472 + MTK_FUNCTION(1, "SDA4_0")
11473 + ),
11474 + MTK_PIN(
11475 + 239, "GPIO239",
11476 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
11477 + DRV_GRP3,
11478 + MTK_FUNCTION(0, "GPIO239"),
11479 + MTK_FUNCTION(1, "SCL4_0")
11480 + ),
11481 + MTK_PIN(
11482 + 240, "GPIO240",
11483 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
11484 + DRV_GRP3,
11485 + MTK_FUNCTION(0, "GPIO240"),
11486 + MTK_FUNCTION(1, "SDA5_0")
11487 + ),
11488 + MTK_PIN(
11489 + 241, "GPIO241",
11490 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
11491 + DRV_GRP3,
11492 + MTK_FUNCTION(0, "GPIO241"),
11493 + MTK_FUNCTION(1, "SCL5_0")
11494 + ),
11495 + MTK_PIN(
11496 + 242, "GPIO242",
11497 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
11498 + DRV_GRP3,
11499 + MTK_FUNCTION(0, "GPIO242"),
11500 + MTK_FUNCTION(1, "SPI2_CLK_B"),
11501 + MTK_FUNCTION(2, "TP_UTXD2_AO"),
11502 + MTK_FUNCTION(3, "SCL4_2"),
11503 + MTK_FUNCTION(4, "UTXD1"),
11504 + MTK_FUNCTION(5, "URTS3"),
11505 + MTK_FUNCTION(6, "PWM_C"),
11506 + MTK_FUNCTION(7, "DBG_MON_A27")
11507 + ),
11508 + MTK_PIN(
11509 + 243, "GPIO243",
11510 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
11511 + DRV_GRP3,
11512 + MTK_FUNCTION(0, "GPIO243"),
11513 + MTK_FUNCTION(1, "SPI2_MI_B"),
11514 + MTK_FUNCTION(2, "SPI2_MO_B"),
11515 + MTK_FUNCTION(3, "SDA4_2"),
11516 + MTK_FUNCTION(4, "URXD1"),
11517 + MTK_FUNCTION(5, "UCTS3"),
11518 + MTK_FUNCTION(6, "CLKM2"),
11519 + MTK_FUNCTION(7, "DBG_MON_A28")
11520 + ),
11521 + MTK_PIN(
11522 + 244, "GPIO244",
11523 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
11524 + DRV_GRP3,
11525 + MTK_FUNCTION(0, "GPIO244"),
11526 + MTK_FUNCTION(1, "SPI2_MO_B"),
11527 + MTK_FUNCTION(2, "SPI2_MI_B"),
11528 + MTK_FUNCTION(3, "SCL5_2"),
11529 + MTK_FUNCTION(4, "URTS1"),
11530 + MTK_FUNCTION(5, "UTXD3"),
11531 + MTK_FUNCTION(6, "PWM_D"),
11532 + MTK_FUNCTION(7, "DBG_MON_A29")
11533 + ),
11534 + MTK_PIN(
11535 + 245, "GPIO245",
11536 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
11537 + DRV_GRP3,
11538 + MTK_FUNCTION(0, "GPIO245"),
11539 + MTK_FUNCTION(1, "SPI2_CS_B"),
11540 + MTK_FUNCTION(2, "TP_URXD2_AO"),
11541 + MTK_FUNCTION(3, "SDA5_2"),
11542 + MTK_FUNCTION(4, "UCTS1"),
11543 + MTK_FUNCTION(5, "URXD3"),
11544 + MTK_FUNCTION(6, "CLKM3"),
11545 + MTK_FUNCTION(7, "DBG_MON_A30")
11546 + ),
11547 + MTK_PIN(
11548 + 246, "GPIO246",
11549 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
11550 + DRV_GRP3,
11551 + MTK_FUNCTION(0, "GPIO246"),
11552 + MTK_FUNCTION(1, "I2S1_LRCK"),
11553 + MTK_FUNCTION(2, "I2S2_LRCK"),
11554 + MTK_FUNCTION(3, "I2S0_LRCK"),
11555 + MTK_FUNCTION(4, "I2S3_LRCK"),
11556 + MTK_FUNCTION(5, "PCM0_SYNC"),
11557 + MTK_FUNCTION(6, "SPI5_CLK_C"),
11558 + MTK_FUNCTION(7, "DBG_MON_A31")
11559 + ),
11560 + MTK_PIN(
11561 + 247, "GPIO247",
11562 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
11563 + DRV_GRP3,
11564 + MTK_FUNCTION(0, "GPIO247"),
11565 + MTK_FUNCTION(1, "I2S1_BCK"),
11566 + MTK_FUNCTION(2, "I2S2_BCK"),
11567 + MTK_FUNCTION(3, "I2S0_BCK"),
11568 + MTK_FUNCTION(4, "I2S3_BCK"),
11569 + MTK_FUNCTION(5, "PCM0_CLK"),
11570 + MTK_FUNCTION(6, "SPI5_MI_C"),
11571 + MTK_FUNCTION(7, "DBG_MON_A32")
11572 + ),
11573 + MTK_PIN(
11574 + 248, "GPIO248",
11575 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
11576 + DRV_GRP3,
11577 + MTK_FUNCTION(0, "GPIO248"),
11578 + MTK_FUNCTION(1, "I2S2_DI"),
11579 + MTK_FUNCTION(2, "I2S2_DI"),
11580 + MTK_FUNCTION(3, "I2S0_DI"),
11581 + MTK_FUNCTION(4, "I2S0_DI"),
11582 + MTK_FUNCTION(5, "PCM0_DI"),
11583 + MTK_FUNCTION(6, "SPI5_CS_C")
11584 + ),
11585 + MTK_PIN(
11586 + 249, "GPIO249",
11587 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
11588 + DRV_GRP3,
11589 + MTK_FUNCTION(0, "GPIO249"),
11590 + MTK_FUNCTION(1, "I2S1_DO"),
11591 + MTK_FUNCTION(2, "I2S1_DO"),
11592 + MTK_FUNCTION(3, "I2S3_DO"),
11593 + MTK_FUNCTION(4, "I2S3_DO"),
11594 + MTK_FUNCTION(5, "PCM0_DO"),
11595 + MTK_FUNCTION(6, "SPI5_MO_C"),
11596 + MTK_FUNCTION(7, "TRAP_SRAM_PWR_BYPASS")
11597 + ),
11598 + MTK_PIN(
11599 + 250, "GPIO250",
11600 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
11601 + DRV_GRP3,
11602 + MTK_FUNCTION(0, "GPIO250"),
11603 + MTK_FUNCTION(1, "SPI3_MI"),
11604 + MTK_FUNCTION(2, "SPI3_MO"),
11605 + MTK_FUNCTION(3, "IRTX_OUT"),
11606 + MTK_FUNCTION(6, "TP_URXD1_AO"),
11607 + MTK_FUNCTION(7, "DROP_ZONE")
11608 + ),
11609 + MTK_PIN(
11610 + 251, "GPIO251",
11611 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
11612 + DRV_GRP3,
11613 + MTK_FUNCTION(0, "GPIO251"),
11614 + MTK_FUNCTION(1, "SPI3_MO"),
11615 + MTK_FUNCTION(2, "SPI3_MI"),
11616 + MTK_FUNCTION(3, "CMFLASH"),
11617 + MTK_FUNCTION(6, "TP_UTXD1_AO"),
11618 + MTK_FUNCTION(7, "C2K_RTCK")
11619 + ),
11620 + MTK_PIN(
11621 + 252, "GPIO252",
11622 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
11623 + DRV_GRP3,
11624 + MTK_FUNCTION(0, "GPIO252"),
11625 + MTK_FUNCTION(1, "SPI3_CLK"),
11626 + MTK_FUNCTION(2, "SCL0_4"),
11627 + MTK_FUNCTION(3, "PWM_D"),
11628 + MTK_FUNCTION(7, "C2K_TMS")
11629 + ),
11630 + MTK_PIN(
11631 + 253, "GPIO253",
11632 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
11633 + DRV_GRP3,
11634 + MTK_FUNCTION(0, "GPIO253"),
11635 + MTK_FUNCTION(1, "SPI3_CS"),
11636 + MTK_FUNCTION(2, "SDA0_4"),
11637 + MTK_FUNCTION(3, "PWM_A"),
11638 + MTK_FUNCTION(7, "C2K_TCK")
11639 + ),
11640 + MTK_PIN(
11641 + 254, "GPIO254",
11642 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
11643 + DRV_GRP3,
11644 + MTK_FUNCTION(0, "GPIO254"),
11645 + MTK_FUNCTION(1, "I2S1_MCK"),
11646 + MTK_FUNCTION(2, "I2S2_MCK"),
11647 + MTK_FUNCTION(3, "I2S0_MCK"),
11648 + MTK_FUNCTION(4, "I2S3_MCK"),
11649 + MTK_FUNCTION(5, "CLKM0"),
11650 + MTK_FUNCTION(7, "C2K_TDI")
11651 + ),
11652 + MTK_PIN(
11653 + 255, "GPIO255",
11654 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
11655 + DRV_GRP3,
11656 + MTK_FUNCTION(0, "GPIO255"),
11657 + MTK_FUNCTION(1, "CLKM1"),
11658 + MTK_FUNCTION(2, "DISP_PWM"),
11659 + MTK_FUNCTION(3, "PWM_B"),
11660 + MTK_FUNCTION(6, "TP_GPIO1_AO"),
11661 + MTK_FUNCTION(7, "C2K_TDO")
11662 + ),
11663 + MTK_PIN(
11664 + 256, "GPIO256",
11665 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
11666 + DRV_GRP3,
11667 + MTK_FUNCTION(0, "GPIO256"),
11668 + MTK_FUNCTION(1, "CLKM2"),
11669 + MTK_FUNCTION(2, "IRTX_OUT"),
11670 + MTK_FUNCTION(3, "PWM_C"),
11671 + MTK_FUNCTION(6, "TP_GPIO0_AO"),
11672 + MTK_FUNCTION(7, "C2K_NTRST")
11673 + ),
11674 + MTK_PIN(
11675 + 257, "GPIO257",
11676 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
11677 + DRV_GRP3,
11678 + MTK_FUNCTION(0, "GPIO257"),
11679 + MTK_FUNCTION(1, "IO_JTAG_TMS"),
11680 + MTK_FUNCTION(2, "LTE_JTAG_TMS"),
11681 + MTK_FUNCTION(3, "DFD_TMS"),
11682 + MTK_FUNCTION(4, "DAP_SIB1_SWD"),
11683 + MTK_FUNCTION(5, "ANC_JTAG_TMS"),
11684 + MTK_FUNCTION(6, "SCP_JTAG_TMS"),
11685 + MTK_FUNCTION(7, "C2K_DM_OTMS")
11686 + ),
11687 + MTK_PIN(
11688 + 258, "GPIO258",
11689 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
11690 + DRV_GRP3,
11691 + MTK_FUNCTION(0, "GPIO258"),
11692 + MTK_FUNCTION(1, "IO_JTAG_TCK"),
11693 + MTK_FUNCTION(2, "LTE_JTAG_TCK"),
11694 + MTK_FUNCTION(3, "DFD_TCK_XI"),
11695 + MTK_FUNCTION(4, "DAP_SIB1_SWCK"),
11696 + MTK_FUNCTION(5, "ANC_JTAG_TCK"),
11697 + MTK_FUNCTION(6, "SCP_JTAG_TCK"),
11698 + MTK_FUNCTION(7, "C2K_DM_OTCK")
11699 + ),
11700 + MTK_PIN(
11701 + 259, "GPIO259",
11702 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
11703 + DRV_GRP3,
11704 + MTK_FUNCTION(0, "GPIO259"),
11705 + MTK_FUNCTION(1, "IO_JTAG_TDI"),
11706 + MTK_FUNCTION(2, "LTE_JTAG_TDI"),
11707 + MTK_FUNCTION(3, "DFD_TDI"),
11708 + MTK_FUNCTION(5, "ANC_JTAG_TDI"),
11709 + MTK_FUNCTION(6, "SCP_JTAG_TDI"),
11710 + MTK_FUNCTION(7, "C2K_DM_OTDI")
11711 + ),
11712 + MTK_PIN(
11713 + 260, "GPIO260",
11714 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
11715 + DRV_GRP3,
11716 + MTK_FUNCTION(0, "GPIO260"),
11717 + MTK_FUNCTION(1, "IO_JTAG_TDO"),
11718 + MTK_FUNCTION(2, "LTE_JTAG_TDO"),
11719 + MTK_FUNCTION(3, "DFD_TDO"),
11720 + MTK_FUNCTION(5, "ANC_JTAG_TDO"),
11721 + MTK_FUNCTION(6, "SCP_JTAG_TDO"),
11722 + MTK_FUNCTION(7, "C2K_DM_OTDO")
11723 + ),
11724 + MTK_PIN(
11725 + 261, "GPIO261",
11726 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
11727 + DRV_GRP3,
11728 + MTK_FUNCTION(0, "GPIO261"),
11729 + MTK_FUNCTION(2, "LTE_JTAG_TRSTN"),
11730 + MTK_FUNCTION(3, "DFD_NTRST"),
11731 + MTK_FUNCTION(5, "ANC_JTAG_TRSTN"),
11732 + MTK_FUNCTION(6, "SCP_JTAG_TRSTN"),
11733 + MTK_FUNCTION(7, "C2K_DM_JTINTP")
11734 + ),
11735 +};
11736 +
11737 +#endif /* __PINCTRL_MTK_MT6797_H */
11738 --- /dev/null
11739 +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-mt8183.h
11740 @@ -0,0 +1,1916 @@
11741 +/* SPDX-License-Identifier: GPL-2.0 */
11742 +/*
11743 + * Copyright (C) 2018 MediaTek Inc.
11744 + *
11745 + * Author: Zhiyong Tao <zhiyong.tao@mediatek.com>
11746 + *
11747 + */
11748 +
11749 +#ifndef __PINCTRL_MTK_MT8183_H
11750 +#define __PINCTRL_MTK_MT8183_H
11751 +
11752 +#include "pinctrl-paris.h"
11753 +
11754 +static struct mtk_pin_desc mtk_pins_mt8183[] = {
11755 + MTK_PIN(
11756 + 0, "GPIO0",
11757 + MTK_EINT_FUNCTION(0, 0),
11758 + DRV_GRP4,
11759 + MTK_FUNCTION(0, "GPIO0"),
11760 + MTK_FUNCTION(1, "MRG_SYNC"),
11761 + MTK_FUNCTION(2, "PCM0_SYNC"),
11762 + MTK_FUNCTION(3, "TP_GPIO0_AO"),
11763 + MTK_FUNCTION(4, "SRCLKENAI0"),
11764 + MTK_FUNCTION(5, "SCP_SPI2_CS"),
11765 + MTK_FUNCTION(6, "I2S3_MCK"),
11766 + MTK_FUNCTION(7, "SPI2_CSB")
11767 + ),
11768 + MTK_PIN(
11769 + 1, "GPIO1",
11770 + MTK_EINT_FUNCTION(0, 1),
11771 + DRV_GRP4,
11772 + MTK_FUNCTION(0, "GPIO1"),
11773 + MTK_FUNCTION(1, "MRG_CLK"),
11774 + MTK_FUNCTION(2, "PCM0_CLK"),
11775 + MTK_FUNCTION(3, "TP_GPIO1_AO"),
11776 + MTK_FUNCTION(4, "CLKM3"),
11777 + MTK_FUNCTION(5, "SCP_SPI2_MO"),
11778 + MTK_FUNCTION(6, "I2S3_BCK"),
11779 + MTK_FUNCTION(7, "SPI2_MO")
11780 + ),
11781 + MTK_PIN(
11782 + 2, "GPIO2",
11783 + MTK_EINT_FUNCTION(0, 2),
11784 + DRV_GRP4,
11785 + MTK_FUNCTION(0, "GPIO2"),
11786 + MTK_FUNCTION(1, "MRG_DO"),
11787 + MTK_FUNCTION(2, "PCM0_DO"),
11788 + MTK_FUNCTION(3, "TP_GPIO2_AO"),
11789 + MTK_FUNCTION(4, "SCL6"),
11790 + MTK_FUNCTION(5, "SCP_SPI2_CK"),
11791 + MTK_FUNCTION(6, "I2S3_LRCK"),
11792 + MTK_FUNCTION(7, "SPI2_CLK")
11793 + ),
11794 + MTK_PIN(
11795 + 3, "GPIO3",
11796 + MTK_EINT_FUNCTION(0, 3),
11797 + DRV_GRP4,
11798 + MTK_FUNCTION(0, "GPIO3"),
11799 + MTK_FUNCTION(1, "MRG_DI"),
11800 + MTK_FUNCTION(2, "PCM0_DI"),
11801 + MTK_FUNCTION(3, "TP_GPIO3_AO"),
11802 + MTK_FUNCTION(4, "SDA6"),
11803 + MTK_FUNCTION(5, "TDM_MCK"),
11804 + MTK_FUNCTION(6, "I2S3_DO"),
11805 + MTK_FUNCTION(7, "SCP_VREQ_VAO")
11806 + ),
11807 + MTK_PIN(
11808 + 4, "GPIO4",
11809 + MTK_EINT_FUNCTION(0, 4),
11810 + DRV_GRP4,
11811 + MTK_FUNCTION(0, "GPIO4"),
11812 + MTK_FUNCTION(1, "PWM_B"),
11813 + MTK_FUNCTION(2, "I2S0_MCK"),
11814 + MTK_FUNCTION(3, "SSPM_UTXD_AO"),
11815 + MTK_FUNCTION(4, "MD_URXD1"),
11816 + MTK_FUNCTION(5, "TDM_BCK"),
11817 + MTK_FUNCTION(6, "TP_GPIO4_AO"),
11818 + MTK_FUNCTION(7, "DAP_MD32_SWD")
11819 + ),
11820 + MTK_PIN(
11821 + 5, "GPIO5",
11822 + MTK_EINT_FUNCTION(0, 5),
11823 + DRV_GRP4,
11824 + MTK_FUNCTION(0, "GPIO5"),
11825 + MTK_FUNCTION(1, "PWM_C"),
11826 + MTK_FUNCTION(2, "I2S0_BCK"),
11827 + MTK_FUNCTION(3, "SSPM_URXD_AO"),
11828 + MTK_FUNCTION(4, "MD_UTXD1"),
11829 + MTK_FUNCTION(5, "TDM_LRCK"),
11830 + MTK_FUNCTION(6, "TP_GPIO5_AO"),
11831 + MTK_FUNCTION(7, "DAP_MD32_SWCK")
11832 + ),
11833 + MTK_PIN(
11834 + 6, "GPIO6",
11835 + MTK_EINT_FUNCTION(0, 6),
11836 + DRV_GRP4,
11837 + MTK_FUNCTION(0, "GPIO6"),
11838 + MTK_FUNCTION(1, "PWM_A"),
11839 + MTK_FUNCTION(2, "I2S0_LRCK"),
11840 + MTK_FUNCTION(3, "IDDIG"),
11841 + MTK_FUNCTION(4, "MD_URXD0"),
11842 + MTK_FUNCTION(5, "TDM_DATA0"),
11843 + MTK_FUNCTION(6, "TP_GPIO6_AO"),
11844 + MTK_FUNCTION(7, "CMFLASH")
11845 + ),
11846 + MTK_PIN(
11847 + 7, "GPIO7",
11848 + MTK_EINT_FUNCTION(0, 7),
11849 + DRV_GRP4,
11850 + MTK_FUNCTION(0, "GPIO7"),
11851 + MTK_FUNCTION(1, "SPI1_B_MI"),
11852 + MTK_FUNCTION(2, "I2S0_DI"),
11853 + MTK_FUNCTION(3, "USB_DRVVBUS"),
11854 + MTK_FUNCTION(4, "MD_UTXD0"),
11855 + MTK_FUNCTION(5, "TDM_DATA1"),
11856 + MTK_FUNCTION(6, "TP_GPIO7_AO"),
11857 + MTK_FUNCTION(7, "DVFSRC_EXT_REQ")
11858 + ),
11859 + MTK_PIN(
11860 + 8, "GPIO8",
11861 + MTK_EINT_FUNCTION(0, 8),
11862 + DRV_GRP4,
11863 + MTK_FUNCTION(0, "GPIO8"),
11864 + MTK_FUNCTION(1, "SPI1_B_CSB"),
11865 + MTK_FUNCTION(2, "ANT_SEL3"),
11866 + MTK_FUNCTION(3, "SCL7"),
11867 + MTK_FUNCTION(4, "CONN_MCU_TRST_B"),
11868 + MTK_FUNCTION(5, "TDM_DATA2"),
11869 + MTK_FUNCTION(6, "MD_INT0"),
11870 + MTK_FUNCTION(7, "JTRSTN_SEL1")
11871 + ),
11872 + MTK_PIN(
11873 + 9, "GPIO9",
11874 + MTK_EINT_FUNCTION(0, 9),
11875 + DRV_GRP4,
11876 + MTK_FUNCTION(0, "GPIO9"),
11877 + MTK_FUNCTION(1, "SPI1_B_MO"),
11878 + MTK_FUNCTION(2, "ANT_SEL4"),
11879 + MTK_FUNCTION(3, "CMMCLK2"),
11880 + MTK_FUNCTION(4, "CONN_MCU_DBGACK_N"),
11881 + MTK_FUNCTION(5, "SSPM_JTAG_TRSTN"),
11882 + MTK_FUNCTION(6, "IO_JTAG_TRSTN"),
11883 + MTK_FUNCTION(7, "DBG_MON_B10")
11884 + ),
11885 + MTK_PIN(
11886 + 10, "GPIO10",
11887 + MTK_EINT_FUNCTION(0, 10),
11888 + DRV_GRP4,
11889 + MTK_FUNCTION(0, "GPIO10"),
11890 + MTK_FUNCTION(1, "SPI1_B_CLK"),
11891 + MTK_FUNCTION(2, "ANT_SEL5"),
11892 + MTK_FUNCTION(3, "CMMCLK3"),
11893 + MTK_FUNCTION(4, "CONN_MCU_DBGI_N"),
11894 + MTK_FUNCTION(5, "TDM_DATA3"),
11895 + MTK_FUNCTION(6, "EXT_FRAME_SYNC"),
11896 + MTK_FUNCTION(7, "DBG_MON_B11")
11897 + ),
11898 + MTK_PIN(
11899 + 11, "GPIO11",
11900 + MTK_EINT_FUNCTION(0, 11),
11901 + DRV_GRP4,
11902 + MTK_FUNCTION(0, "GPIO11"),
11903 + MTK_FUNCTION(1, "TP_URXD1_AO"),
11904 + MTK_FUNCTION(2, "IDDIG"),
11905 + MTK_FUNCTION(3, "SCL6"),
11906 + MTK_FUNCTION(4, "UCTS1"),
11907 + MTK_FUNCTION(5, "UCTS0"),
11908 + MTK_FUNCTION(6, "SRCLKENAI1"),
11909 + MTK_FUNCTION(7, "I2S5_MCK")
11910 + ),
11911 + MTK_PIN(
11912 + 12, "GPIO12",
11913 + MTK_EINT_FUNCTION(0, 12),
11914 + DRV_GRP4,
11915 + MTK_FUNCTION(0, "GPIO12"),
11916 + MTK_FUNCTION(1, "TP_UTXD1_AO"),
11917 + MTK_FUNCTION(2, "USB_DRVVBUS"),
11918 + MTK_FUNCTION(3, "SDA6"),
11919 + MTK_FUNCTION(4, "URTS1"),
11920 + MTK_FUNCTION(5, "URTS0"),
11921 + MTK_FUNCTION(6, "I2S2_DI2"),
11922 + MTK_FUNCTION(7, "I2S5_BCK")
11923 + ),
11924 + MTK_PIN(
11925 + 13, "GPIO13",
11926 + MTK_EINT_FUNCTION(0, 13),
11927 + DRV_GRP4,
11928 + MTK_FUNCTION(0, "GPIO13"),
11929 + MTK_FUNCTION(1, "DBPI_D0"),
11930 + MTK_FUNCTION(2, "SPI5_MI"),
11931 + MTK_FUNCTION(3, "PCM0_SYNC"),
11932 + MTK_FUNCTION(4, "MD_URXD0"),
11933 + MTK_FUNCTION(5, "ANT_SEL3"),
11934 + MTK_FUNCTION(6, "I2S0_MCK"),
11935 + MTK_FUNCTION(7, "DBG_MON_B15")
11936 + ),
11937 + MTK_PIN(
11938 + 14, "GPIO14",
11939 + MTK_EINT_FUNCTION(0, 14),
11940 + DRV_GRP4,
11941 + MTK_FUNCTION(0, "GPIO14"),
11942 + MTK_FUNCTION(1, "DBPI_D1"),
11943 + MTK_FUNCTION(2, "SPI5_CSB"),
11944 + MTK_FUNCTION(3, "PCM0_CLK"),
11945 + MTK_FUNCTION(4, "MD_UTXD0"),
11946 + MTK_FUNCTION(5, "ANT_SEL4"),
11947 + MTK_FUNCTION(6, "I2S0_BCK"),
11948 + MTK_FUNCTION(7, "DBG_MON_B16")
11949 + ),
11950 + MTK_PIN(
11951 + 15, "GPIO15",
11952 + MTK_EINT_FUNCTION(0, 15),
11953 + DRV_GRP4,
11954 + MTK_FUNCTION(0, "GPIO15"),
11955 + MTK_FUNCTION(1, "DBPI_D2"),
11956 + MTK_FUNCTION(2, "SPI5_MO"),
11957 + MTK_FUNCTION(3, "PCM0_DO"),
11958 + MTK_FUNCTION(4, "MD_URXD1"),
11959 + MTK_FUNCTION(5, "ANT_SEL5"),
11960 + MTK_FUNCTION(6, "I2S0_LRCK"),
11961 + MTK_FUNCTION(7, "DBG_MON_B17")
11962 + ),
11963 + MTK_PIN(
11964 + 16, "GPIO16",
11965 + MTK_EINT_FUNCTION(0, 16),
11966 + DRV_GRP4,
11967 + MTK_FUNCTION(0, "GPIO16"),
11968 + MTK_FUNCTION(1, "DBPI_D3"),
11969 + MTK_FUNCTION(2, "SPI5_CLK"),
11970 + MTK_FUNCTION(3, "PCM0_DI"),
11971 + MTK_FUNCTION(4, "MD_UTXD1"),
11972 + MTK_FUNCTION(5, "ANT_SEL6"),
11973 + MTK_FUNCTION(6, "I2S0_DI"),
11974 + MTK_FUNCTION(7, "DBG_MON_B23")
11975 + ),
11976 + MTK_PIN(
11977 + 17, "GPIO17",
11978 + MTK_EINT_FUNCTION(0, 17),
11979 + DRV_GRP4,
11980 + MTK_FUNCTION(0, "GPIO17"),
11981 + MTK_FUNCTION(1, "DBPI_D4"),
11982 + MTK_FUNCTION(2, "SPI4_MI"),
11983 + MTK_FUNCTION(3, "CONN_MCU_TRST_B"),
11984 + MTK_FUNCTION(4, "MD_INT0"),
11985 + MTK_FUNCTION(5, "ANT_SEL7"),
11986 + MTK_FUNCTION(6, "I2S3_MCK"),
11987 + MTK_FUNCTION(7, "DBG_MON_A1")
11988 + ),
11989 + MTK_PIN(
11990 + 18, "GPIO18",
11991 + MTK_EINT_FUNCTION(0, 18),
11992 + DRV_GRP4,
11993 + MTK_FUNCTION(0, "GPIO18"),
11994 + MTK_FUNCTION(1, "DBPI_D5"),
11995 + MTK_FUNCTION(2, "SPI4_CSB"),
11996 + MTK_FUNCTION(3, "CONN_MCU_DBGI_N"),
11997 + MTK_FUNCTION(4, "MD_INT0"),
11998 + MTK_FUNCTION(5, "SCP_VREQ_VAO"),
11999 + MTK_FUNCTION(6, "I2S3_BCK"),
12000 + MTK_FUNCTION(7, "DBG_MON_A2")
12001 + ),
12002 + MTK_PIN(
12003 + 19, "GPIO19",
12004 + MTK_EINT_FUNCTION(0, 19),
12005 + DRV_GRP4,
12006 + MTK_FUNCTION(0, "GPIO19"),
12007 + MTK_FUNCTION(1, "DBPI_D6"),
12008 + MTK_FUNCTION(2, "SPI4_MO"),
12009 + MTK_FUNCTION(3, "CONN_MCU_TDO"),
12010 + MTK_FUNCTION(4, "MD_INT2_C2K_UIM1_HOT_PLUG"),
12011 + MTK_FUNCTION(5, "URXD1"),
12012 + MTK_FUNCTION(6, "I2S3_LRCK"),
12013 + MTK_FUNCTION(7, "DBG_MON_A3")
12014 + ),
12015 + MTK_PIN(
12016 + 20, "GPIO20",
12017 + MTK_EINT_FUNCTION(0, 20),
12018 + DRV_GRP4,
12019 + MTK_FUNCTION(0, "GPIO20"),
12020 + MTK_FUNCTION(1, "DBPI_D7"),
12021 + MTK_FUNCTION(2, "SPI4_CLK"),
12022 + MTK_FUNCTION(3, "CONN_MCU_DBGACK_N"),
12023 + MTK_FUNCTION(4, "MD_INT1_C2K_UIM0_HOT_PLUG"),
12024 + MTK_FUNCTION(5, "UTXD1"),
12025 + MTK_FUNCTION(6, "I2S3_DO"),
12026 + MTK_FUNCTION(7, "DBG_MON_A19")
12027 + ),
12028 + MTK_PIN(
12029 + 21, "GPIO21",
12030 + MTK_EINT_FUNCTION(0, 21),
12031 + DRV_GRP4,
12032 + MTK_FUNCTION(0, "GPIO21"),
12033 + MTK_FUNCTION(1, "DBPI_D8"),
12034 + MTK_FUNCTION(2, "SPI3_MI"),
12035 + MTK_FUNCTION(3, "CONN_MCU_TMS"),
12036 + MTK_FUNCTION(4, "DAP_MD32_SWD"),
12037 + MTK_FUNCTION(5, "CONN_MCU_AICE_TMSC"),
12038 + MTK_FUNCTION(6, "I2S2_MCK"),
12039 + MTK_FUNCTION(7, "DBG_MON_B5")
12040 + ),
12041 + MTK_PIN(
12042 + 22, "GPIO22",
12043 + MTK_EINT_FUNCTION(0, 22),
12044 + DRV_GRP4,
12045 + MTK_FUNCTION(0, "GPIO22"),
12046 + MTK_FUNCTION(1, "DBPI_D9"),
12047 + MTK_FUNCTION(2, "SPI3_CSB"),
12048 + MTK_FUNCTION(3, "CONN_MCU_TCK"),
12049 + MTK_FUNCTION(4, "DAP_MD32_SWCK"),
12050 + MTK_FUNCTION(5, "CONN_MCU_AICE_TCKC"),
12051 + MTK_FUNCTION(6, "I2S2_BCK"),
12052 + MTK_FUNCTION(7, "DBG_MON_B6")
12053 + ),
12054 + MTK_PIN(
12055 + 23, "GPIO23",
12056 + MTK_EINT_FUNCTION(0, 23),
12057 + DRV_GRP4,
12058 + MTK_FUNCTION(0, "GPIO23"),
12059 + MTK_FUNCTION(1, "DBPI_D10"),
12060 + MTK_FUNCTION(2, "SPI3_MO"),
12061 + MTK_FUNCTION(3, "CONN_MCU_TDI"),
12062 + MTK_FUNCTION(4, "UCTS1"),
12063 + MTK_FUNCTION(5, "EXT_FRAME_SYNC"),
12064 + MTK_FUNCTION(6, "I2S2_LRCK"),
12065 + MTK_FUNCTION(7, "DBG_MON_B7")
12066 + ),
12067 + MTK_PIN(
12068 + 24, "GPIO24",
12069 + MTK_EINT_FUNCTION(0, 24),
12070 + DRV_GRP4,
12071 + MTK_FUNCTION(0, "GPIO24"),
12072 + MTK_FUNCTION(1, "DBPI_D11"),
12073 + MTK_FUNCTION(2, "SPI3_CLK"),
12074 + MTK_FUNCTION(3, "SRCLKENAI0"),
12075 + MTK_FUNCTION(4, "URTS1"),
12076 + MTK_FUNCTION(5, "IO_JTAG_TCK"),
12077 + MTK_FUNCTION(6, "I2S2_DI"),
12078 + MTK_FUNCTION(7, "DBG_MON_B31")
12079 + ),
12080 + MTK_PIN(
12081 + 25, "GPIO25",
12082 + MTK_EINT_FUNCTION(0, 25),
12083 + DRV_GRP4,
12084 + MTK_FUNCTION(0, "GPIO25"),
12085 + MTK_FUNCTION(1, "DBPI_HSYNC"),
12086 + MTK_FUNCTION(2, "ANT_SEL0"),
12087 + MTK_FUNCTION(3, "SCL6"),
12088 + MTK_FUNCTION(4, "KPCOL2"),
12089 + MTK_FUNCTION(5, "IO_JTAG_TMS"),
12090 + MTK_FUNCTION(6, "I2S1_MCK"),
12091 + MTK_FUNCTION(7, "DBG_MON_B0")
12092 + ),
12093 + MTK_PIN(
12094 + 26, "GPIO26",
12095 + MTK_EINT_FUNCTION(0, 26),
12096 + DRV_GRP4,
12097 + MTK_FUNCTION(0, "GPIO26"),
12098 + MTK_FUNCTION(1, "DBPI_VSYNC"),
12099 + MTK_FUNCTION(2, "ANT_SEL1"),
12100 + MTK_FUNCTION(3, "SDA6"),
12101 + MTK_FUNCTION(4, "KPROW2"),
12102 + MTK_FUNCTION(5, "IO_JTAG_TDI"),
12103 + MTK_FUNCTION(6, "I2S1_BCK"),
12104 + MTK_FUNCTION(7, "DBG_MON_B1")
12105 + ),
12106 + MTK_PIN(
12107 + 27, "GPIO27",
12108 + MTK_EINT_FUNCTION(0, 27),
12109 + DRV_GRP4,
12110 + MTK_FUNCTION(0, "GPIO27"),
12111 + MTK_FUNCTION(1, "DBPI_DE"),
12112 + MTK_FUNCTION(2, "ANT_SEL2"),
12113 + MTK_FUNCTION(3, "SCL7"),
12114 + MTK_FUNCTION(4, "DMIC_CLK"),
12115 + MTK_FUNCTION(5, "IO_JTAG_TDO"),
12116 + MTK_FUNCTION(6, "I2S1_LRCK"),
12117 + MTK_FUNCTION(7, "DBG_MON_B9")
12118 + ),
12119 + MTK_PIN(
12120 + 28, "GPIO28",
12121 + MTK_EINT_FUNCTION(0, 28),
12122 + DRV_GRP4,
12123 + MTK_FUNCTION(0, "GPIO28"),
12124 + MTK_FUNCTION(1, "DBPI_CK"),
12125 + MTK_FUNCTION(2, "DVFSRC_EXT_REQ"),
12126 + MTK_FUNCTION(3, "SDA7"),
12127 + MTK_FUNCTION(4, "DMIC_DAT"),
12128 + MTK_FUNCTION(5, "IO_JTAG_TRSTN"),
12129 + MTK_FUNCTION(6, "I2S1_DO"),
12130 + MTK_FUNCTION(7, "DBG_MON_B32")
12131 + ),
12132 + MTK_PIN(
12133 + 29, "GPIO29",
12134 + MTK_EINT_FUNCTION(0, 29),
12135 + DRV_GRP4,
12136 + MTK_FUNCTION(0, "GPIO29"),
12137 + MTK_FUNCTION(1, "MSDC1_CLK"),
12138 + MTK_FUNCTION(2, "IO_JTAG_TCK"),
12139 + MTK_FUNCTION(3, "UDI_TCK"),
12140 + MTK_FUNCTION(4, "CONN_DSP_JCK"),
12141 + MTK_FUNCTION(5, "SSPM_JTAG_TCK"),
12142 + MTK_FUNCTION(6, "PCM1_CLK"),
12143 + MTK_FUNCTION(7, "DBG_MON_A6")
12144 + ),
12145 + MTK_PIN(
12146 + 30, "GPIO30",
12147 + MTK_EINT_FUNCTION(0, 30),
12148 + DRV_GRP4,
12149 + MTK_FUNCTION(0, "GPIO30"),
12150 + MTK_FUNCTION(1, "MSDC1_DAT3"),
12151 + MTK_FUNCTION(2, "DAP_MD32_SWD"),
12152 + MTK_FUNCTION(3, "CONN_MCU_AICE_TMSC"),
12153 + MTK_FUNCTION(4, "CONN_DSP_JINTP"),
12154 + MTK_FUNCTION(5, "SSPM_JTAG_TRSTN"),
12155 + MTK_FUNCTION(6, "PCM1_DI"),
12156 + MTK_FUNCTION(7, "DBG_MON_A7")
12157 + ),
12158 + MTK_PIN(
12159 + 31, "GPIO31",
12160 + MTK_EINT_FUNCTION(0, 31),
12161 + DRV_GRP4,
12162 + MTK_FUNCTION(0, "GPIO31"),
12163 + MTK_FUNCTION(1, "MSDC1_CMD"),
12164 + MTK_FUNCTION(2, "IO_JTAG_TMS"),
12165 + MTK_FUNCTION(3, "UDI_TMS"),
12166 + MTK_FUNCTION(4, "CONN_DSP_JMS"),
12167 + MTK_FUNCTION(5, "SSPM_JTAG_TMS"),
12168 + MTK_FUNCTION(6, "PCM1_SYNC"),
12169 + MTK_FUNCTION(7, "DBG_MON_A8")
12170 + ),
12171 + MTK_PIN(
12172 + 32, "GPIO32",
12173 + MTK_EINT_FUNCTION(0, 32),
12174 + DRV_GRP4,
12175 + MTK_FUNCTION(0, "GPIO32"),
12176 + MTK_FUNCTION(1, "MSDC1_DAT0"),
12177 + MTK_FUNCTION(2, "IO_JTAG_TDI"),
12178 + MTK_FUNCTION(3, "UDI_TDI"),
12179 + MTK_FUNCTION(4, "CONN_DSP_JDI"),
12180 + MTK_FUNCTION(5, "SSPM_JTAG_TDI"),
12181 + MTK_FUNCTION(6, "PCM1_DO0"),
12182 + MTK_FUNCTION(7, "DBG_MON_A9")
12183 + ),
12184 + MTK_PIN(
12185 + 33, "GPIO33",
12186 + MTK_EINT_FUNCTION(0, 33),
12187 + DRV_GRP4,
12188 + MTK_FUNCTION(0, "GPIO33"),
12189 + MTK_FUNCTION(1, "MSDC1_DAT2"),
12190 + MTK_FUNCTION(2, "IO_JTAG_TRSTN"),
12191 + MTK_FUNCTION(3, "UDI_NTRST"),
12192 + MTK_FUNCTION(4, "DAP_MD32_SWCK"),
12193 + MTK_FUNCTION(5, "CONN_MCU_AICE_TCKC"),
12194 + MTK_FUNCTION(6, "PCM1_DO2"),
12195 + MTK_FUNCTION(7, "DBG_MON_A10")
12196 + ),
12197 + MTK_PIN(
12198 + 34, "GPIO34",
12199 + MTK_EINT_FUNCTION(0, 34),
12200 + DRV_GRP4,
12201 + MTK_FUNCTION(0, "GPIO34"),
12202 + MTK_FUNCTION(1, "MSDC1_DAT1"),
12203 + MTK_FUNCTION(2, "IO_JTAG_TDO"),
12204 + MTK_FUNCTION(3, "UDI_TDO"),
12205 + MTK_FUNCTION(4, "CONN_DSP_JDO"),
12206 + MTK_FUNCTION(5, "SSPM_JTAG_TDO"),
12207 + MTK_FUNCTION(6, "PCM1_DO1"),
12208 + MTK_FUNCTION(7, "DBG_MON_A11")
12209 + ),
12210 + MTK_PIN(
12211 + 35, "GPIO35",
12212 + MTK_EINT_FUNCTION(0, 35),
12213 + DRV_GRP4,
12214 + MTK_FUNCTION(0, "GPIO35"),
12215 + MTK_FUNCTION(1, "MD1_SIM2_SIO"),
12216 + MTK_FUNCTION(2, "CCU_JTAG_TDO"),
12217 + MTK_FUNCTION(3, "MD1_SIM1_SIO"),
12218 + MTK_FUNCTION(5, "SCP_JTAG_TDO"),
12219 + MTK_FUNCTION(6, "CONN_DSP_JMS"),
12220 + MTK_FUNCTION(7, "DBG_MON_A28")
12221 + ),
12222 + MTK_PIN(
12223 + 36, "GPIO36",
12224 + MTK_EINT_FUNCTION(0, 36),
12225 + DRV_GRP4,
12226 + MTK_FUNCTION(0, "GPIO36"),
12227 + MTK_FUNCTION(1, "MD1_SIM2_SRST"),
12228 + MTK_FUNCTION(2, "CCU_JTAG_TMS"),
12229 + MTK_FUNCTION(3, "MD1_SIM1_SRST"),
12230 + MTK_FUNCTION(4, "CONN_MCU_AICE_TMSC"),
12231 + MTK_FUNCTION(5, "SCP_JTAG_TMS"),
12232 + MTK_FUNCTION(6, "CONN_DSP_JINTP"),
12233 + MTK_FUNCTION(7, "DBG_MON_A29")
12234 + ),
12235 + MTK_PIN(
12236 + 37, "GPIO37",
12237 + MTK_EINT_FUNCTION(0, 37),
12238 + DRV_GRP4,
12239 + MTK_FUNCTION(0, "GPIO37"),
12240 + MTK_FUNCTION(1, "MD1_SIM2_SCLK"),
12241 + MTK_FUNCTION(2, "CCU_JTAG_TDI"),
12242 + MTK_FUNCTION(3, "MD1_SIM1_SCLK"),
12243 + MTK_FUNCTION(5, "SCP_JTAG_TDI"),
12244 + MTK_FUNCTION(6, "CONN_DSP_JDO"),
12245 + MTK_FUNCTION(7, "DBG_MON_A30")
12246 + ),
12247 + MTK_PIN(
12248 + 38, "GPIO38",
12249 + MTK_EINT_FUNCTION(0, 38),
12250 + DRV_GRP4,
12251 + MTK_FUNCTION(0, "GPIO38"),
12252 + MTK_FUNCTION(1, "MD1_SIM1_SCLK"),
12253 + MTK_FUNCTION(3, "MD1_SIM2_SCLK"),
12254 + MTK_FUNCTION(4, "CONN_MCU_AICE_TCKC"),
12255 + MTK_FUNCTION(7, "DBG_MON_A20")
12256 + ),
12257 + MTK_PIN(
12258 + 39, "GPIO39",
12259 + MTK_EINT_FUNCTION(0, 39),
12260 + DRV_GRP4,
12261 + MTK_FUNCTION(0, "GPIO39"),
12262 + MTK_FUNCTION(1, "MD1_SIM1_SRST"),
12263 + MTK_FUNCTION(2, "CCU_JTAG_TCK"),
12264 + MTK_FUNCTION(3, "MD1_SIM2_SRST"),
12265 + MTK_FUNCTION(5, "SCP_JTAG_TCK"),
12266 + MTK_FUNCTION(6, "CONN_DSP_JCK"),
12267 + MTK_FUNCTION(7, "DBG_MON_A31")
12268 + ),
12269 + MTK_PIN(
12270 + 40, "GPIO40",
12271 + MTK_EINT_FUNCTION(0, 40),
12272 + DRV_GRP4,
12273 + MTK_FUNCTION(0, "GPIO40"),
12274 + MTK_FUNCTION(1, "MD1_SIM1_SIO"),
12275 + MTK_FUNCTION(2, "CCU_JTAG_TRST"),
12276 + MTK_FUNCTION(3, "MD1_SIM2_SIO"),
12277 + MTK_FUNCTION(5, "SCP_JTAG_TRSTN"),
12278 + MTK_FUNCTION(6, "CONN_DSP_JDI"),
12279 + MTK_FUNCTION(7, "DBG_MON_A32")
12280 + ),
12281 + MTK_PIN(
12282 + 41, "GPIO41",
12283 + MTK_EINT_FUNCTION(0, 41),
12284 + DRV_GRP4,
12285 + MTK_FUNCTION(0, "GPIO41"),
12286 + MTK_FUNCTION(1, "IDDIG"),
12287 + MTK_FUNCTION(2, "URXD1"),
12288 + MTK_FUNCTION(3, "UCTS0"),
12289 + MTK_FUNCTION(4, "SSPM_UTXD_AO"),
12290 + MTK_FUNCTION(5, "EXT_FRAME_SYNC"),
12291 + MTK_FUNCTION(6, "DMIC_CLK")
12292 + ),
12293 + MTK_PIN(
12294 + 42, "GPIO42",
12295 + MTK_EINT_FUNCTION(0, 42),
12296 + DRV_GRP4,
12297 + MTK_FUNCTION(0, "GPIO42"),
12298 + MTK_FUNCTION(1, "USB_DRVVBUS"),
12299 + MTK_FUNCTION(2, "UTXD1"),
12300 + MTK_FUNCTION(3, "URTS0"),
12301 + MTK_FUNCTION(4, "SSPM_URXD_AO"),
12302 + MTK_FUNCTION(5, "EXT_FRAME_SYNC"),
12303 + MTK_FUNCTION(6, "DMIC_DAT")
12304 + ),
12305 + MTK_PIN(
12306 + 43, "GPIO43",
12307 + MTK_EINT_FUNCTION(0, 43),
12308 + DRV_GRP4,
12309 + MTK_FUNCTION(0, "GPIO43"),
12310 + MTK_FUNCTION(1, "DISP_PWM")
12311 + ),
12312 + MTK_PIN(
12313 + 44, "GPIO44",
12314 + MTK_EINT_FUNCTION(0, 44),
12315 + DRV_GRP4,
12316 + MTK_FUNCTION(0, "GPIO44"),
12317 + MTK_FUNCTION(1, "DSI_TE")
12318 + ),
12319 + MTK_PIN(
12320 + 45, "GPIO45",
12321 + MTK_EINT_FUNCTION(0, 45),
12322 + DRV_GRP4,
12323 + MTK_FUNCTION(0, "GPIO45"),
12324 + MTK_FUNCTION(1, "LCM_RST")
12325 + ),
12326 + MTK_PIN(
12327 + 46, "GPIO46",
12328 + MTK_EINT_FUNCTION(0, 46),
12329 + DRV_GRP4,
12330 + MTK_FUNCTION(0, "GPIO46"),
12331 + MTK_FUNCTION(1, "MD_INT2_C2K_UIM1_HOT_PLUG"),
12332 + MTK_FUNCTION(2, "URXD1"),
12333 + MTK_FUNCTION(3, "UCTS1"),
12334 + MTK_FUNCTION(4, "CCU_UTXD_AO"),
12335 + MTK_FUNCTION(5, "TP_UCTS1_AO"),
12336 + MTK_FUNCTION(6, "IDDIG"),
12337 + MTK_FUNCTION(7, "I2S5_LRCK")
12338 + ),
12339 + MTK_PIN(
12340 + 47, "GPIO47",
12341 + MTK_EINT_FUNCTION(0, 47),
12342 + DRV_GRP4,
12343 + MTK_FUNCTION(0, "GPIO47"),
12344 + MTK_FUNCTION(1, "MD_INT1_C2K_UIM0_HOT_PLUG"),
12345 + MTK_FUNCTION(2, "UTXD1"),
12346 + MTK_FUNCTION(3, "URTS1"),
12347 + MTK_FUNCTION(4, "CCU_URXD_AO"),
12348 + MTK_FUNCTION(5, "TP_URTS1_AO"),
12349 + MTK_FUNCTION(6, "USB_DRVVBUS"),
12350 + MTK_FUNCTION(7, "I2S5_DO")
12351 + ),
12352 + MTK_PIN(
12353 + 48, "GPIO48",
12354 + MTK_EINT_FUNCTION(0, 48),
12355 + DRV_GRP4,
12356 + MTK_FUNCTION(0, "GPIO48"),
12357 + MTK_FUNCTION(1, "SCL5")
12358 + ),
12359 + MTK_PIN(
12360 + 49, "GPIO49",
12361 + MTK_EINT_FUNCTION(0, 49),
12362 + DRV_GRP4,
12363 + MTK_FUNCTION(0, "GPIO49"),
12364 + MTK_FUNCTION(1, "SDA5")
12365 + ),
12366 + MTK_PIN(
12367 + 50, "GPIO50",
12368 + MTK_EINT_FUNCTION(0, 50),
12369 + DRV_GRP4,
12370 + MTK_FUNCTION(0, "GPIO50"),
12371 + MTK_FUNCTION(1, "SCL3")
12372 + ),
12373 + MTK_PIN(
12374 + 51, "GPIO51",
12375 + MTK_EINT_FUNCTION(0, 51),
12376 + DRV_GRP4,
12377 + MTK_FUNCTION(0, "GPIO51"),
12378 + MTK_FUNCTION(1, "SDA3")
12379 + ),
12380 + MTK_PIN(
12381 + 52, "GPIO52",
12382 + MTK_EINT_FUNCTION(0, 52),
12383 + DRV_GRP4,
12384 + MTK_FUNCTION(0, "GPIO52"),
12385 + MTK_FUNCTION(1, "BPI_ANT2")
12386 + ),
12387 + MTK_PIN(
12388 + 53, "GPIO53",
12389 + MTK_EINT_FUNCTION(0, 53),
12390 + DRV_GRP4,
12391 + MTK_FUNCTION(0, "GPIO53"),
12392 + MTK_FUNCTION(1, "BPI_ANT0")
12393 + ),
12394 + MTK_PIN(
12395 + 54, "GPIO54",
12396 + MTK_EINT_FUNCTION(0, 54),
12397 + DRV_GRP4,
12398 + MTK_FUNCTION(0, "GPIO54"),
12399 + MTK_FUNCTION(1, "BPI_OLAT1")
12400 + ),
12401 + MTK_PIN(
12402 + 55, "GPIO55",
12403 + MTK_EINT_FUNCTION(0, 55),
12404 + DRV_GRP4,
12405 + MTK_FUNCTION(0, "GPIO55"),
12406 + MTK_FUNCTION(1, "BPI_BUS8")
12407 + ),
12408 + MTK_PIN(
12409 + 56, "GPIO56",
12410 + MTK_EINT_FUNCTION(0, 56),
12411 + DRV_GRP4,
12412 + MTK_FUNCTION(0, "GPIO56"),
12413 + MTK_FUNCTION(1, "BPI_BUS9"),
12414 + MTK_FUNCTION(2, "SCL_6306")
12415 + ),
12416 + MTK_PIN(
12417 + 57, "GPIO57",
12418 + MTK_EINT_FUNCTION(0, 57),
12419 + DRV_GRP4,
12420 + MTK_FUNCTION(0, "GPIO57"),
12421 + MTK_FUNCTION(1, "BPI_BUS10"),
12422 + MTK_FUNCTION(2, "SDA_6306")
12423 + ),
12424 + MTK_PIN(
12425 + 58, "GPIO58",
12426 + MTK_EINT_FUNCTION(0, 58),
12427 + DRV_GRP4,
12428 + MTK_FUNCTION(0, "GPIO58"),
12429 + MTK_FUNCTION(1, "RFIC0_BSI_D2"),
12430 + MTK_FUNCTION(2, "SPM_BSI_D2"),
12431 + MTK_FUNCTION(3, "PWM_B")
12432 + ),
12433 + MTK_PIN(
12434 + 59, "GPIO59",
12435 + MTK_EINT_FUNCTION(0, 59),
12436 + DRV_GRP4,
12437 + MTK_FUNCTION(0, "GPIO59"),
12438 + MTK_FUNCTION(1, "RFIC0_BSI_D1"),
12439 + MTK_FUNCTION(2, "SPM_BSI_D1")
12440 + ),
12441 + MTK_PIN(
12442 + 60, "GPIO60",
12443 + MTK_EINT_FUNCTION(0, 60),
12444 + DRV_GRP4,
12445 + MTK_FUNCTION(0, "GPIO60"),
12446 + MTK_FUNCTION(1, "RFIC0_BSI_D0"),
12447 + MTK_FUNCTION(2, "SPM_BSI_D0")
12448 + ),
12449 + MTK_PIN(
12450 + 61, "GPIO61",
12451 + MTK_EINT_FUNCTION(0, 61),
12452 + DRV_GRP4,
12453 + MTK_FUNCTION(0, "GPIO61"),
12454 + MTK_FUNCTION(1, "MIPI1_SDATA")
12455 + ),
12456 + MTK_PIN(
12457 + 62, "GPIO62",
12458 + MTK_EINT_FUNCTION(0, 62),
12459 + DRV_GRP4,
12460 + MTK_FUNCTION(0, "GPIO62"),
12461 + MTK_FUNCTION(1, "MIPI1_SCLK")
12462 + ),
12463 + MTK_PIN(
12464 + 63, "GPIO63",
12465 + MTK_EINT_FUNCTION(0, 63),
12466 + DRV_GRP4,
12467 + MTK_FUNCTION(0, "GPIO63"),
12468 + MTK_FUNCTION(1, "MIPI0_SDATA")
12469 + ),
12470 + MTK_PIN(
12471 + 64, "GPIO64",
12472 + MTK_EINT_FUNCTION(0, 64),
12473 + DRV_GRP4,
12474 + MTK_FUNCTION(0, "GPIO64"),
12475 + MTK_FUNCTION(1, "MIPI0_SCLK")
12476 + ),
12477 + MTK_PIN(
12478 + 65, "GPIO65",
12479 + MTK_EINT_FUNCTION(0, 65),
12480 + DRV_GRP4,
12481 + MTK_FUNCTION(0, "GPIO65"),
12482 + MTK_FUNCTION(1, "MIPI3_SDATA"),
12483 + MTK_FUNCTION(2, "BPI_OLAT2")
12484 + ),
12485 + MTK_PIN(
12486 + 66, "GPIO66",
12487 + MTK_EINT_FUNCTION(0, 66),
12488 + DRV_GRP4,
12489 + MTK_FUNCTION(0, "GPIO66"),
12490 + MTK_FUNCTION(1, "MIPI3_SCLK"),
12491 + MTK_FUNCTION(2, "BPI_OLAT3")
12492 + ),
12493 + MTK_PIN(
12494 + 67, "GPIO67",
12495 + MTK_EINT_FUNCTION(0, 67),
12496 + DRV_GRP4,
12497 + MTK_FUNCTION(0, "GPIO67"),
12498 + MTK_FUNCTION(1, "MIPI2_SDATA")
12499 + ),
12500 + MTK_PIN(
12501 + 68, "GPIO68",
12502 + MTK_EINT_FUNCTION(0, 68),
12503 + DRV_GRP4,
12504 + MTK_FUNCTION(0, "GPIO68"),
12505 + MTK_FUNCTION(1, "MIPI2_SCLK")
12506 + ),
12507 + MTK_PIN(
12508 + 69, "GPIO69",
12509 + MTK_EINT_FUNCTION(0, 69),
12510 + DRV_GRP4,
12511 + MTK_FUNCTION(0, "GPIO69"),
12512 + MTK_FUNCTION(1, "BPI_BUS7")
12513 + ),
12514 + MTK_PIN(
12515 + 70, "GPIO70",
12516 + MTK_EINT_FUNCTION(0, 70),
12517 + DRV_GRP4,
12518 + MTK_FUNCTION(0, "GPIO70"),
12519 + MTK_FUNCTION(1, "BPI_BUS6")
12520 + ),
12521 + MTK_PIN(
12522 + 71, "GPIO71",
12523 + MTK_EINT_FUNCTION(0, 71),
12524 + DRV_GRP4,
12525 + MTK_FUNCTION(0, "GPIO71"),
12526 + MTK_FUNCTION(1, "BPI_BUS5")
12527 + ),
12528 + MTK_PIN(
12529 + 72, "GPIO72",
12530 + MTK_EINT_FUNCTION(0, 72),
12531 + DRV_GRP4,
12532 + MTK_FUNCTION(0, "GPIO72"),
12533 + MTK_FUNCTION(1, "BPI_BUS4")
12534 + ),
12535 + MTK_PIN(
12536 + 73, "GPIO73",
12537 + MTK_EINT_FUNCTION(0, 73),
12538 + DRV_GRP4,
12539 + MTK_FUNCTION(0, "GPIO73"),
12540 + MTK_FUNCTION(1, "BPI_BUS3")
12541 + ),
12542 + MTK_PIN(
12543 + 74, "GPIO74",
12544 + MTK_EINT_FUNCTION(0, 74),
12545 + DRV_GRP4,
12546 + MTK_FUNCTION(0, "GPIO74"),
12547 + MTK_FUNCTION(1, "BPI_BUS2")
12548 + ),
12549 + MTK_PIN(
12550 + 75, "GPIO75",
12551 + MTK_EINT_FUNCTION(0, 75),
12552 + DRV_GRP4,
12553 + MTK_FUNCTION(0, "GPIO75"),
12554 + MTK_FUNCTION(1, "BPI_BUS1")
12555 + ),
12556 + MTK_PIN(
12557 + 76, "GPIO76",
12558 + MTK_EINT_FUNCTION(0, 76),
12559 + DRV_GRP4,
12560 + MTK_FUNCTION(0, "GPIO76"),
12561 + MTK_FUNCTION(1, "BPI_BUS0")
12562 + ),
12563 + MTK_PIN(
12564 + 77, "GPIO77",
12565 + MTK_EINT_FUNCTION(0, 77),
12566 + DRV_GRP4,
12567 + MTK_FUNCTION(0, "GPIO77"),
12568 + MTK_FUNCTION(1, "BPI_ANT1")
12569 + ),
12570 + MTK_PIN(
12571 + 78, "GPIO78",
12572 + MTK_EINT_FUNCTION(0, 78),
12573 + DRV_GRP4,
12574 + MTK_FUNCTION(0, "GPIO78"),
12575 + MTK_FUNCTION(1, "BPI_OLAT0")
12576 + ),
12577 + MTK_PIN(
12578 + 79, "GPIO79",
12579 + MTK_EINT_FUNCTION(0, 79),
12580 + DRV_GRP4,
12581 + MTK_FUNCTION(0, "GPIO79"),
12582 + MTK_FUNCTION(1, "BPI_PA_VM1"),
12583 + MTK_FUNCTION(2, "MIPI4_SDATA")
12584 + ),
12585 + MTK_PIN(
12586 + 80, "GPIO80",
12587 + MTK_EINT_FUNCTION(0, 80),
12588 + DRV_GRP4,
12589 + MTK_FUNCTION(0, "GPIO80"),
12590 + MTK_FUNCTION(1, "BPI_PA_VM0"),
12591 + MTK_FUNCTION(2, "MIPI4_SCLK")
12592 + ),
12593 + MTK_PIN(
12594 + 81, "GPIO81",
12595 + MTK_EINT_FUNCTION(0, 81),
12596 + DRV_GRP4,
12597 + MTK_FUNCTION(0, "GPIO81"),
12598 + MTK_FUNCTION(1, "SDA1")
12599 + ),
12600 + MTK_PIN(
12601 + 82, "GPIO82",
12602 + MTK_EINT_FUNCTION(0, 82),
12603 + DRV_GRP4,
12604 + MTK_FUNCTION(0, "GPIO82"),
12605 + MTK_FUNCTION(1, "SDA0")
12606 + ),
12607 + MTK_PIN(
12608 + 83, "GPIO83",
12609 + MTK_EINT_FUNCTION(0, 83),
12610 + DRV_GRP4,
12611 + MTK_FUNCTION(0, "GPIO83"),
12612 + MTK_FUNCTION(1, "SCL0")
12613 + ),
12614 + MTK_PIN(
12615 + 84, "GPIO84",
12616 + MTK_EINT_FUNCTION(0, 84),
12617 + DRV_GRP4,
12618 + MTK_FUNCTION(0, "GPIO84"),
12619 + MTK_FUNCTION(1, "SCL1")
12620 + ),
12621 + MTK_PIN(
12622 + 85, "GPIO85",
12623 + MTK_EINT_FUNCTION(0, 85),
12624 + DRV_GRP4,
12625 + MTK_FUNCTION(0, "GPIO85"),
12626 + MTK_FUNCTION(1, "SPI0_MI"),
12627 + MTK_FUNCTION(2, "SCP_SPI0_MI"),
12628 + MTK_FUNCTION(3, "CLKM3"),
12629 + MTK_FUNCTION(4, "I2S1_BCK"),
12630 + MTK_FUNCTION(5, "MFG_DFD_JTAG_TDO"),
12631 + MTK_FUNCTION(6, "DFD_TDO"),
12632 + MTK_FUNCTION(7, "JTDO_SEL1")
12633 + ),
12634 + MTK_PIN(
12635 + 86, "GPIO86",
12636 + MTK_EINT_FUNCTION(0, 86),
12637 + DRV_GRP4,
12638 + MTK_FUNCTION(0, "GPIO86"),
12639 + MTK_FUNCTION(1, "SPI0_CSB"),
12640 + MTK_FUNCTION(2, "SCP_SPI0_CS"),
12641 + MTK_FUNCTION(3, "CLKM0"),
12642 + MTK_FUNCTION(4, "I2S1_LRCK"),
12643 + MTK_FUNCTION(5, "MFG_DFD_JTAG_TMS"),
12644 + MTK_FUNCTION(6, "DFD_TMS"),
12645 + MTK_FUNCTION(7, "JTMS_SEL1")
12646 + ),
12647 + MTK_PIN(
12648 + 87, "GPIO87",
12649 + MTK_EINT_FUNCTION(0, 87),
12650 + DRV_GRP4,
12651 + MTK_FUNCTION(0, "GPIO87"),
12652 + MTK_FUNCTION(1, "SPI0_MO"),
12653 + MTK_FUNCTION(2, "SCP_SPI0_MO"),
12654 + MTK_FUNCTION(3, "SDA1"),
12655 + MTK_FUNCTION(4, "I2S1_DO"),
12656 + MTK_FUNCTION(5, "MFG_DFD_JTAG_TDI"),
12657 + MTK_FUNCTION(6, "DFD_TDI"),
12658 + MTK_FUNCTION(7, "JTDI_SEL1")
12659 + ),
12660 + MTK_PIN(
12661 + 88, "GPIO88",
12662 + MTK_EINT_FUNCTION(0, 88),
12663 + DRV_GRP4,
12664 + MTK_FUNCTION(0, "GPIO88"),
12665 + MTK_FUNCTION(1, "SPI0_CLK"),
12666 + MTK_FUNCTION(2, "SCP_SPI0_CK"),
12667 + MTK_FUNCTION(3, "SCL1"),
12668 + MTK_FUNCTION(4, "I2S1_MCK"),
12669 + MTK_FUNCTION(5, "MFG_DFD_JTAG_TCK"),
12670 + MTK_FUNCTION(6, "DFD_TCK_XI"),
12671 + MTK_FUNCTION(7, "JTCK_SEL1")
12672 + ),
12673 + MTK_PIN(
12674 + 89, "GPIO89",
12675 + MTK_EINT_FUNCTION(0, 89),
12676 + DRV_GRP4,
12677 + MTK_FUNCTION(0, "GPIO89"),
12678 + MTK_FUNCTION(1, "SRCLKENAI0"),
12679 + MTK_FUNCTION(2, "PWM_C"),
12680 + MTK_FUNCTION(3, "I2S5_BCK"),
12681 + MTK_FUNCTION(4, "ANT_SEL6"),
12682 + MTK_FUNCTION(5, "SDA8"),
12683 + MTK_FUNCTION(6, "CMVREF0"),
12684 + MTK_FUNCTION(7, "DBG_MON_A21")
12685 + ),
12686 + MTK_PIN(
12687 + 90, "GPIO90",
12688 + MTK_EINT_FUNCTION(0, 90),
12689 + DRV_GRP4,
12690 + MTK_FUNCTION(0, "GPIO90"),
12691 + MTK_FUNCTION(1, "PWM_A"),
12692 + MTK_FUNCTION(2, "CMMCLK2"),
12693 + MTK_FUNCTION(3, "I2S5_LRCK"),
12694 + MTK_FUNCTION(4, "SCP_VREQ_VAO"),
12695 + MTK_FUNCTION(5, "SCL8"),
12696 + MTK_FUNCTION(6, "PTA_RXD"),
12697 + MTK_FUNCTION(7, "DBG_MON_A22")
12698 + ),
12699 + MTK_PIN(
12700 + 91, "GPIO91",
12701 + MTK_EINT_FUNCTION(0, 91),
12702 + DRV_GRP4,
12703 + MTK_FUNCTION(0, "GPIO91"),
12704 + MTK_FUNCTION(1, "KPROW1"),
12705 + MTK_FUNCTION(2, "PWM_B"),
12706 + MTK_FUNCTION(3, "I2S5_DO"),
12707 + MTK_FUNCTION(4, "ANT_SEL7"),
12708 + MTK_FUNCTION(5, "CMMCLK3"),
12709 + MTK_FUNCTION(6, "PTA_TXD")
12710 + ),
12711 + MTK_PIN(
12712 + 92, "GPIO92",
12713 + MTK_EINT_FUNCTION(0, 92),
12714 + DRV_GRP4,
12715 + MTK_FUNCTION(0, "GPIO92"),
12716 + MTK_FUNCTION(1, "KPROW0")
12717 + ),
12718 + MTK_PIN(
12719 + 93, "GPIO93",
12720 + MTK_EINT_FUNCTION(0, 93),
12721 + DRV_GRP4,
12722 + MTK_FUNCTION(0, "GPIO93"),
12723 + MTK_FUNCTION(1, "KPCOL0"),
12724 + MTK_FUNCTION(7, "DBG_MON_B27")
12725 + ),
12726 + MTK_PIN(
12727 + 94, "GPIO94",
12728 + MTK_EINT_FUNCTION(0, 94),
12729 + DRV_GRP4,
12730 + MTK_FUNCTION(0, "GPIO94"),
12731 + MTK_FUNCTION(1, "KPCOL1"),
12732 + MTK_FUNCTION(2, "I2S2_DI2"),
12733 + MTK_FUNCTION(3, "I2S5_MCK"),
12734 + MTK_FUNCTION(4, "CMMCLK2"),
12735 + MTK_FUNCTION(5, "SCP_SPI2_MI"),
12736 + MTK_FUNCTION(6, "SRCLKENAI1"),
12737 + MTK_FUNCTION(7, "SPI2_MI")
12738 + ),
12739 + MTK_PIN(
12740 + 95, "GPIO95",
12741 + MTK_EINT_FUNCTION(0, 95),
12742 + DRV_GRP4,
12743 + MTK_FUNCTION(0, "GPIO95"),
12744 + MTK_FUNCTION(1, "URXD0"),
12745 + MTK_FUNCTION(2, "UTXD0"),
12746 + MTK_FUNCTION(3, "MD_URXD0"),
12747 + MTK_FUNCTION(4, "MD_URXD1"),
12748 + MTK_FUNCTION(5, "SSPM_URXD_AO"),
12749 + MTK_FUNCTION(6, "CCU_URXD_AO")
12750 + ),
12751 + MTK_PIN(
12752 + 96, "GPIO96",
12753 + MTK_EINT_FUNCTION(0, 96),
12754 + DRV_GRP4,
12755 + MTK_FUNCTION(0, "GPIO96"),
12756 + MTK_FUNCTION(1, "UTXD0"),
12757 + MTK_FUNCTION(2, "URXD0"),
12758 + MTK_FUNCTION(3, "MD_UTXD0"),
12759 + MTK_FUNCTION(4, "MD_UTXD1"),
12760 + MTK_FUNCTION(5, "SSPM_UTXD_AO"),
12761 + MTK_FUNCTION(6, "CCU_UTXD_AO"),
12762 + MTK_FUNCTION(7, "DBG_MON_B2")
12763 + ),
12764 + MTK_PIN(
12765 + 97, "GPIO97",
12766 + MTK_EINT_FUNCTION(0, 97),
12767 + DRV_GRP4,
12768 + MTK_FUNCTION(0, "GPIO97"),
12769 + MTK_FUNCTION(1, "UCTS0"),
12770 + MTK_FUNCTION(2, "I2S2_MCK"),
12771 + MTK_FUNCTION(3, "IDDIG"),
12772 + MTK_FUNCTION(4, "CONN_MCU_TDO"),
12773 + MTK_FUNCTION(5, "SSPM_JTAG_TDO"),
12774 + MTK_FUNCTION(6, "IO_JTAG_TDO"),
12775 + MTK_FUNCTION(7, "DBG_MON_B3")
12776 + ),
12777 + MTK_PIN(
12778 + 98, "GPIO98",
12779 + MTK_EINT_FUNCTION(0, 98),
12780 + DRV_GRP4,
12781 + MTK_FUNCTION(0, "GPIO98"),
12782 + MTK_FUNCTION(1, "URTS0"),
12783 + MTK_FUNCTION(2, "I2S2_BCK"),
12784 + MTK_FUNCTION(3, "USB_DRVVBUS"),
12785 + MTK_FUNCTION(4, "CONN_MCU_TMS"),
12786 + MTK_FUNCTION(5, "SSPM_JTAG_TMS"),
12787 + MTK_FUNCTION(6, "IO_JTAG_TMS"),
12788 + MTK_FUNCTION(7, "DBG_MON_B4")
12789 + ),
12790 + MTK_PIN(
12791 + 99, "GPIO99",
12792 + MTK_EINT_FUNCTION(0, 99),
12793 + DRV_GRP4,
12794 + MTK_FUNCTION(0, "GPIO99"),
12795 + MTK_FUNCTION(1, "CMMCLK0"),
12796 + MTK_FUNCTION(4, "CONN_MCU_AICE_TMSC"),
12797 + MTK_FUNCTION(7, "DBG_MON_B28")
12798 + ),
12799 + MTK_PIN(
12800 + 100, "GPIO100",
12801 + MTK_EINT_FUNCTION(0, 100),
12802 + DRV_GRP4,
12803 + MTK_FUNCTION(0, "GPIO100"),
12804 + MTK_FUNCTION(1, "CMMCLK1"),
12805 + MTK_FUNCTION(2, "PWM_C"),
12806 + MTK_FUNCTION(3, "MD_INT1_C2K_UIM0_HOT_PLUG"),
12807 + MTK_FUNCTION(4, "CONN_MCU_AICE_TCKC"),
12808 + MTK_FUNCTION(7, "DBG_MON_B29")
12809 + ),
12810 + MTK_PIN(
12811 + 101, "GPIO101",
12812 + MTK_EINT_FUNCTION(0, 101),
12813 + DRV_GRP4,
12814 + MTK_FUNCTION(0, "GPIO101"),
12815 + MTK_FUNCTION(1, "CLKM2"),
12816 + MTK_FUNCTION(2, "I2S2_LRCK"),
12817 + MTK_FUNCTION(3, "CMVREF1"),
12818 + MTK_FUNCTION(4, "CONN_MCU_TCK"),
12819 + MTK_FUNCTION(5, "SSPM_JTAG_TCK"),
12820 + MTK_FUNCTION(6, "IO_JTAG_TCK")
12821 + ),
12822 + MTK_PIN(
12823 + 102, "GPIO102",
12824 + MTK_EINT_FUNCTION(0, 102),
12825 + DRV_GRP4,
12826 + MTK_FUNCTION(0, "GPIO102"),
12827 + MTK_FUNCTION(1, "CLKM1"),
12828 + MTK_FUNCTION(2, "I2S2_DI"),
12829 + MTK_FUNCTION(3, "DVFSRC_EXT_REQ"),
12830 + MTK_FUNCTION(4, "CONN_MCU_TDI"),
12831 + MTK_FUNCTION(5, "SSPM_JTAG_TDI"),
12832 + MTK_FUNCTION(6, "IO_JTAG_TDI"),
12833 + MTK_FUNCTION(7, "DBG_MON_B8")
12834 + ),
12835 + MTK_PIN(
12836 + 103, "GPIO103",
12837 + MTK_EINT_FUNCTION(0, 103),
12838 + DRV_GRP4,
12839 + MTK_FUNCTION(0, "GPIO103"),
12840 + MTK_FUNCTION(1, "SCL2")
12841 + ),
12842 + MTK_PIN(
12843 + 104, "GPIO104",
12844 + MTK_EINT_FUNCTION(0, 104),
12845 + DRV_GRP4,
12846 + MTK_FUNCTION(0, "GPIO104"),
12847 + MTK_FUNCTION(1, "SDA2")
12848 + ),
12849 + MTK_PIN(
12850 + 105, "GPIO105",
12851 + MTK_EINT_FUNCTION(0, 105),
12852 + DRV_GRP4,
12853 + MTK_FUNCTION(0, "GPIO105"),
12854 + MTK_FUNCTION(1, "SCL4")
12855 + ),
12856 + MTK_PIN(
12857 + 106, "GPIO106",
12858 + MTK_EINT_FUNCTION(0, 106),
12859 + DRV_GRP4,
12860 + MTK_FUNCTION(0, "GPIO106"),
12861 + MTK_FUNCTION(1, "SDA4")
12862 + ),
12863 + MTK_PIN(
12864 + 107, "GPIO107",
12865 + MTK_EINT_FUNCTION(0, 107),
12866 + DRV_GRP4,
12867 + MTK_FUNCTION(0, "GPIO107"),
12868 + MTK_FUNCTION(1, "DMIC_CLK"),
12869 + MTK_FUNCTION(2, "ANT_SEL0"),
12870 + MTK_FUNCTION(3, "CLKM0"),
12871 + MTK_FUNCTION(4, "SDA7"),
12872 + MTK_FUNCTION(5, "EXT_FRAME_SYNC"),
12873 + MTK_FUNCTION(6, "PWM_A"),
12874 + MTK_FUNCTION(7, "DBG_MON_B12")
12875 + ),
12876 + MTK_PIN(
12877 + 108, "GPIO108",
12878 + MTK_EINT_FUNCTION(0, 108),
12879 + DRV_GRP4,
12880 + MTK_FUNCTION(0, "GPIO108"),
12881 + MTK_FUNCTION(1, "CMMCLK2"),
12882 + MTK_FUNCTION(2, "ANT_SEL1"),
12883 + MTK_FUNCTION(3, "CLKM1"),
12884 + MTK_FUNCTION(4, "SCL8"),
12885 + MTK_FUNCTION(5, "DAP_MD32_SWD"),
12886 + MTK_FUNCTION(6, "PWM_B"),
12887 + MTK_FUNCTION(7, "DBG_MON_B13")
12888 + ),
12889 + MTK_PIN(
12890 + 109, "GPIO109",
12891 + MTK_EINT_FUNCTION(0, 109),
12892 + DRV_GRP4,
12893 + MTK_FUNCTION(0, "GPIO109"),
12894 + MTK_FUNCTION(1, "DMIC_DAT"),
12895 + MTK_FUNCTION(2, "ANT_SEL2"),
12896 + MTK_FUNCTION(3, "CLKM2"),
12897 + MTK_FUNCTION(4, "SDA8"),
12898 + MTK_FUNCTION(5, "DAP_MD32_SWCK"),
12899 + MTK_FUNCTION(6, "PWM_C"),
12900 + MTK_FUNCTION(7, "DBG_MON_B14")
12901 + ),
12902 + MTK_PIN(
12903 + 110, "GPIO110",
12904 + MTK_EINT_FUNCTION(0, 110),
12905 + DRV_GRP4,
12906 + MTK_FUNCTION(0, "GPIO110"),
12907 + MTK_FUNCTION(1, "SCL7"),
12908 + MTK_FUNCTION(2, "ANT_SEL0"),
12909 + MTK_FUNCTION(3, "TP_URXD1_AO"),
12910 + MTK_FUNCTION(4, "USB_DRVVBUS"),
12911 + MTK_FUNCTION(5, "SRCLKENAI1"),
12912 + MTK_FUNCTION(6, "KPCOL2"),
12913 + MTK_FUNCTION(7, "URXD1")
12914 + ),
12915 + MTK_PIN(
12916 + 111, "GPIO111",
12917 + MTK_EINT_FUNCTION(0, 111),
12918 + DRV_GRP4,
12919 + MTK_FUNCTION(0, "GPIO111"),
12920 + MTK_FUNCTION(1, "CMMCLK3"),
12921 + MTK_FUNCTION(2, "ANT_SEL1"),
12922 + MTK_FUNCTION(3, "SRCLKENAI0"),
12923 + MTK_FUNCTION(4, "SCP_VREQ_VAO"),
12924 + MTK_FUNCTION(5, "MD_INT2_C2K_UIM1_HOT_PLUG"),
12925 + MTK_FUNCTION(7, "DVFSRC_EXT_REQ")
12926 + ),
12927 + MTK_PIN(
12928 + 112, "GPIO112",
12929 + MTK_EINT_FUNCTION(0, 112),
12930 + DRV_GRP4,
12931 + MTK_FUNCTION(0, "GPIO112"),
12932 + MTK_FUNCTION(1, "SDA7"),
12933 + MTK_FUNCTION(2, "ANT_SEL2"),
12934 + MTK_FUNCTION(3, "TP_UTXD1_AO"),
12935 + MTK_FUNCTION(4, "IDDIG"),
12936 + MTK_FUNCTION(5, "AGPS_SYNC"),
12937 + MTK_FUNCTION(6, "KPROW2"),
12938 + MTK_FUNCTION(7, "UTXD1")
12939 + ),
12940 + MTK_PIN(
12941 + 113, "GPIO113",
12942 + MTK_EINT_FUNCTION(0, 113),
12943 + DRV_GRP4,
12944 + MTK_FUNCTION(0, "GPIO113"),
12945 + MTK_FUNCTION(1, "CONN_TOP_CLK"),
12946 + MTK_FUNCTION(3, "SCL6"),
12947 + MTK_FUNCTION(4, "AUXIF_CLK0"),
12948 + MTK_FUNCTION(6, "TP_UCTS1_AO")
12949 + ),
12950 + MTK_PIN(
12951 + 114, "GPIO114",
12952 + MTK_EINT_FUNCTION(0, 114),
12953 + DRV_GRP4,
12954 + MTK_FUNCTION(0, "GPIO114"),
12955 + MTK_FUNCTION(1, "CONN_TOP_DATA"),
12956 + MTK_FUNCTION(3, "SDA6"),
12957 + MTK_FUNCTION(4, "AUXIF_ST0"),
12958 + MTK_FUNCTION(6, "TP_URTS1_AO")
12959 + ),
12960 + MTK_PIN(
12961 + 115, "GPIO115",
12962 + MTK_EINT_FUNCTION(0, 115),
12963 + DRV_GRP4,
12964 + MTK_FUNCTION(0, "GPIO115"),
12965 + MTK_FUNCTION(1, "CONN_BT_CLK"),
12966 + MTK_FUNCTION(2, "UTXD1"),
12967 + MTK_FUNCTION(3, "PTA_TXD"),
12968 + MTK_FUNCTION(4, "AUXIF_CLK1"),
12969 + MTK_FUNCTION(5, "DAP_MD32_SWD"),
12970 + MTK_FUNCTION(6, "TP_UTXD1_AO")
12971 + ),
12972 + MTK_PIN(
12973 + 116, "GPIO116",
12974 + MTK_EINT_FUNCTION(0, 116),
12975 + DRV_GRP4,
12976 + MTK_FUNCTION(0, "GPIO116"),
12977 + MTK_FUNCTION(1, "CONN_BT_DATA"),
12978 + MTK_FUNCTION(2, "IPU_JTAG_TRST"),
12979 + MTK_FUNCTION(4, "AUXIF_ST1"),
12980 + MTK_FUNCTION(5, "DAP_MD32_SWCK"),
12981 + MTK_FUNCTION(6, "TP_URXD2_AO"),
12982 + MTK_FUNCTION(7, "DBG_MON_A0")
12983 + ),
12984 + MTK_PIN(
12985 + 117, "GPIO117",
12986 + MTK_EINT_FUNCTION(0, 117),
12987 + DRV_GRP4,
12988 + MTK_FUNCTION(0, "GPIO117"),
12989 + MTK_FUNCTION(1, "CONN_WF_HB0"),
12990 + MTK_FUNCTION(2, "IPU_JTAG_TDO"),
12991 + MTK_FUNCTION(6, "TP_UTXD2_AO"),
12992 + MTK_FUNCTION(7, "DBG_MON_A4")
12993 + ),
12994 + MTK_PIN(
12995 + 118, "GPIO118",
12996 + MTK_EINT_FUNCTION(0, 118),
12997 + DRV_GRP4,
12998 + MTK_FUNCTION(0, "GPIO118"),
12999 + MTK_FUNCTION(1, "CONN_WF_HB1"),
13000 + MTK_FUNCTION(2, "IPU_JTAG_TDI"),
13001 + MTK_FUNCTION(5, "SSPM_URXD_AO"),
13002 + MTK_FUNCTION(6, "TP_UCTS2_AO"),
13003 + MTK_FUNCTION(7, "DBG_MON_A5")
13004 + ),
13005 + MTK_PIN(
13006 + 119, "GPIO119",
13007 + MTK_EINT_FUNCTION(0, 119),
13008 + DRV_GRP4,
13009 + MTK_FUNCTION(0, "GPIO119"),
13010 + MTK_FUNCTION(1, "CONN_WF_HB2"),
13011 + MTK_FUNCTION(2, "IPU_JTAG_TCK"),
13012 + MTK_FUNCTION(5, "SSPM_UTXD_AO"),
13013 + MTK_FUNCTION(6, "TP_URTS2_AO")
13014 + ),
13015 + MTK_PIN(
13016 + 120, "GPIO120",
13017 + MTK_EINT_FUNCTION(0, 120),
13018 + DRV_GRP4,
13019 + MTK_FUNCTION(0, "GPIO120"),
13020 + MTK_FUNCTION(1, "CONN_WB_PTA"),
13021 + MTK_FUNCTION(2, "IPU_JTAG_TMS"),
13022 + MTK_FUNCTION(5, "CCU_URXD_AO")
13023 + ),
13024 + MTK_PIN(
13025 + 121, "GPIO121",
13026 + MTK_EINT_FUNCTION(0, 121),
13027 + DRV_GRP4,
13028 + MTK_FUNCTION(0, "GPIO121"),
13029 + MTK_FUNCTION(1, "CONN_HRST_B"),
13030 + MTK_FUNCTION(2, "URXD1"),
13031 + MTK_FUNCTION(3, "PTA_RXD"),
13032 + MTK_FUNCTION(5, "CCU_UTXD_AO"),
13033 + MTK_FUNCTION(6, "TP_URXD1_AO")
13034 + ),
13035 + MTK_PIN(
13036 + 122, "GPIO122",
13037 + MTK_EINT_FUNCTION(0, 122),
13038 + DRV_GRP4,
13039 + MTK_FUNCTION(0, "GPIO122"),
13040 + MTK_FUNCTION(1, "MSDC0_CMD"),
13041 + MTK_FUNCTION(2, "SSPM_URXD2_AO"),
13042 + MTK_FUNCTION(3, "ANT_SEL1"),
13043 + MTK_FUNCTION(7, "DBG_MON_A12")
13044 + ),
13045 + MTK_PIN(
13046 + 123, "GPIO123",
13047 + MTK_EINT_FUNCTION(0, 123),
13048 + DRV_GRP4,
13049 + MTK_FUNCTION(0, "GPIO123"),
13050 + MTK_FUNCTION(1, "MSDC0_DAT0"),
13051 + MTK_FUNCTION(3, "ANT_SEL0"),
13052 + MTK_FUNCTION(7, "DBG_MON_A13")
13053 + ),
13054 + MTK_PIN(
13055 + 124, "GPIO124",
13056 + MTK_EINT_FUNCTION(0, 124),
13057 + DRV_GRP4,
13058 + MTK_FUNCTION(0, "GPIO124"),
13059 + MTK_FUNCTION(1, "MSDC0_CLK"),
13060 + MTK_FUNCTION(7, "DBG_MON_A14")
13061 + ),
13062 + MTK_PIN(
13063 + 125, "GPIO125",
13064 + MTK_EINT_FUNCTION(0, 125),
13065 + DRV_GRP4,
13066 + MTK_FUNCTION(0, "GPIO125"),
13067 + MTK_FUNCTION(1, "MSDC0_DAT2"),
13068 + MTK_FUNCTION(3, "MRG_CLK"),
13069 + MTK_FUNCTION(7, "DBG_MON_A15")
13070 + ),
13071 + MTK_PIN(
13072 + 126, "GPIO126",
13073 + MTK_EINT_FUNCTION(0, 126),
13074 + DRV_GRP4,
13075 + MTK_FUNCTION(0, "GPIO126"),
13076 + MTK_FUNCTION(1, "MSDC0_DAT4"),
13077 + MTK_FUNCTION(3, "ANT_SEL5"),
13078 + MTK_FUNCTION(6, "UFS_MPHY_SCL"),
13079 + MTK_FUNCTION(7, "DBG_MON_A16")
13080 + ),
13081 + MTK_PIN(
13082 + 127, "GPIO127",
13083 + MTK_EINT_FUNCTION(0, 127),
13084 + DRV_GRP4,
13085 + MTK_FUNCTION(0, "GPIO127"),
13086 + MTK_FUNCTION(1, "MSDC0_DAT6"),
13087 + MTK_FUNCTION(3, "ANT_SEL4"),
13088 + MTK_FUNCTION(6, "UFS_MPHY_SDA"),
13089 + MTK_FUNCTION(7, "DBG_MON_A17")
13090 + ),
13091 + MTK_PIN(
13092 + 128, "GPIO128",
13093 + MTK_EINT_FUNCTION(0, 128),
13094 + DRV_GRP4,
13095 + MTK_FUNCTION(0, "GPIO128"),
13096 + MTK_FUNCTION(1, "MSDC0_DAT1"),
13097 + MTK_FUNCTION(3, "ANT_SEL2"),
13098 + MTK_FUNCTION(6, "UFS_UNIPRO_SDA"),
13099 + MTK_FUNCTION(7, "DBG_MON_A18")
13100 + ),
13101 + MTK_PIN(
13102 + 129, "GPIO129",
13103 + MTK_EINT_FUNCTION(0, 129),
13104 + DRV_GRP4,
13105 + MTK_FUNCTION(0, "GPIO129"),
13106 + MTK_FUNCTION(1, "MSDC0_DAT5"),
13107 + MTK_FUNCTION(3, "ANT_SEL3"),
13108 + MTK_FUNCTION(6, "UFS_UNIPRO_SCL"),
13109 + MTK_FUNCTION(7, "DBG_MON_A23")
13110 + ),
13111 + MTK_PIN(
13112 + 130, "GPIO130",
13113 + MTK_EINT_FUNCTION(0, 130),
13114 + DRV_GRP4,
13115 + MTK_FUNCTION(0, "GPIO130"),
13116 + MTK_FUNCTION(1, "MSDC0_DAT7"),
13117 + MTK_FUNCTION(3, "MRG_DO"),
13118 + MTK_FUNCTION(7, "DBG_MON_A24")
13119 + ),
13120 + MTK_PIN(
13121 + 131, "GPIO131",
13122 + MTK_EINT_FUNCTION(0, 131),
13123 + DRV_GRP4,
13124 + MTK_FUNCTION(0, "GPIO131"),
13125 + MTK_FUNCTION(1, "MSDC0_DSL"),
13126 + MTK_FUNCTION(3, "MRG_SYNC"),
13127 + MTK_FUNCTION(7, "DBG_MON_A25")
13128 + ),
13129 + MTK_PIN(
13130 + 132, "GPIO132",
13131 + MTK_EINT_FUNCTION(0, 132),
13132 + DRV_GRP4,
13133 + MTK_FUNCTION(0, "GPIO132"),
13134 + MTK_FUNCTION(1, "MSDC0_DAT3"),
13135 + MTK_FUNCTION(3, "MRG_DI"),
13136 + MTK_FUNCTION(7, "DBG_MON_A26")
13137 + ),
13138 + MTK_PIN(
13139 + 133, "GPIO133",
13140 + MTK_EINT_FUNCTION(0, 133),
13141 + DRV_GRP4,
13142 + MTK_FUNCTION(0, "GPIO133"),
13143 + MTK_FUNCTION(1, "MSDC0_RSTB"),
13144 + MTK_FUNCTION(3, "AGPS_SYNC"),
13145 + MTK_FUNCTION(7, "DBG_MON_A27")
13146 + ),
13147 + MTK_PIN(
13148 + 134, "GPIO134",
13149 + MTK_EINT_FUNCTION(0, 134),
13150 + DRV_GRP4,
13151 + MTK_FUNCTION(0, "GPIO134"),
13152 + MTK_FUNCTION(1, "RTC32K_CK")
13153 + ),
13154 + MTK_PIN(
13155 + 135, "GPIO135",
13156 + MTK_EINT_FUNCTION(0, 135),
13157 + DRV_GRP4,
13158 + MTK_FUNCTION(0, "GPIO135"),
13159 + MTK_FUNCTION(1, "WATCHDOG")
13160 + ),
13161 + MTK_PIN(
13162 + 136, "GPIO136",
13163 + MTK_EINT_FUNCTION(0, 136),
13164 + DRV_GRP4,
13165 + MTK_FUNCTION(0, "GPIO136"),
13166 + MTK_FUNCTION(1, "AUD_CLK_MOSI"),
13167 + MTK_FUNCTION(2, "AUD_CLK_MISO"),
13168 + MTK_FUNCTION(3, "I2S1_MCK"),
13169 + MTK_FUNCTION(6, "UFS_UNIPRO_SCL")
13170 + ),
13171 + MTK_PIN(
13172 + 137, "GPIO137",
13173 + MTK_EINT_FUNCTION(0, 137),
13174 + DRV_GRP4,
13175 + MTK_FUNCTION(0, "GPIO137"),
13176 + MTK_FUNCTION(1, "AUD_SYNC_MOSI"),
13177 + MTK_FUNCTION(2, "AUD_SYNC_MISO"),
13178 + MTK_FUNCTION(3, "I2S1_BCK")
13179 + ),
13180 + MTK_PIN(
13181 + 138, "GPIO138",
13182 + MTK_EINT_FUNCTION(0, 138),
13183 + DRV_GRP4,
13184 + MTK_FUNCTION(0, "GPIO138"),
13185 + MTK_FUNCTION(1, "AUD_DAT_MOSI0"),
13186 + MTK_FUNCTION(2, "AUD_DAT_MISO0"),
13187 + MTK_FUNCTION(3, "I2S1_LRCK"),
13188 + MTK_FUNCTION(7, "DBG_MON_B24")
13189 + ),
13190 + MTK_PIN(
13191 + 139, "GPIO139",
13192 + MTK_EINT_FUNCTION(0, 139),
13193 + DRV_GRP4,
13194 + MTK_FUNCTION(0, "GPIO139"),
13195 + MTK_FUNCTION(1, "AUD_DAT_MOSI1"),
13196 + MTK_FUNCTION(2, "AUD_DAT_MISO1"),
13197 + MTK_FUNCTION(3, "I2S1_DO"),
13198 + MTK_FUNCTION(6, "UFS_MPHY_SDA")
13199 + ),
13200 + MTK_PIN(
13201 + 140, "GPIO140",
13202 + MTK_EINT_FUNCTION(0, 140),
13203 + DRV_GRP4,
13204 + MTK_FUNCTION(0, "GPIO140"),
13205 + MTK_FUNCTION(1, "AUD_CLK_MISO"),
13206 + MTK_FUNCTION(2, "AUD_CLK_MOSI"),
13207 + MTK_FUNCTION(3, "I2S0_MCK"),
13208 + MTK_FUNCTION(6, "UFS_UNIPRO_SDA")
13209 + ),
13210 + MTK_PIN(
13211 + 141, "GPIO141",
13212 + MTK_EINT_FUNCTION(0, 141),
13213 + DRV_GRP4,
13214 + MTK_FUNCTION(0, "GPIO141"),
13215 + MTK_FUNCTION(1, "AUD_SYNC_MISO"),
13216 + MTK_FUNCTION(2, "AUD_SYNC_MOSI"),
13217 + MTK_FUNCTION(3, "I2S0_BCK")
13218 + ),
13219 + MTK_PIN(
13220 + 142, "GPIO142",
13221 + MTK_EINT_FUNCTION(0, 142),
13222 + DRV_GRP4,
13223 + MTK_FUNCTION(0, "GPIO142"),
13224 + MTK_FUNCTION(1, "AUD_DAT_MISO0"),
13225 + MTK_FUNCTION(2, "AUD_DAT_MOSI0"),
13226 + MTK_FUNCTION(3, "I2S0_LRCK"),
13227 + MTK_FUNCTION(4, "VOW_DAT_MISO"),
13228 + MTK_FUNCTION(7, "DBG_MON_B25")
13229 + ),
13230 + MTK_PIN(
13231 + 143, "GPIO143",
13232 + MTK_EINT_FUNCTION(0, 143),
13233 + DRV_GRP4,
13234 + MTK_FUNCTION(0, "GPIO143"),
13235 + MTK_FUNCTION(1, "AUD_DAT_MISO1"),
13236 + MTK_FUNCTION(2, "AUD_DAT_MOSI1"),
13237 + MTK_FUNCTION(3, "I2S0_DI"),
13238 + MTK_FUNCTION(4, "VOW_CLK_MISO"),
13239 + MTK_FUNCTION(6, "UFS_MPHY_SCL"),
13240 + MTK_FUNCTION(7, "DBG_MON_B26")
13241 + ),
13242 + MTK_PIN(
13243 + 144, "GPIO144",
13244 + MTK_EINT_FUNCTION(0, 144),
13245 + DRV_GRP4,
13246 + MTK_FUNCTION(0, "GPIO144"),
13247 + MTK_FUNCTION(1, "PWRAP_SPI0_MI"),
13248 + MTK_FUNCTION(2, "PWRAP_SPI0_MO")
13249 + ),
13250 + MTK_PIN(
13251 + 145, "GPIO145",
13252 + MTK_EINT_FUNCTION(0, 145),
13253 + DRV_GRP4,
13254 + MTK_FUNCTION(0, "GPIO145"),
13255 + MTK_FUNCTION(1, "PWRAP_SPI0_CSN")
13256 + ),
13257 + MTK_PIN(
13258 + 146, "GPIO146",
13259 + MTK_EINT_FUNCTION(0, 146),
13260 + DRV_GRP4,
13261 + MTK_FUNCTION(0, "GPIO146"),
13262 + MTK_FUNCTION(1, "PWRAP_SPI0_MO"),
13263 + MTK_FUNCTION(2, "PWRAP_SPI0_MI")
13264 + ),
13265 + MTK_PIN(
13266 + 147, "GPIO147",
13267 + MTK_EINT_FUNCTION(0, 147),
13268 + DRV_GRP4,
13269 + MTK_FUNCTION(0, "GPIO147"),
13270 + MTK_FUNCTION(1, "PWRAP_SPI0_CK")
13271 + ),
13272 + MTK_PIN(
13273 + 148, "GPIO148",
13274 + MTK_EINT_FUNCTION(0, 148),
13275 + DRV_GRP4,
13276 + MTK_FUNCTION(0, "GPIO148"),
13277 + MTK_FUNCTION(1, "SRCLKENA0")
13278 + ),
13279 + MTK_PIN(
13280 + 149, "GPIO149",
13281 + MTK_EINT_FUNCTION(0, 149),
13282 + DRV_GRP4,
13283 + MTK_FUNCTION(0, "GPIO149"),
13284 + MTK_FUNCTION(1, "SRCLKENA1")
13285 + ),
13286 + MTK_PIN(
13287 + 150, "GPIO150",
13288 + MTK_EINT_FUNCTION(0, 150),
13289 + DRV_GRP4,
13290 + MTK_FUNCTION(0, "GPIO150"),
13291 + MTK_FUNCTION(1, "PWM_A"),
13292 + MTK_FUNCTION(2, "CMFLASH"),
13293 + MTK_FUNCTION(3, "CLKM0"),
13294 + MTK_FUNCTION(7, "DBG_MON_B30")
13295 + ),
13296 + MTK_PIN(
13297 + 151, "GPIO151",
13298 + MTK_EINT_FUNCTION(0, 151),
13299 + DRV_GRP4,
13300 + MTK_FUNCTION(0, "GPIO151"),
13301 + MTK_FUNCTION(1, "PWM_B"),
13302 + MTK_FUNCTION(2, "CMVREF0"),
13303 + MTK_FUNCTION(3, "CLKM1"),
13304 + MTK_FUNCTION(7, "DBG_MON_B20")
13305 + ),
13306 + MTK_PIN(
13307 + 152, "GPIO152",
13308 + MTK_EINT_FUNCTION(0, 152),
13309 + DRV_GRP4,
13310 + MTK_FUNCTION(0, "GPIO152"),
13311 + MTK_FUNCTION(1, "PWM_C"),
13312 + MTK_FUNCTION(2, "CMFLASH"),
13313 + MTK_FUNCTION(3, "CLKM2"),
13314 + MTK_FUNCTION(7, "DBG_MON_B21")
13315 + ),
13316 + MTK_PIN(
13317 + 153, "GPIO153",
13318 + MTK_EINT_FUNCTION(0, 153),
13319 + DRV_GRP4,
13320 + MTK_FUNCTION(0, "GPIO153"),
13321 + MTK_FUNCTION(1, "PWM_A"),
13322 + MTK_FUNCTION(2, "CMVREF0"),
13323 + MTK_FUNCTION(3, "CLKM3"),
13324 + MTK_FUNCTION(7, "DBG_MON_B22")
13325 + ),
13326 + MTK_PIN(
13327 + 154, "GPIO154",
13328 + MTK_EINT_FUNCTION(0, 154),
13329 + DRV_GRP4,
13330 + MTK_FUNCTION(0, "GPIO154"),
13331 + MTK_FUNCTION(1, "SCP_VREQ_VAO"),
13332 + MTK_FUNCTION(2, "DVFSRC_EXT_REQ"),
13333 + MTK_FUNCTION(7, "DBG_MON_B18")
13334 + ),
13335 + MTK_PIN(
13336 + 155, "GPIO155",
13337 + MTK_EINT_FUNCTION(0, 155),
13338 + DRV_GRP4,
13339 + MTK_FUNCTION(0, "GPIO155"),
13340 + MTK_FUNCTION(1, "ANT_SEL0"),
13341 + MTK_FUNCTION(2, "DVFSRC_EXT_REQ"),
13342 + MTK_FUNCTION(3, "CMVREF1"),
13343 + MTK_FUNCTION(7, "SCP_JTAG_TDI")
13344 + ),
13345 + MTK_PIN(
13346 + 156, "GPIO156",
13347 + MTK_EINT_FUNCTION(0, 156),
13348 + DRV_GRP4,
13349 + MTK_FUNCTION(0, "GPIO156"),
13350 + MTK_FUNCTION(1, "ANT_SEL1"),
13351 + MTK_FUNCTION(2, "SRCLKENAI0"),
13352 + MTK_FUNCTION(3, "SCL6"),
13353 + MTK_FUNCTION(4, "KPCOL2"),
13354 + MTK_FUNCTION(5, "IDDIG"),
13355 + MTK_FUNCTION(7, "SCP_JTAG_TCK")
13356 + ),
13357 + MTK_PIN(
13358 + 157, "GPIO157",
13359 + MTK_EINT_FUNCTION(0, 157),
13360 + DRV_GRP4,
13361 + MTK_FUNCTION(0, "GPIO157"),
13362 + MTK_FUNCTION(1, "ANT_SEL2"),
13363 + MTK_FUNCTION(2, "SRCLKENAI1"),
13364 + MTK_FUNCTION(3, "SDA6"),
13365 + MTK_FUNCTION(4, "KPROW2"),
13366 + MTK_FUNCTION(5, "USB_DRVVBUS"),
13367 + MTK_FUNCTION(7, "SCP_JTAG_TRSTN")
13368 + ),
13369 + MTK_PIN(
13370 + 158, "GPIO158",
13371 + MTK_EINT_FUNCTION(0, 158),
13372 + DRV_GRP4,
13373 + MTK_FUNCTION(0, "GPIO158"),
13374 + MTK_FUNCTION(1, "ANT_SEL3")
13375 + ),
13376 + MTK_PIN(
13377 + 159, "GPIO159",
13378 + MTK_EINT_FUNCTION(0, 159),
13379 + DRV_GRP4,
13380 + MTK_FUNCTION(0, "GPIO159"),
13381 + MTK_FUNCTION(1, "ANT_SEL4")
13382 + ),
13383 + MTK_PIN(
13384 + 160, "GPIO160",
13385 + MTK_EINT_FUNCTION(0, 160),
13386 + DRV_GRP4,
13387 + MTK_FUNCTION(0, "GPIO160"),
13388 + MTK_FUNCTION(1, "ANT_SEL5")
13389 + ),
13390 + MTK_PIN(
13391 + 161, "GPIO161",
13392 + MTK_EINT_FUNCTION(0, 161),
13393 + DRV_GRP4,
13394 + MTK_FUNCTION(0, "GPIO161"),
13395 + MTK_FUNCTION(1, "SPI1_A_MI"),
13396 + MTK_FUNCTION(2, "SCP_SPI1_MI"),
13397 + MTK_FUNCTION(3, "IDDIG"),
13398 + MTK_FUNCTION(4, "ANT_SEL6"),
13399 + MTK_FUNCTION(5, "KPCOL2"),
13400 + MTK_FUNCTION(6, "PTA_RXD"),
13401 + MTK_FUNCTION(7, "DBG_MON_B19")
13402 + ),
13403 + MTK_PIN(
13404 + 162, "GPIO162",
13405 + MTK_EINT_FUNCTION(0, 162),
13406 + DRV_GRP4,
13407 + MTK_FUNCTION(0, "GPIO162"),
13408 + MTK_FUNCTION(1, "SPI1_A_CSB"),
13409 + MTK_FUNCTION(2, "SCP_SPI1_CS"),
13410 + MTK_FUNCTION(3, "USB_DRVVBUS"),
13411 + MTK_FUNCTION(4, "ANT_SEL5"),
13412 + MTK_FUNCTION(5, "KPROW2"),
13413 + MTK_FUNCTION(6, "PTA_TXD")
13414 + ),
13415 + MTK_PIN(
13416 + 163, "GPIO163",
13417 + MTK_EINT_FUNCTION(0, 163),
13418 + DRV_GRP4,
13419 + MTK_FUNCTION(0, "GPIO163"),
13420 + MTK_FUNCTION(1, "SPI1_A_MO"),
13421 + MTK_FUNCTION(2, "SCP_SPI1_MO"),
13422 + MTK_FUNCTION(3, "SDA1"),
13423 + MTK_FUNCTION(4, "ANT_SEL4"),
13424 + MTK_FUNCTION(5, "CMMCLK2"),
13425 + MTK_FUNCTION(6, "DMIC_CLK")
13426 + ),
13427 + MTK_PIN(
13428 + 164, "GPIO164",
13429 + MTK_EINT_FUNCTION(0, 164),
13430 + DRV_GRP4,
13431 + MTK_FUNCTION(0, "GPIO164"),
13432 + MTK_FUNCTION(1, "SPI1_A_CLK"),
13433 + MTK_FUNCTION(2, "SCP_SPI1_CK"),
13434 + MTK_FUNCTION(3, "SCL1"),
13435 + MTK_FUNCTION(4, "ANT_SEL3"),
13436 + MTK_FUNCTION(5, "CMMCLK3"),
13437 + MTK_FUNCTION(6, "DMIC_DAT")
13438 + ),
13439 + MTK_PIN(
13440 + 165, "GPIO165",
13441 + MTK_EINT_FUNCTION(0, 165),
13442 + DRV_GRP4,
13443 + MTK_FUNCTION(0, "GPIO165"),
13444 + MTK_FUNCTION(1, "PWM_B"),
13445 + MTK_FUNCTION(2, "CMMCLK2"),
13446 + MTK_FUNCTION(3, "SCP_VREQ_VAO"),
13447 + MTK_FUNCTION(6, "TDM_MCK_2ND"),
13448 + MTK_FUNCTION(7, "SCP_JTAG_TDO")
13449 + ),
13450 + MTK_PIN(
13451 + 166, "GPIO166",
13452 + MTK_EINT_FUNCTION(0, 166),
13453 + DRV_GRP4,
13454 + MTK_FUNCTION(0, "GPIO166"),
13455 + MTK_FUNCTION(1, "ANT_SEL6")
13456 + ),
13457 + MTK_PIN(
13458 + 167, "GPIO167",
13459 + MTK_EINT_FUNCTION(0, 167),
13460 + DRV_GRP4,
13461 + MTK_FUNCTION(0, "GPIO167"),
13462 + MTK_FUNCTION(1, "RFIC0_BSI_EN"),
13463 + MTK_FUNCTION(2, "SPM_BSI_EN")
13464 + ),
13465 + MTK_PIN(
13466 + 168, "GPIO168",
13467 + MTK_EINT_FUNCTION(0, 168),
13468 + DRV_GRP4,
13469 + MTK_FUNCTION(0, "GPIO168"),
13470 + MTK_FUNCTION(1, "RFIC0_BSI_CK"),
13471 + MTK_FUNCTION(2, "SPM_BSI_CK")
13472 + ),
13473 + MTK_PIN(
13474 + 169, "GPIO169",
13475 + MTK_EINT_FUNCTION(0, 169),
13476 + DRV_GRP4,
13477 + MTK_FUNCTION(0, "GPIO169"),
13478 + MTK_FUNCTION(1, "PWM_C"),
13479 + MTK_FUNCTION(2, "CMMCLK3"),
13480 + MTK_FUNCTION(3, "CMVREF1"),
13481 + MTK_FUNCTION(4, "ANT_SEL7"),
13482 + MTK_FUNCTION(5, "AGPS_SYNC"),
13483 + MTK_FUNCTION(6, "TDM_BCK_2ND"),
13484 + MTK_FUNCTION(7, "SCP_JTAG_TMS")
13485 + ),
13486 + MTK_PIN(
13487 + 170, "GPIO170",
13488 + MTK_EINT_FUNCTION(0, 170),
13489 + DRV_GRP4,
13490 + MTK_FUNCTION(0, "GPIO170"),
13491 + MTK_FUNCTION(1, "I2S1_BCK"),
13492 + MTK_FUNCTION(2, "I2S3_BCK"),
13493 + MTK_FUNCTION(3, "SCL7"),
13494 + MTK_FUNCTION(4, "I2S5_BCK"),
13495 + MTK_FUNCTION(5, "EXT_FRAME_SYNC"),
13496 + MTK_FUNCTION(6, "TDM_LRCK_2ND"),
13497 + MTK_FUNCTION(7, "ANT_SEL3")
13498 + ),
13499 + MTK_PIN(
13500 + 171, "GPIO171",
13501 + MTK_EINT_FUNCTION(0, 184),
13502 + DRV_GRP4,
13503 + MTK_FUNCTION(0, "GPIO171"),
13504 + MTK_FUNCTION(1, "I2S1_LRCK"),
13505 + MTK_FUNCTION(2, "I2S3_LRCK"),
13506 + MTK_FUNCTION(3, "SDA7"),
13507 + MTK_FUNCTION(4, "I2S5_LRCK"),
13508 + MTK_FUNCTION(5, "URXD1"),
13509 + MTK_FUNCTION(6, "TDM_DATA0_2ND"),
13510 + MTK_FUNCTION(7, "ANT_SEL4")
13511 + ),
13512 + MTK_PIN(
13513 + 172, "GPIO172",
13514 + MTK_EINT_FUNCTION(0, 185),
13515 + DRV_GRP4,
13516 + MTK_FUNCTION(0, "GPIO172"),
13517 + MTK_FUNCTION(1, "I2S1_DO"),
13518 + MTK_FUNCTION(2, "I2S3_DO"),
13519 + MTK_FUNCTION(3, "SCL8"),
13520 + MTK_FUNCTION(4, "I2S5_DO"),
13521 + MTK_FUNCTION(5, "UTXD1"),
13522 + MTK_FUNCTION(6, "TDM_DATA1_2ND"),
13523 + MTK_FUNCTION(7, "ANT_SEL5")
13524 + ),
13525 + MTK_PIN(
13526 + 173, "GPIO173",
13527 + MTK_EINT_FUNCTION(0, 186),
13528 + DRV_GRP4,
13529 + MTK_FUNCTION(0, "GPIO173"),
13530 + MTK_FUNCTION(1, "I2S1_MCK"),
13531 + MTK_FUNCTION(2, "I2S3_MCK"),
13532 + MTK_FUNCTION(3, "SDA8"),
13533 + MTK_FUNCTION(4, "I2S5_MCK"),
13534 + MTK_FUNCTION(5, "UCTS0"),
13535 + MTK_FUNCTION(6, "TDM_DATA2_2ND"),
13536 + MTK_FUNCTION(7, "ANT_SEL6")
13537 + ),
13538 + MTK_PIN(
13539 + 174, "GPIO174",
13540 + MTK_EINT_FUNCTION(0, 187),
13541 + DRV_GRP4,
13542 + MTK_FUNCTION(0, "GPIO174"),
13543 + MTK_FUNCTION(1, "I2S2_DI"),
13544 + MTK_FUNCTION(2, "I2S0_DI"),
13545 + MTK_FUNCTION(3, "DVFSRC_EXT_REQ"),
13546 + MTK_FUNCTION(4, "I2S2_DI2"),
13547 + MTK_FUNCTION(5, "URTS0"),
13548 + MTK_FUNCTION(6, "TDM_DATA3_2ND"),
13549 + MTK_FUNCTION(7, "ANT_SEL7")
13550 + ),
13551 + MTK_PIN(
13552 + 175, "GPIO175",
13553 + MTK_EINT_FUNCTION(0, 188),
13554 + DRV_GRP4,
13555 + MTK_FUNCTION(0, "GPIO175"),
13556 + MTK_FUNCTION(1, "ANT_SEL7")
13557 + ),
13558 + MTK_PIN(
13559 + 176, "GPIO176",
13560 + MTK_EINT_FUNCTION(0, 189),
13561 + DRV_GRP4,
13562 + MTK_FUNCTION(0, "GPIO176")
13563 + ),
13564 + MTK_PIN(
13565 + 177, "GPIO177",
13566 + MTK_EINT_FUNCTION(0, 190),
13567 + DRV_GRP4,
13568 + MTK_FUNCTION(0, "GPIO177")
13569 + ),
13570 + MTK_PIN(
13571 + 178, "GPIO178",
13572 + MTK_EINT_FUNCTION(0, 191),
13573 + DRV_GRP4,
13574 + MTK_FUNCTION(0, "GPIO178")
13575 + ),
13576 + MTK_PIN(
13577 + 179, "GPIO179",
13578 + MTK_EINT_FUNCTION(0, 192),
13579 + DRV_GRP4,
13580 + MTK_FUNCTION(0, "GPIO179")
13581 + ),
13582 + MTK_PIN(
13583 + 180, "GPIO180",
13584 + MTK_EINT_FUNCTION(0, 171),
13585 + DRV_GRP4,
13586 + MTK_FUNCTION(0, "GPIO180")
13587 + ),
13588 + MTK_PIN(
13589 + 181, "GPIO181",
13590 + MTK_EINT_FUNCTION(0, 172),
13591 + DRV_GRP4,
13592 + MTK_FUNCTION(0, "GPIO181")
13593 + ),
13594 + MTK_PIN(
13595 + 182, "GPIO182",
13596 + MTK_EINT_FUNCTION(0, 173),
13597 + DRV_GRP4,
13598 + MTK_FUNCTION(0, "GPIO182")
13599 + ),
13600 + MTK_PIN(
13601 + 183, "GPIO183",
13602 + MTK_EINT_FUNCTION(0, 174),
13603 + DRV_GRP4,
13604 + MTK_FUNCTION(0, "GPIO183")
13605 + ),
13606 + MTK_PIN(
13607 + 184, "GPIO184",
13608 + MTK_EINT_FUNCTION(0, 175),
13609 + DRV_GRP4,
13610 + MTK_FUNCTION(0, "GPIO184")
13611 + ),
13612 + MTK_PIN(
13613 + 185, "GPIO185",
13614 + MTK_EINT_FUNCTION(0, 177),
13615 + DRV_GRP4,
13616 + MTK_FUNCTION(0, "GPIO185")
13617 + ),
13618 + MTK_PIN(
13619 + 186, "GPIO186",
13620 + MTK_EINT_FUNCTION(0, 178),
13621 + DRV_GRP4,
13622 + MTK_FUNCTION(0, "GPIO186")
13623 + ),
13624 + MTK_PIN(
13625 + 187, "GPIO187",
13626 + MTK_EINT_FUNCTION(0, 179),
13627 + DRV_GRP4,
13628 + MTK_FUNCTION(0, "GPIO187")
13629 + ),
13630 + MTK_PIN(
13631 + 188, "GPIO188",
13632 + MTK_EINT_FUNCTION(0, 180),
13633 + DRV_GRP4,
13634 + MTK_FUNCTION(0, "GPIO188")
13635 + ),
13636 + MTK_PIN(
13637 + 189, "GPIO189",
13638 + MTK_EINT_FUNCTION(0, 181),
13639 + DRV_GRP4,
13640 + MTK_FUNCTION(0, "GPIO189")
13641 + ),
13642 + MTK_PIN(
13643 + 190, "GPIO190",
13644 + MTK_EINT_FUNCTION(0, 182),
13645 + DRV_GRP4,
13646 + MTK_FUNCTION(0, "GPIO190")
13647 + ),
13648 + MTK_PIN(
13649 + 191, "GPIO191",
13650 + MTK_EINT_FUNCTION(0, 183),
13651 + DRV_GRP4,
13652 + MTK_FUNCTION(0, "GPIO191")
13653 + ),
13654 +};
13655 +
13656 +#endif /* __PINCTRL_MTK_MT8183_H */
13657 --- /dev/null
13658 +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-mt8516.h
13659 @@ -0,0 +1,1182 @@
13660 +/* SPDX-License-Identifier: GPL-2.0 */
13661 +/*
13662 + * Copyright (C) 2019 MediaTek Inc.
13663 + */
13664 +#ifndef __PINCTRL_MTK_MT8516_H
13665 +#define __PINCTRL_MTK_MT8516_H
13666 +
13667 +#include <linux/pinctrl/pinctrl.h>
13668 +#include "pinctrl-mtk-common.h"
13669 +
13670 +static const struct mtk_desc_pin mtk_pins_mt8516[] = {
13671 + MTK_PIN(
13672 + PINCTRL_PIN(0, "EINT0"),
13673 + NULL, "mt8516",
13674 + MTK_EINT_FUNCTION(0, 0),
13675 + MTK_FUNCTION(0, "GPIO0"),
13676 + MTK_FUNCTION(1, "PWM_B"),
13677 + MTK_FUNCTION(3, "I2S2_BCK"),
13678 + MTK_FUNCTION(4, "EXT_TXD0"),
13679 + MTK_FUNCTION(6, "SQICS"),
13680 + MTK_FUNCTION(7, "DBG_MON_A[6]")
13681 + ),
13682 + MTK_PIN(
13683 + PINCTRL_PIN(1, "EINT1"),
13684 + NULL, "mt8516",
13685 + MTK_EINT_FUNCTION(0, 1),
13686 + MTK_FUNCTION(0, "GPIO1"),
13687 + MTK_FUNCTION(1, "PWM_C"),
13688 + MTK_FUNCTION(3, "I2S2_DI"),
13689 + MTK_FUNCTION(4, "EXT_TXD1"),
13690 + MTK_FUNCTION(5, "CONN_MCU_TDO"),
13691 + MTK_FUNCTION(6, "SQISO"),
13692 + MTK_FUNCTION(7, "DBG_MON_A[7]")
13693 + ),
13694 + MTK_PIN(
13695 + PINCTRL_PIN(2, "EINT2"),
13696 + NULL, "mt8516",
13697 + MTK_EINT_FUNCTION(0, 2),
13698 + MTK_FUNCTION(0, "GPIO2"),
13699 + MTK_FUNCTION(1, "CLKM0"),
13700 + MTK_FUNCTION(3, "I2S2_LRCK"),
13701 + MTK_FUNCTION(4, "EXT_TXD2"),
13702 + MTK_FUNCTION(5, "CONN_MCU_DBGACK_N"),
13703 + MTK_FUNCTION(6, "SQISI"),
13704 + MTK_FUNCTION(7, "DBG_MON_A[8]")
13705 + ),
13706 + MTK_PIN(
13707 + PINCTRL_PIN(3, "EINT3"),
13708 + NULL, "mt8516",
13709 + MTK_EINT_FUNCTION(0, 3),
13710 + MTK_FUNCTION(0, "GPIO3"),
13711 + MTK_FUNCTION(1, "CLKM1"),
13712 + MTK_FUNCTION(3, "SPI_MI"),
13713 + MTK_FUNCTION(4, "EXT_TXD3"),
13714 + MTK_FUNCTION(5, "CONN_MCU_DBGI_N"),
13715 + MTK_FUNCTION(6, "SQIWP"),
13716 + MTK_FUNCTION(7, "DBG_MON_A[9]")
13717 + ),
13718 + MTK_PIN(
13719 + PINCTRL_PIN(4, "EINT4"),
13720 + NULL, "mt8516",
13721 + MTK_EINT_FUNCTION(0, 4),
13722 + MTK_FUNCTION(0, "GPIO4"),
13723 + MTK_FUNCTION(1, "CLKM2"),
13724 + MTK_FUNCTION(3, "SPI_MO"),
13725 + MTK_FUNCTION(4, "EXT_TXC"),
13726 + MTK_FUNCTION(5, "CONN_MCU_TCK"),
13727 + MTK_FUNCTION(6, "CONN_MCU_AICE_JCKC"),
13728 + MTK_FUNCTION(7, "DBG_MON_A[10]")
13729 + ),
13730 + MTK_PIN(
13731 + PINCTRL_PIN(5, "EINT5"),
13732 + NULL, "mt8516",
13733 + MTK_EINT_FUNCTION(0, 5),
13734 + MTK_FUNCTION(0, "GPIO5"),
13735 + MTK_FUNCTION(1, "UCTS2"),
13736 + MTK_FUNCTION(3, "SPI_CSB"),
13737 + MTK_FUNCTION(4, "EXT_RXER"),
13738 + MTK_FUNCTION(5, "CONN_MCU_TDI"),
13739 + MTK_FUNCTION(6, "CONN_TEST_CK"),
13740 + MTK_FUNCTION(7, "DBG_MON_A[11]")
13741 + ),
13742 + MTK_PIN(
13743 + PINCTRL_PIN(6, "EINT6"),
13744 + NULL, "mt8516",
13745 + MTK_EINT_FUNCTION(0, 6),
13746 + MTK_FUNCTION(0, "GPIO6"),
13747 + MTK_FUNCTION(1, "URTS2"),
13748 + MTK_FUNCTION(3, "SPI_CLK"),
13749 + MTK_FUNCTION(4, "EXT_RXC"),
13750 + MTK_FUNCTION(5, "CONN_MCU_TRST_B"),
13751 + MTK_FUNCTION(7, "DBG_MON_A[12]")
13752 + ),
13753 + MTK_PIN(
13754 + PINCTRL_PIN(7, "EINT7"),
13755 + NULL, "mt8516",
13756 + MTK_EINT_FUNCTION(0, 7),
13757 + MTK_FUNCTION(0, "GPIO7"),
13758 + MTK_FUNCTION(1, "SQIRST"),
13759 + MTK_FUNCTION(3, "SDA1_0"),
13760 + MTK_FUNCTION(4, "EXT_RXDV"),
13761 + MTK_FUNCTION(5, "CONN_MCU_TMS"),
13762 + MTK_FUNCTION(6, "CONN_MCU_AICE_JMSC"),
13763 + MTK_FUNCTION(7, "DBG_MON_A[13]")
13764 + ),
13765 + MTK_PIN(
13766 + PINCTRL_PIN(8, "EINT8"),
13767 + NULL, "mt8516",
13768 + MTK_EINT_FUNCTION(0, 8),
13769 + MTK_FUNCTION(0, "GPIO8"),
13770 + MTK_FUNCTION(1, "SQICK"),
13771 + MTK_FUNCTION(2, "CLKM3"),
13772 + MTK_FUNCTION(3, "SCL1_0"),
13773 + MTK_FUNCTION(4, "EXT_RXD0"),
13774 + MTK_FUNCTION(5, "ANT_SEL0"),
13775 + MTK_FUNCTION(7, "DBG_MON_A[14]")
13776 + ),
13777 + MTK_PIN(
13778 + PINCTRL_PIN(9, "EINT9"),
13779 + NULL, "mt8516",
13780 + MTK_EINT_FUNCTION(0, 9),
13781 + MTK_FUNCTION(0, "GPIO9"),
13782 + MTK_FUNCTION(1, "CLKM4"),
13783 + MTK_FUNCTION(2, "SDA2_0"),
13784 + MTK_FUNCTION(3, "EXT_FRAME_SYNC"),
13785 + MTK_FUNCTION(4, "EXT_RXD1"),
13786 + MTK_FUNCTION(5, "ANT_SEL1"),
13787 + MTK_FUNCTION(7, "DBG_MON_A[15]")
13788 + ),
13789 + MTK_PIN(
13790 + PINCTRL_PIN(10, "EINT10"),
13791 + NULL, "mt8516",
13792 + MTK_EINT_FUNCTION(0, 10),
13793 + MTK_FUNCTION(0, "GPIO10"),
13794 + MTK_FUNCTION(1, "CLKM5"),
13795 + MTK_FUNCTION(2, "SCL2_0"),
13796 + MTK_FUNCTION(3, "EXT_FRAME_SYNC"),
13797 + MTK_FUNCTION(4, "EXT_RXD2"),
13798 + MTK_FUNCTION(5, "ANT_SEL2"),
13799 + MTK_FUNCTION(7, "DBG_MON_A[16]")
13800 + ),
13801 + MTK_PIN(
13802 + PINCTRL_PIN(11, "EINT11"),
13803 + NULL, "mt8516",
13804 + MTK_EINT_FUNCTION(0, 11),
13805 + MTK_FUNCTION(0, "GPIO11"),
13806 + MTK_FUNCTION(1, "CLKM4"),
13807 + MTK_FUNCTION(2, "PWM_C"),
13808 + MTK_FUNCTION(3, "CONN_TEST_CK"),
13809 + MTK_FUNCTION(4, "ANT_SEL3"),
13810 + MTK_FUNCTION(6, "EXT_RXD3"),
13811 + MTK_FUNCTION(7, "DBG_MON_A[17]")
13812 + ),
13813 + MTK_PIN(
13814 + PINCTRL_PIN(12, "EINT12"),
13815 + NULL, "mt8516",
13816 + MTK_EINT_FUNCTION(0, 12),
13817 + MTK_FUNCTION(0, "GPIO12"),
13818 + MTK_FUNCTION(1, "CLKM5"),
13819 + MTK_FUNCTION(2, "PWM_A"),
13820 + MTK_FUNCTION(3, "SPDIF_OUT"),
13821 + MTK_FUNCTION(4, "ANT_SEL4"),
13822 + MTK_FUNCTION(6, "EXT_TXEN"),
13823 + MTK_FUNCTION(7, "DBG_MON_A[18]")
13824 + ),
13825 + MTK_PIN(
13826 + PINCTRL_PIN(13, "EINT13"),
13827 + NULL, "mt8516",
13828 + MTK_EINT_FUNCTION(0, 13),
13829 + MTK_FUNCTION(0, "GPIO13"),
13830 + MTK_FUNCTION(3, "TSF_IN"),
13831 + MTK_FUNCTION(4, "ANT_SEL5"),
13832 + MTK_FUNCTION(6, "SPDIF_IN"),
13833 + MTK_FUNCTION(7, "DBG_MON_A[19]")
13834 + ),
13835 + MTK_PIN(
13836 + PINCTRL_PIN(14, "EINT14"),
13837 + NULL, "mt8516",
13838 + MTK_EINT_FUNCTION(0, 14),
13839 + MTK_FUNCTION(0, "GPIO14"),
13840 + MTK_FUNCTION(2, "I2S_8CH_DO1"),
13841 + MTK_FUNCTION(3, "TDM_RX_MCK"),
13842 + MTK_FUNCTION(4, "ANT_SEL1"),
13843 + MTK_FUNCTION(5, "CONN_MCU_DBGACK_N"),
13844 + MTK_FUNCTION(6, "NCLE"),
13845 + MTK_FUNCTION(7, "DBG_MON_B[8]")
13846 + ),
13847 + MTK_PIN(
13848 + PINCTRL_PIN(15, "EINT15"),
13849 + NULL, "mt8516",
13850 + MTK_EINT_FUNCTION(0, 15),
13851 + MTK_FUNCTION(0, "GPIO15"),
13852 + MTK_FUNCTION(2, "I2S_8CH_LRCK"),
13853 + MTK_FUNCTION(3, "TDM_RX_BCK"),
13854 + MTK_FUNCTION(4, "ANT_SEL2"),
13855 + MTK_FUNCTION(5, "CONN_MCU_DBGI_N"),
13856 + MTK_FUNCTION(6, "NCEB1"),
13857 + MTK_FUNCTION(7, "DBG_MON_B[9]")
13858 + ),
13859 + MTK_PIN(
13860 + PINCTRL_PIN(16, "EINT16"),
13861 + NULL, "mt8516",
13862 + MTK_EINT_FUNCTION(0, 16),
13863 + MTK_FUNCTION(0, "GPIO16"),
13864 + MTK_FUNCTION(2, "I2S_8CH_BCK"),
13865 + MTK_FUNCTION(3, "TDM_RX_LRCK"),
13866 + MTK_FUNCTION(4, "ANT_SEL3"),
13867 + MTK_FUNCTION(5, "CONN_MCU_TRST_B"),
13868 + MTK_FUNCTION(6, "NCEB0"),
13869 + MTK_FUNCTION(7, "DBG_MON_B[10]")
13870 + ),
13871 + MTK_PIN(
13872 + PINCTRL_PIN(17, "EINT17"),
13873 + NULL, "mt8516",
13874 + MTK_EINT_FUNCTION(0, 17),
13875 + MTK_FUNCTION(0, "GPIO17"),
13876 + MTK_FUNCTION(2, "I2S_8CH_MCK"),
13877 + MTK_FUNCTION(3, "TDM_RX_DI"),
13878 + MTK_FUNCTION(4, "IDDIG"),
13879 + MTK_FUNCTION(5, "ANT_SEL4"),
13880 + MTK_FUNCTION(6, "NREB"),
13881 + MTK_FUNCTION(7, "DBG_MON_B[11]")
13882 + ),
13883 + MTK_PIN(
13884 + PINCTRL_PIN(18, "EINT18"),
13885 + NULL, "mt8516",
13886 + MTK_EINT_FUNCTION(0, 18),
13887 + MTK_FUNCTION(0, "GPIO18"),
13888 + MTK_FUNCTION(2, "USB_DRVVBUS"),
13889 + MTK_FUNCTION(3, "I2S3_LRCK"),
13890 + MTK_FUNCTION(4, "CLKM1"),
13891 + MTK_FUNCTION(5, "ANT_SEL3"),
13892 + MTK_FUNCTION(6, "I2S2_BCK"),
13893 + MTK_FUNCTION(7, "DBG_MON_A[20]")
13894 + ),
13895 + MTK_PIN(
13896 + PINCTRL_PIN(19, "EINT19"),
13897 + NULL, "mt8516",
13898 + MTK_EINT_FUNCTION(0, 19),
13899 + MTK_FUNCTION(0, "GPIO19"),
13900 + MTK_FUNCTION(1, "UCTS1"),
13901 + MTK_FUNCTION(2, "IDDIG"),
13902 + MTK_FUNCTION(3, "I2S3_BCK"),
13903 + MTK_FUNCTION(4, "CLKM2"),
13904 + MTK_FUNCTION(5, "ANT_SEL4"),
13905 + MTK_FUNCTION(6, "I2S2_DI"),
13906 + MTK_FUNCTION(7, "DBG_MON_A[21]")
13907 + ),
13908 + MTK_PIN(
13909 + PINCTRL_PIN(20, "EINT20"),
13910 + NULL, "mt8516",
13911 + MTK_EINT_FUNCTION(0, 20),
13912 + MTK_FUNCTION(0, "GPIO20"),
13913 + MTK_FUNCTION(1, "URTS1"),
13914 + MTK_FUNCTION(3, "I2S3_DO"),
13915 + MTK_FUNCTION(4, "CLKM3"),
13916 + MTK_FUNCTION(5, "ANT_SEL5"),
13917 + MTK_FUNCTION(6, "I2S2_LRCK"),
13918 + MTK_FUNCTION(7, "DBG_MON_A[22]")
13919 + ),
13920 + MTK_PIN(
13921 + PINCTRL_PIN(21, "EINT21"),
13922 + NULL, "mt8516",
13923 + MTK_EINT_FUNCTION(0, 21),
13924 + MTK_FUNCTION(0, "GPIO21"),
13925 + MTK_FUNCTION(1, "NRNB"),
13926 + MTK_FUNCTION(2, "ANT_SEL0"),
13927 + MTK_FUNCTION(3, "I2S_8CH_DO4"),
13928 + MTK_FUNCTION(7, "DBG_MON_B[31]")
13929 + ),
13930 + MTK_PIN(
13931 + PINCTRL_PIN(22, "EINT22"),
13932 + NULL, "mt8516",
13933 + MTK_EINT_FUNCTION(0, 22),
13934 + MTK_FUNCTION(0, "GPIO22"),
13935 + MTK_FUNCTION(2, "I2S_8CH_DO2"),
13936 + MTK_FUNCTION(3, "TSF_IN"),
13937 + MTK_FUNCTION(4, "USB_DRVVBUS"),
13938 + MTK_FUNCTION(5, "SPDIF_OUT"),
13939 + MTK_FUNCTION(6, "NRE_C"),
13940 + MTK_FUNCTION(7, "DBG_MON_B[12]")
13941 + ),
13942 + MTK_PIN(
13943 + PINCTRL_PIN(23, "EINT23"),
13944 + NULL, "mt8516",
13945 + MTK_EINT_FUNCTION(0, 23),
13946 + MTK_FUNCTION(0, "GPIO23"),
13947 + MTK_FUNCTION(2, "I2S_8CH_DO3"),
13948 + MTK_FUNCTION(3, "CLKM0"),
13949 + MTK_FUNCTION(4, "IR"),
13950 + MTK_FUNCTION(5, "SPDIF_IN"),
13951 + MTK_FUNCTION(6, "NDQS_C"),
13952 + MTK_FUNCTION(7, "DBG_MON_B[13]")
13953 + ),
13954 + MTK_PIN(
13955 + PINCTRL_PIN(24, "EINT24"),
13956 + NULL, "mt8516",
13957 + MTK_EINT_FUNCTION(0, 24),
13958 + MTK_FUNCTION(0, "GPIO24"),
13959 + MTK_FUNCTION(3, "ANT_SEL1"),
13960 + MTK_FUNCTION(4, "UCTS2"),
13961 + MTK_FUNCTION(5, "PWM_A"),
13962 + MTK_FUNCTION(6, "I2S0_MCK"),
13963 + MTK_FUNCTION(7, "DBG_MON_A[0]")
13964 + ),
13965 + MTK_PIN(
13966 + PINCTRL_PIN(25, "EINT25"),
13967 + NULL, "mt8516",
13968 + MTK_EINT_FUNCTION(0, 25),
13969 + MTK_FUNCTION(0, "GPIO25"),
13970 + MTK_FUNCTION(3, "ANT_SEL0"),
13971 + MTK_FUNCTION(4, "URTS2"),
13972 + MTK_FUNCTION(5, "PWM_B"),
13973 + MTK_FUNCTION(6, "I2S_8CH_MCK"),
13974 + MTK_FUNCTION(7, "DBG_MON_A[1]")
13975 + ),
13976 + MTK_PIN(
13977 + PINCTRL_PIN(26, "PWRAP_SPI0_MI"),
13978 + NULL, "mt8516",
13979 + MTK_EINT_FUNCTION(0, 26),
13980 + MTK_FUNCTION(0, "GPIO26"),
13981 + MTK_FUNCTION(1, "PWRAP_SPI0_MO"),
13982 + MTK_FUNCTION(2, "PWRAP_SPI0_MI")
13983 + ),
13984 + MTK_PIN(
13985 + PINCTRL_PIN(27, "PWRAP_SPI0_MO"),
13986 + NULL, "mt8516",
13987 + MTK_EINT_FUNCTION(0, 27),
13988 + MTK_FUNCTION(0, "GPIO27"),
13989 + MTK_FUNCTION(1, "PWRAP_SPI0_MI"),
13990 + MTK_FUNCTION(2, "PWRAP_SPI0_MO")
13991 + ),
13992 + MTK_PIN(
13993 + PINCTRL_PIN(28, "PWRAP_INT"),
13994 + NULL, "mt8516",
13995 + MTK_EINT_FUNCTION(0, 28),
13996 + MTK_FUNCTION(0, "GPIO28"),
13997 + MTK_FUNCTION(1, "I2S0_MCK"),
13998 + MTK_FUNCTION(4, "I2S_8CH_MCK"),
13999 + MTK_FUNCTION(5, "I2S2_MCK"),
14000 + MTK_FUNCTION(6, "I2S3_MCK")
14001 + ),
14002 + MTK_PIN(
14003 + PINCTRL_PIN(29, "PWRAP_SPI0_CK"),
14004 + NULL, "mt8516",
14005 + MTK_EINT_FUNCTION(0, 29),
14006 + MTK_FUNCTION(0, "GPIO29"),
14007 + MTK_FUNCTION(1, "PWRAP_SPI0_CK")
14008 + ),
14009 + MTK_PIN(
14010 + PINCTRL_PIN(30, "PWRAP_SPI0_CSN"),
14011 + NULL, "mt8516",
14012 + MTK_EINT_FUNCTION(0, 30),
14013 + MTK_FUNCTION(0, "GPIO30"),
14014 + MTK_FUNCTION(1, "PWRAP_SPI0_CSN")
14015 + ),
14016 + MTK_PIN(
14017 + PINCTRL_PIN(31, "RTC32K_CK"),
14018 + NULL, "mt8516",
14019 + MTK_EINT_FUNCTION(0, 31),
14020 + MTK_FUNCTION(0, "GPIO31"),
14021 + MTK_FUNCTION(1, "RTC32K_CK")
14022 + ),
14023 + MTK_PIN(
14024 + PINCTRL_PIN(32, "WATCHDOG"),
14025 + NULL, "mt8516",
14026 + MTK_EINT_FUNCTION(0, 32),
14027 + MTK_FUNCTION(0, "GPIO32"),
14028 + MTK_FUNCTION(1, "WATCHDOG")
14029 + ),
14030 + MTK_PIN(
14031 + PINCTRL_PIN(33, "SRCLKENA"),
14032 + NULL, "mt8516",
14033 + MTK_EINT_FUNCTION(0, 33),
14034 + MTK_FUNCTION(0, "GPIO33"),
14035 + MTK_FUNCTION(1, "SRCLKENA0")
14036 + ),
14037 + MTK_PIN(
14038 + PINCTRL_PIN(34, "URXD2"),
14039 + NULL, "mt8516",
14040 + MTK_EINT_FUNCTION(0, 34),
14041 + MTK_FUNCTION(0, "GPIO34"),
14042 + MTK_FUNCTION(1, "URXD2"),
14043 + MTK_FUNCTION(3, "UTXD2"),
14044 + MTK_FUNCTION(4, "DBG_SCL"),
14045 + MTK_FUNCTION(6, "I2S2_MCK"),
14046 + MTK_FUNCTION(7, "DBG_MON_B[0]")
14047 + ),
14048 + MTK_PIN(
14049 + PINCTRL_PIN(35, "UTXD2"),
14050 + NULL, "mt8516",
14051 + MTK_EINT_FUNCTION(0, 35),
14052 + MTK_FUNCTION(0, "GPIO35"),
14053 + MTK_FUNCTION(1, "UTXD2"),
14054 + MTK_FUNCTION(3, "URXD2"),
14055 + MTK_FUNCTION(4, "DBG_SDA"),
14056 + MTK_FUNCTION(6, "I2S3_MCK"),
14057 + MTK_FUNCTION(7, "DBG_MON_B[1]")
14058 + ),
14059 + MTK_PIN(
14060 + PINCTRL_PIN(36, "MRG_CLK"),
14061 + NULL, "mt8516",
14062 + MTK_EINT_FUNCTION(0, 36),
14063 + MTK_FUNCTION(0, "GPIO36"),
14064 + MTK_FUNCTION(1, "MRG_CLK"),
14065 + MTK_FUNCTION(3, "I2S0_BCK"),
14066 + MTK_FUNCTION(4, "I2S3_BCK"),
14067 + MTK_FUNCTION(5, "PCM0_CLK"),
14068 + MTK_FUNCTION(6, "IR"),
14069 + MTK_FUNCTION(7, "DBG_MON_A[2]")
14070 + ),
14071 + MTK_PIN(
14072 + PINCTRL_PIN(37, "MRG_SYNC"),
14073 + NULL, "mt8516",
14074 + MTK_EINT_FUNCTION(0, 37),
14075 + MTK_FUNCTION(0, "GPIO37"),
14076 + MTK_FUNCTION(1, "MRG_SYNC"),
14077 + MTK_FUNCTION(3, "I2S0_LRCK"),
14078 + MTK_FUNCTION(4, "I2S3_LRCK"),
14079 + MTK_FUNCTION(5, "PCM0_SYNC"),
14080 + MTK_FUNCTION(6, "EXT_COL"),
14081 + MTK_FUNCTION(7, "DBG_MON_A[3]")
14082 + ),
14083 + MTK_PIN(
14084 + PINCTRL_PIN(38, "MRG_DI"),
14085 + NULL, "mt8516",
14086 + MTK_EINT_FUNCTION(0, 38),
14087 + MTK_FUNCTION(0, "GPIO38"),
14088 + MTK_FUNCTION(1, "MRG_DI"),
14089 + MTK_FUNCTION(3, "I2S0_DI"),
14090 + MTK_FUNCTION(4, "I2S3_DO"),
14091 + MTK_FUNCTION(5, "PCM0_DI"),
14092 + MTK_FUNCTION(6, "EXT_MDIO"),
14093 + MTK_FUNCTION(7, "DBG_MON_A[4]")
14094 + ),
14095 + MTK_PIN(
14096 + PINCTRL_PIN(39, "MRG_DO"),
14097 + NULL, "mt8516",
14098 + MTK_EINT_FUNCTION(0, 39),
14099 + MTK_FUNCTION(0, "GPIO39"),
14100 + MTK_FUNCTION(1, "MRG_DO"),
14101 + MTK_FUNCTION(3, "I2S0_MCK"),
14102 + MTK_FUNCTION(4, "I2S3_MCK"),
14103 + MTK_FUNCTION(5, "PCM0_DO"),
14104 + MTK_FUNCTION(6, "EXT_MDC"),
14105 + MTK_FUNCTION(7, "DBG_MON_A[5]")
14106 + ),
14107 + MTK_PIN(
14108 + PINCTRL_PIN(40, "KPROW0"),
14109 + NULL, "mt8516",
14110 + MTK_EINT_FUNCTION(0, 40),
14111 + MTK_FUNCTION(0, "GPIO40"),
14112 + MTK_FUNCTION(1, "KPROW0"),
14113 + MTK_FUNCTION(7, "DBG_MON_B[4]")
14114 + ),
14115 + MTK_PIN(
14116 + PINCTRL_PIN(41, "KPROW1"),
14117 + NULL, "mt8516",
14118 + MTK_EINT_FUNCTION(0, 41),
14119 + MTK_FUNCTION(0, "GPIO41"),
14120 + MTK_FUNCTION(1, "KPROW1"),
14121 + MTK_FUNCTION(2, "IDDIG"),
14122 + MTK_FUNCTION(3, "EXT_FRAME_SYNC"),
14123 + MTK_FUNCTION(7, "DBG_MON_B[5]")
14124 + ),
14125 + MTK_PIN(
14126 + PINCTRL_PIN(42, "KPCOL0"),
14127 + NULL, "mt8516",
14128 + MTK_EINT_FUNCTION(0, 42),
14129 + MTK_FUNCTION(0, "GPIO42"),
14130 + MTK_FUNCTION(1, "KPCOL0"),
14131 + MTK_FUNCTION(7, "DBG_MON_B[6]")
14132 + ),
14133 + MTK_PIN(
14134 + PINCTRL_PIN(43, "KPCOL1"),
14135 + NULL, "mt8516",
14136 + MTK_EINT_FUNCTION(0, 43),
14137 + MTK_FUNCTION(0, "GPIO43"),
14138 + MTK_FUNCTION(1, "KPCOL1"),
14139 + MTK_FUNCTION(2, "USB_DRVVBUS"),
14140 + MTK_FUNCTION(3, "EXT_FRAME_SYNC"),
14141 + MTK_FUNCTION(4, "TSF_IN"),
14142 + MTK_FUNCTION(7, "DBG_MON_B[7]")
14143 + ),
14144 + MTK_PIN(
14145 + PINCTRL_PIN(44, "JTMS"),
14146 + NULL, "mt8516",
14147 + MTK_EINT_FUNCTION(0, 44),
14148 + MTK_FUNCTION(0, "GPIO44"),
14149 + MTK_FUNCTION(1, "JTMS"),
14150 + MTK_FUNCTION(2, "CONN_MCU_TMS"),
14151 + MTK_FUNCTION(3, "CONN_MCU_AICE_JMSC")
14152 + ),
14153 + MTK_PIN(
14154 + PINCTRL_PIN(45, "JTCK"),
14155 + NULL, "mt8516",
14156 + MTK_EINT_FUNCTION(0, 45),
14157 + MTK_FUNCTION(0, "GPIO45"),
14158 + MTK_FUNCTION(1, "JTCK"),
14159 + MTK_FUNCTION(2, "CONN_MCU_TCK"),
14160 + MTK_FUNCTION(3, "CONN_MCU_AICE_JCKC")
14161 + ),
14162 + MTK_PIN(
14163 + PINCTRL_PIN(46, "JTDI"),
14164 + NULL, "mt8516",
14165 + MTK_EINT_FUNCTION(0, 46),
14166 + MTK_FUNCTION(0, "GPIO46"),
14167 + MTK_FUNCTION(1, "JTDI"),
14168 + MTK_FUNCTION(2, "CONN_MCU_TDI")
14169 + ),
14170 + MTK_PIN(
14171 + PINCTRL_PIN(47, "JTDO"),
14172 + NULL, "mt8516",
14173 + MTK_EINT_FUNCTION(0, 47),
14174 + MTK_FUNCTION(0, "GPIO47"),
14175 + MTK_FUNCTION(1, "JTDO"),
14176 + MTK_FUNCTION(2, "CONN_MCU_TDO")
14177 + ),
14178 + MTK_PIN(
14179 + PINCTRL_PIN(48, "SPI_CS"),
14180 + NULL, "mt8516",
14181 + MTK_EINT_FUNCTION(0, 48),
14182 + MTK_FUNCTION(0, "GPIO48"),
14183 + MTK_FUNCTION(1, "SPI_CSB"),
14184 + MTK_FUNCTION(3, "I2S0_DI"),
14185 + MTK_FUNCTION(4, "I2S2_BCK"),
14186 + MTK_FUNCTION(7, "DBG_MON_A[23]")
14187 + ),
14188 + MTK_PIN(
14189 + PINCTRL_PIN(49, "SPI_CK"),
14190 + NULL, "mt8516",
14191 + MTK_EINT_FUNCTION(0, 49),
14192 + MTK_FUNCTION(0, "GPIO49"),
14193 + MTK_FUNCTION(1, "SPI_CLK"),
14194 + MTK_FUNCTION(3, "I2S0_LRCK"),
14195 + MTK_FUNCTION(4, "I2S2_DI"),
14196 + MTK_FUNCTION(7, "DBG_MON_A[24]")
14197 + ),
14198 + MTK_PIN(
14199 + PINCTRL_PIN(50, "SPI_MI"),
14200 + NULL, "mt8516",
14201 + MTK_EINT_FUNCTION(0, 50),
14202 + MTK_FUNCTION(0, "GPIO50"),
14203 + MTK_FUNCTION(1, "SPI_MI"),
14204 + MTK_FUNCTION(2, "SPI_MO"),
14205 + MTK_FUNCTION(3, "I2S0_BCK"),
14206 + MTK_FUNCTION(4, "I2S2_LRCK"),
14207 + MTK_FUNCTION(7, "DBG_MON_A[25]")
14208 + ),
14209 + MTK_PIN(
14210 + PINCTRL_PIN(51, "SPI_MO"),
14211 + NULL, "mt8516",
14212 + MTK_EINT_FUNCTION(0, 51),
14213 + MTK_FUNCTION(0, "GPIO51"),
14214 + MTK_FUNCTION(1, "SPI_MO"),
14215 + MTK_FUNCTION(2, "SPI_MI"),
14216 + MTK_FUNCTION(3, "I2S0_MCK"),
14217 + MTK_FUNCTION(4, "I2S2_MCK"),
14218 + MTK_FUNCTION(7, "DBG_MON_A[26]")
14219 + ),
14220 + MTK_PIN(
14221 + PINCTRL_PIN(52, "SDA1"),
14222 + NULL, "mt8516",
14223 + MTK_EINT_FUNCTION(0, 52),
14224 + MTK_FUNCTION(0, "GPIO52"),
14225 + MTK_FUNCTION(1, "SDA1_0")
14226 + ),
14227 + MTK_PIN(
14228 + PINCTRL_PIN(53, "SCL1"),
14229 + NULL, "mt8516",
14230 + MTK_EINT_FUNCTION(0, 53),
14231 + MTK_FUNCTION(0, "GPIO53"),
14232 + MTK_FUNCTION(1, "SCL1_0")
14233 + ),
14234 + MTK_PIN(
14235 + PINCTRL_PIN(54, "GPIO54"),
14236 + NULL, "mt8516",
14237 + MTK_EINT_FUNCTION(0, 54),
14238 + MTK_FUNCTION(0, "GPIO54"),
14239 + MTK_FUNCTION(2, "PWM_B"),
14240 + MTK_FUNCTION(7, "DBG_MON_B[2]")
14241 + ),
14242 + MTK_PIN(
14243 + PINCTRL_PIN(55, "I2S_DATA_IN"),
14244 + NULL, "mt8516",
14245 + MTK_EINT_FUNCTION(0, 55),
14246 + MTK_FUNCTION(0, "GPIO55"),
14247 + MTK_FUNCTION(1, "I2S0_DI"),
14248 + MTK_FUNCTION(2, "UCTS0"),
14249 + MTK_FUNCTION(3, "I2S3_DO"),
14250 + MTK_FUNCTION(4, "I2S_8CH_DO1"),
14251 + MTK_FUNCTION(5, "PWM_A"),
14252 + MTK_FUNCTION(6, "I2S2_BCK"),
14253 + MTK_FUNCTION(7, "DBG_MON_A[28]")
14254 + ),
14255 + MTK_PIN(
14256 + PINCTRL_PIN(56, "I2S_LRCK"),
14257 + NULL, "mt8516",
14258 + MTK_EINT_FUNCTION(0, 56),
14259 + MTK_FUNCTION(0, "GPIO56"),
14260 + MTK_FUNCTION(1, "I2S0_LRCK"),
14261 + MTK_FUNCTION(3, "I2S3_LRCK"),
14262 + MTK_FUNCTION(4, "I2S_8CH_LRCK"),
14263 + MTK_FUNCTION(5, "PWM_B"),
14264 + MTK_FUNCTION(6, "I2S2_DI"),
14265 + MTK_FUNCTION(7, "DBG_MON_A[29]")
14266 + ),
14267 + MTK_PIN(
14268 + PINCTRL_PIN(57, "I2S_BCK"),
14269 + NULL, "mt8516",
14270 + MTK_EINT_FUNCTION(0, 57),
14271 + MTK_FUNCTION(0, "GPIO57"),
14272 + MTK_FUNCTION(1, "I2S0_BCK"),
14273 + MTK_FUNCTION(2, "URTS0"),
14274 + MTK_FUNCTION(3, "I2S3_BCK"),
14275 + MTK_FUNCTION(4, "I2S_8CH_BCK"),
14276 + MTK_FUNCTION(5, "PWM_C"),
14277 + MTK_FUNCTION(6, "I2S2_LRCK"),
14278 + MTK_FUNCTION(7, "DBG_MON_A[30]")
14279 + ),
14280 + MTK_PIN(
14281 + PINCTRL_PIN(58, "SDA0"),
14282 + NULL, "mt8516",
14283 + MTK_EINT_FUNCTION(0, 58),
14284 + MTK_FUNCTION(0, "GPIO58"),
14285 + MTK_FUNCTION(1, "SDA0_0")
14286 + ),
14287 + MTK_PIN(
14288 + PINCTRL_PIN(59, "SCL0"),
14289 + NULL, "mt8516",
14290 + MTK_EINT_FUNCTION(0, 59),
14291 + MTK_FUNCTION(0, "GPIO59"),
14292 + MTK_FUNCTION(1, "SCL0_0")
14293 + ),
14294 + MTK_PIN(
14295 + PINCTRL_PIN(60, "SDA2"),
14296 + NULL, "mt8516",
14297 + MTK_EINT_FUNCTION(0, 60),
14298 + MTK_FUNCTION(0, "GPIO60"),
14299 + MTK_FUNCTION(1, "SDA2_0"),
14300 + MTK_FUNCTION(2, "PWM_B")
14301 + ),
14302 + MTK_PIN(
14303 + PINCTRL_PIN(61, "SCL2"),
14304 + NULL, "mt8516",
14305 + MTK_EINT_FUNCTION(0, 61),
14306 + MTK_FUNCTION(0, "GPIO61"),
14307 + MTK_FUNCTION(1, "SCL2_0"),
14308 + MTK_FUNCTION(2, "PWM_C")
14309 + ),
14310 + MTK_PIN(
14311 + PINCTRL_PIN(62, "URXD0"),
14312 + NULL, "mt8516",
14313 + MTK_EINT_FUNCTION(0, 62),
14314 + MTK_FUNCTION(0, "GPIO62"),
14315 + MTK_FUNCTION(1, "URXD0"),
14316 + MTK_FUNCTION(2, "UTXD0")
14317 + ),
14318 + MTK_PIN(
14319 + PINCTRL_PIN(63, "UTXD0"),
14320 + NULL, "mt8516",
14321 + MTK_EINT_FUNCTION(0, 63),
14322 + MTK_FUNCTION(0, "GPIO63"),
14323 + MTK_FUNCTION(1, "UTXD0"),
14324 + MTK_FUNCTION(2, "URXD0")
14325 + ),
14326 + MTK_PIN(
14327 + PINCTRL_PIN(64, "URXD1"),
14328 + NULL, "mt8516",
14329 + MTK_EINT_FUNCTION(0, 64),
14330 + MTK_FUNCTION(0, "GPIO64"),
14331 + MTK_FUNCTION(1, "URXD1"),
14332 + MTK_FUNCTION(2, "UTXD1"),
14333 + MTK_FUNCTION(7, "DBG_MON_A[27]")
14334 + ),
14335 + MTK_PIN(
14336 + PINCTRL_PIN(65, "UTXD1"),
14337 + NULL, "mt8516",
14338 + MTK_EINT_FUNCTION(0, 65),
14339 + MTK_FUNCTION(0, "GPIO65"),
14340 + MTK_FUNCTION(1, "UTXD1"),
14341 + MTK_FUNCTION(2, "URXD1"),
14342 + MTK_FUNCTION(7, "DBG_MON_A[31]")
14343 + ),
14344 + MTK_PIN(
14345 + PINCTRL_PIN(66, "LCM_RST"),
14346 + NULL, "mt8516",
14347 + MTK_EINT_FUNCTION(0, 66),
14348 + MTK_FUNCTION(0, "GPIO66"),
14349 + MTK_FUNCTION(1, "LCM_RST"),
14350 + MTK_FUNCTION(3, "I2S0_MCK"),
14351 + MTK_FUNCTION(7, "DBG_MON_B[3]")
14352 + ),
14353 + MTK_PIN(
14354 + PINCTRL_PIN(67, "GPIO67"),
14355 + NULL, "mt8516",
14356 + MTK_EINT_FUNCTION(0, 67),
14357 + MTK_FUNCTION(0, "GPIO67"),
14358 + MTK_FUNCTION(3, "I2S_8CH_MCK"),
14359 + MTK_FUNCTION(7, "DBG_MON_B[14]")
14360 + ),
14361 + MTK_PIN(
14362 + PINCTRL_PIN(68, "MSDC2_CMD"),
14363 + NULL, "mt8516",
14364 + MTK_EINT_FUNCTION(0, 68),
14365 + MTK_FUNCTION(0, "GPIO68"),
14366 + MTK_FUNCTION(1, "MSDC2_CMD"),
14367 + MTK_FUNCTION(2, "I2S_8CH_DO4"),
14368 + MTK_FUNCTION(3, "SDA1_0"),
14369 + MTK_FUNCTION(5, "USB_SDA"),
14370 + MTK_FUNCTION(6, "I2S3_BCK"),
14371 + MTK_FUNCTION(7, "DBG_MON_B[15]")
14372 + ),
14373 + MTK_PIN(
14374 + PINCTRL_PIN(69, "MSDC2_CLK"),
14375 + NULL, "mt8516",
14376 + MTK_EINT_FUNCTION(0, 69),
14377 + MTK_FUNCTION(0, "GPIO69"),
14378 + MTK_FUNCTION(1, "MSDC2_CLK"),
14379 + MTK_FUNCTION(2, "I2S_8CH_DO3"),
14380 + MTK_FUNCTION(3, "SCL1_0"),
14381 + MTK_FUNCTION(5, "USB_SCL"),
14382 + MTK_FUNCTION(6, "I2S3_LRCK"),
14383 + MTK_FUNCTION(7, "DBG_MON_B[16]")
14384 + ),
14385 + MTK_PIN(
14386 + PINCTRL_PIN(70, "MSDC2_DAT0"),
14387 + NULL, "mt8516",
14388 + MTK_EINT_FUNCTION(0, 70),
14389 + MTK_FUNCTION(0, "GPIO70"),
14390 + MTK_FUNCTION(1, "MSDC2_DAT0"),
14391 + MTK_FUNCTION(2, "I2S_8CH_DO2"),
14392 + MTK_FUNCTION(5, "UTXD0"),
14393 + MTK_FUNCTION(6, "I2S3_DO"),
14394 + MTK_FUNCTION(7, "DBG_MON_B[17]")
14395 + ),
14396 + MTK_PIN(
14397 + PINCTRL_PIN(71, "MSDC2_DAT1"),
14398 + NULL, "mt8516",
14399 + MTK_EINT_FUNCTION(0, 71),
14400 + MTK_FUNCTION(0, "GPIO71"),
14401 + MTK_FUNCTION(1, "MSDC2_DAT1"),
14402 + MTK_FUNCTION(2, "I2S_8CH_DO1"),
14403 + MTK_FUNCTION(3, "PWM_A"),
14404 + MTK_FUNCTION(4, "I2S3_MCK"),
14405 + MTK_FUNCTION(5, "URXD0"),
14406 + MTK_FUNCTION(6, "PWM_B"),
14407 + MTK_FUNCTION(7, "DBG_MON_B[18]")
14408 + ),
14409 + MTK_PIN(
14410 + PINCTRL_PIN(72, "MSDC2_DAT2"),
14411 + NULL, "mt8516",
14412 + MTK_EINT_FUNCTION(0, 72),
14413 + MTK_FUNCTION(0, "GPIO72"),
14414 + MTK_FUNCTION(1, "MSDC2_DAT2"),
14415 + MTK_FUNCTION(2, "I2S_8CH_LRCK"),
14416 + MTK_FUNCTION(3, "SDA2_0"),
14417 + MTK_FUNCTION(5, "UTXD1"),
14418 + MTK_FUNCTION(6, "PWM_C"),
14419 + MTK_FUNCTION(7, "DBG_MON_B[19]")
14420 + ),
14421 + MTK_PIN(
14422 + PINCTRL_PIN(73, "MSDC2_DAT3"),
14423 + NULL, "mt8516",
14424 + MTK_EINT_FUNCTION(0, 73),
14425 + MTK_FUNCTION(0, "GPIO73"),
14426 + MTK_FUNCTION(1, "MSDC2_DAT3"),
14427 + MTK_FUNCTION(2, "I2S_8CH_BCK"),
14428 + MTK_FUNCTION(3, "SCL2_0"),
14429 + MTK_FUNCTION(4, "EXT_FRAME_SYNC"),
14430 + MTK_FUNCTION(5, "URXD1"),
14431 + MTK_FUNCTION(6, "PWM_A"),
14432 + MTK_FUNCTION(7, "DBG_MON_B[20]")
14433 + ),
14434 + MTK_PIN(
14435 + PINCTRL_PIN(74, "TDN3"),
14436 + NULL, "mt8516",
14437 + MTK_EINT_FUNCTION(0, 74),
14438 + MTK_FUNCTION(0, "GPIO74"),
14439 + MTK_FUNCTION(1, "TDN3")
14440 + ),
14441 + MTK_PIN(
14442 + PINCTRL_PIN(75, "TDP3"),
14443 + NULL, "mt8516",
14444 + MTK_EINT_FUNCTION(0, 75),
14445 + MTK_FUNCTION(0, "GPIO75"),
14446 + MTK_FUNCTION(1, "TDP3")
14447 + ),
14448 + MTK_PIN(
14449 + PINCTRL_PIN(76, "TDN2"),
14450 + NULL, "mt8516",
14451 + MTK_EINT_FUNCTION(0, 76),
14452 + MTK_FUNCTION(0, "GPIO76"),
14453 + MTK_FUNCTION(1, "TDN2")
14454 + ),
14455 + MTK_PIN(
14456 + PINCTRL_PIN(77, "TDP2"),
14457 + NULL, "mt8516",
14458 + MTK_EINT_FUNCTION(0, 77),
14459 + MTK_FUNCTION(0, "GPIO77"),
14460 + MTK_FUNCTION(1, "TDP2")
14461 + ),
14462 + MTK_PIN(
14463 + PINCTRL_PIN(78, "TCN"),
14464 + NULL, "mt8516",
14465 + MTK_EINT_FUNCTION(0, 78),
14466 + MTK_FUNCTION(0, "GPIO78"),
14467 + MTK_FUNCTION(1, "TCN")
14468 + ),
14469 + MTK_PIN(
14470 + PINCTRL_PIN(79, "TCP"),
14471 + NULL, "mt8516",
14472 + MTK_EINT_FUNCTION(0, 79),
14473 + MTK_FUNCTION(0, "GPIO79"),
14474 + MTK_FUNCTION(1, "TCP")
14475 + ),
14476 + MTK_PIN(
14477 + PINCTRL_PIN(80, "TDN1"),
14478 + NULL, "mt8516",
14479 + MTK_EINT_FUNCTION(0, 80),
14480 + MTK_FUNCTION(0, "GPIO80"),
14481 + MTK_FUNCTION(1, "TDN1")
14482 + ),
14483 + MTK_PIN(
14484 + PINCTRL_PIN(81, "TDP1"),
14485 + NULL, "mt8516",
14486 + MTK_EINT_FUNCTION(0, 81),
14487 + MTK_FUNCTION(0, "GPIO81"),
14488 + MTK_FUNCTION(1, "TDP1")
14489 + ),
14490 + MTK_PIN(
14491 + PINCTRL_PIN(82, "TDN0"),
14492 + NULL, "mt8516",
14493 + MTK_EINT_FUNCTION(0, 82),
14494 + MTK_FUNCTION(0, "GPIO82"),
14495 + MTK_FUNCTION(1, "TDN0")
14496 + ),
14497 + MTK_PIN(
14498 + PINCTRL_PIN(83, "TDP0"),
14499 + NULL, "mt8516",
14500 + MTK_EINT_FUNCTION(0, 83),
14501 + MTK_FUNCTION(0, "GPIO83"),
14502 + MTK_FUNCTION(1, "TDP0")
14503 + ),
14504 + MTK_PIN(
14505 + PINCTRL_PIN(84, "RDN0"),
14506 + NULL, "mt8516",
14507 + MTK_EINT_FUNCTION(0, 84),
14508 + MTK_FUNCTION(0, "GPIO84"),
14509 + MTK_FUNCTION(1, "RDN0")
14510 + ),
14511 + MTK_PIN(
14512 + PINCTRL_PIN(85, "RDP0"),
14513 + NULL, "mt8516",
14514 + MTK_EINT_FUNCTION(0, 85),
14515 + MTK_FUNCTION(0, "GPIO85"),
14516 + MTK_FUNCTION(1, "RDP0")
14517 + ),
14518 + MTK_PIN(
14519 + PINCTRL_PIN(86, "RDN1"),
14520 + NULL, "mt8516",
14521 + MTK_EINT_FUNCTION(0, 86),
14522 + MTK_FUNCTION(0, "GPIO86"),
14523 + MTK_FUNCTION(1, "RDN1")
14524 + ),
14525 + MTK_PIN(
14526 + PINCTRL_PIN(87, "RDP1"),
14527 + NULL, "mt8516",
14528 + MTK_EINT_FUNCTION(0, 87),
14529 + MTK_FUNCTION(0, "GPIO87"),
14530 + MTK_FUNCTION(1, "RDP1")
14531 + ),
14532 + MTK_PIN(
14533 + PINCTRL_PIN(88, "RCN"),
14534 + NULL, "mt8516",
14535 + MTK_EINT_FUNCTION(0, 88),
14536 + MTK_FUNCTION(0, "GPIO88"),
14537 + MTK_FUNCTION(1, "RCN")
14538 + ),
14539 + MTK_PIN(
14540 + PINCTRL_PIN(89, "RCP"),
14541 + NULL, "mt8516",
14542 + MTK_EINT_FUNCTION(0, 89),
14543 + MTK_FUNCTION(0, "GPIO89"),
14544 + MTK_FUNCTION(1, "RCP")
14545 + ),
14546 + MTK_PIN(
14547 + PINCTRL_PIN(90, "RDN2"),
14548 + NULL, "mt8516",
14549 + MTK_EINT_FUNCTION(0, 90),
14550 + MTK_FUNCTION(0, "GPIO90"),
14551 + MTK_FUNCTION(1, "RDN2"),
14552 + MTK_FUNCTION(2, "CMDAT8")
14553 + ),
14554 + MTK_PIN(
14555 + PINCTRL_PIN(91, "RDP2"),
14556 + NULL, "mt8516",
14557 + MTK_EINT_FUNCTION(0, 91),
14558 + MTK_FUNCTION(0, "GPIO91"),
14559 + MTK_FUNCTION(1, "RDP2"),
14560 + MTK_FUNCTION(2, "CMDAT9")
14561 + ),
14562 + MTK_PIN(
14563 + PINCTRL_PIN(92, "RDN3"),
14564 + NULL, "mt8516",
14565 + MTK_EINT_FUNCTION(0, 92),
14566 + MTK_FUNCTION(0, "GPIO92"),
14567 + MTK_FUNCTION(1, "RDN3"),
14568 + MTK_FUNCTION(2, "CMDAT4")
14569 + ),
14570 + MTK_PIN(
14571 + PINCTRL_PIN(93, "RDP3"),
14572 + NULL, "mt8516",
14573 + MTK_EINT_FUNCTION(0, 93),
14574 + MTK_FUNCTION(0, "GPIO93"),
14575 + MTK_FUNCTION(1, "RDP3"),
14576 + MTK_FUNCTION(2, "CMDAT5")
14577 + ),
14578 + MTK_PIN(
14579 + PINCTRL_PIN(94, "RCN_A"),
14580 + NULL, "mt8516",
14581 + MTK_EINT_FUNCTION(0, 94),
14582 + MTK_FUNCTION(0, "GPIO94"),
14583 + MTK_FUNCTION(1, "RCN_A"),
14584 + MTK_FUNCTION(2, "CMDAT6")
14585 + ),
14586 + MTK_PIN(
14587 + PINCTRL_PIN(95, "RCP_A"),
14588 + NULL, "mt8516",
14589 + MTK_EINT_FUNCTION(0, 95),
14590 + MTK_FUNCTION(0, "GPIO95"),
14591 + MTK_FUNCTION(1, "RCP_A"),
14592 + MTK_FUNCTION(2, "CMDAT7")
14593 + ),
14594 + MTK_PIN(
14595 + PINCTRL_PIN(96, "RDN1_A"),
14596 + NULL, "mt8516",
14597 + MTK_EINT_FUNCTION(0, 96),
14598 + MTK_FUNCTION(0, "GPIO96"),
14599 + MTK_FUNCTION(1, "RDN1_A"),
14600 + MTK_FUNCTION(2, "CMDAT2"),
14601 + MTK_FUNCTION(3, "CMCSD2")
14602 + ),
14603 + MTK_PIN(
14604 + PINCTRL_PIN(97, "RDP1_A"),
14605 + NULL, "mt8516",
14606 + MTK_EINT_FUNCTION(0, 97),
14607 + MTK_FUNCTION(0, "GPIO97"),
14608 + MTK_FUNCTION(1, "RDP1_A"),
14609 + MTK_FUNCTION(2, "CMDAT3"),
14610 + MTK_FUNCTION(3, "CMCSD3")
14611 + ),
14612 + MTK_PIN(
14613 + PINCTRL_PIN(98, "RDN0_A"),
14614 + NULL, "mt8516",
14615 + MTK_EINT_FUNCTION(0, 98),
14616 + MTK_FUNCTION(0, "GPIO98"),
14617 + MTK_FUNCTION(1, "RDN0_A"),
14618 + MTK_FUNCTION(2, "CMHSYNC")
14619 + ),
14620 + MTK_PIN(
14621 + PINCTRL_PIN(99, "RDP0_A"),
14622 + NULL, "mt8516",
14623 + MTK_EINT_FUNCTION(0, 99),
14624 + MTK_FUNCTION(0, "GPIO99"),
14625 + MTK_FUNCTION(1, "RDP0_A"),
14626 + MTK_FUNCTION(2, "CMVSYNC")
14627 + ),
14628 + MTK_PIN(
14629 + PINCTRL_PIN(100, "CMDAT0"),
14630 + NULL, "mt8516",
14631 + MTK_EINT_FUNCTION(0, 100),
14632 + MTK_FUNCTION(0, "GPIO100"),
14633 + MTK_FUNCTION(1, "CMDAT0"),
14634 + MTK_FUNCTION(2, "CMCSD0"),
14635 + MTK_FUNCTION(3, "ANT_SEL2"),
14636 + MTK_FUNCTION(5, "TDM_RX_MCK"),
14637 + MTK_FUNCTION(7, "DBG_MON_B[21]")
14638 + ),
14639 + MTK_PIN(
14640 + PINCTRL_PIN(101, "CMDAT1"),
14641 + NULL, "mt8516",
14642 + MTK_EINT_FUNCTION(0, 101),
14643 + MTK_FUNCTION(0, "GPIO101"),
14644 + MTK_FUNCTION(1, "CMDAT1"),
14645 + MTK_FUNCTION(2, "CMCSD1"),
14646 + MTK_FUNCTION(3, "ANT_SEL3"),
14647 + MTK_FUNCTION(4, "CMFLASH"),
14648 + MTK_FUNCTION(5, "TDM_RX_BCK"),
14649 + MTK_FUNCTION(7, "DBG_MON_B[22]")
14650 + ),
14651 + MTK_PIN(
14652 + PINCTRL_PIN(102, "CMMCLK"),
14653 + NULL, "mt8516",
14654 + MTK_EINT_FUNCTION(0, 102),
14655 + MTK_FUNCTION(0, "GPIO102"),
14656 + MTK_FUNCTION(1, "CMMCLK"),
14657 + MTK_FUNCTION(3, "ANT_SEL4"),
14658 + MTK_FUNCTION(5, "TDM_RX_LRCK"),
14659 + MTK_FUNCTION(7, "DBG_MON_B[23]")
14660 + ),
14661 + MTK_PIN(
14662 + PINCTRL_PIN(103, "CMPCLK"),
14663 + NULL, "mt8516",
14664 + MTK_EINT_FUNCTION(0, 103),
14665 + MTK_FUNCTION(0, "GPIO103"),
14666 + MTK_FUNCTION(1, "CMPCLK"),
14667 + MTK_FUNCTION(2, "CMCSK"),
14668 + MTK_FUNCTION(3, "ANT_SEL5"),
14669 + MTK_FUNCTION(5, " TDM_RX_DI"),
14670 + MTK_FUNCTION(7, "DBG_MON_B[24]")
14671 + ),
14672 + MTK_PIN(
14673 + PINCTRL_PIN(104, "MSDC1_CMD"),
14674 + NULL, "mt8516",
14675 + MTK_EINT_FUNCTION(0, 104),
14676 + MTK_FUNCTION(0, "GPIO104"),
14677 + MTK_FUNCTION(1, "MSDC1_CMD"),
14678 + MTK_FUNCTION(4, "SQICS"),
14679 + MTK_FUNCTION(7, "DBG_MON_B[25]")
14680 + ),
14681 + MTK_PIN(
14682 + PINCTRL_PIN(105, "MSDC1_CLK"),
14683 + NULL, "mt8516",
14684 + MTK_EINT_FUNCTION(0, 105),
14685 + MTK_FUNCTION(0, "GPIO105"),
14686 + MTK_FUNCTION(1, "MSDC1_CLK"),
14687 + MTK_FUNCTION(4, "SQISO"),
14688 + MTK_FUNCTION(7, "DBG_MON_B[26]")
14689 + ),
14690 + MTK_PIN(
14691 + PINCTRL_PIN(106, "MSDC1_DAT0"),
14692 + NULL, "mt8516",
14693 + MTK_EINT_FUNCTION(0, 106),
14694 + MTK_FUNCTION(0, "GPIO106"),
14695 + MTK_FUNCTION(1, "MSDC1_DAT0"),
14696 + MTK_FUNCTION(4, "SQISI"),
14697 + MTK_FUNCTION(7, "DBG_MON_B[27]")
14698 + ),
14699 + MTK_PIN(
14700 + PINCTRL_PIN(107, "MSDC1_DAT1"),
14701 + NULL, "mt8516",
14702 + MTK_EINT_FUNCTION(0, 107),
14703 + MTK_FUNCTION(0, "GPIO107"),
14704 + MTK_FUNCTION(1, "MSDC1_DAT1"),
14705 + MTK_FUNCTION(4, "SQIWP"),
14706 + MTK_FUNCTION(7, "DBG_MON_B[28]")
14707 + ),
14708 + MTK_PIN(
14709 + PINCTRL_PIN(108, "MSDC1_DAT2"),
14710 + NULL, "mt8516",
14711 + MTK_EINT_FUNCTION(0, 108),
14712 + MTK_FUNCTION(0, "GPIO108"),
14713 + MTK_FUNCTION(1, "MSDC1_DAT2"),
14714 + MTK_FUNCTION(4, "SQIRST"),
14715 + MTK_FUNCTION(7, "DBG_MON_B[29]")
14716 + ),
14717 + MTK_PIN(
14718 + PINCTRL_PIN(109, "MSDC1_DAT3"),
14719 + NULL, "mt8516",
14720 + MTK_EINT_FUNCTION(0, 109),
14721 + MTK_FUNCTION(0, "GPIO109"),
14722 + MTK_FUNCTION(1, "MSDC1_DAT3"),
14723 + MTK_FUNCTION(4, "SQICK"), /* WIP */
14724 + MTK_FUNCTION(7, "DBG_MON_B[30]")
14725 + ),
14726 + MTK_PIN(
14727 + PINCTRL_PIN(110, "MSDC0_DAT7"),
14728 + NULL, "mt8516",
14729 + MTK_EINT_FUNCTION(0, 110),
14730 + MTK_FUNCTION(0, "GPIO110"),
14731 + MTK_FUNCTION(1, "MSDC0_DAT7"),
14732 + MTK_FUNCTION(4, "NLD7")
14733 + ),
14734 + MTK_PIN(
14735 + PINCTRL_PIN(111, "MSDC0_DAT6"),
14736 + NULL, "mt8516",
14737 + MTK_EINT_FUNCTION(0, 111),
14738 + MTK_FUNCTION(0, "GPIO111"),
14739 + MTK_FUNCTION(1, "MSDC0_DAT6"),
14740 + MTK_FUNCTION(4, "NLD6")
14741 + ),
14742 + MTK_PIN(
14743 + PINCTRL_PIN(112, "MSDC0_DAT5"),
14744 + NULL, "mt8516",
14745 + MTK_EINT_FUNCTION(0, 112),
14746 + MTK_FUNCTION(0, "GPIO112"),
14747 + MTK_FUNCTION(1, "MSDC0_DAT5"),
14748 + MTK_FUNCTION(4, "NLD4")
14749 + ),
14750 + MTK_PIN(
14751 + PINCTRL_PIN(113, "MSDC0_DAT4"),
14752 + NULL, "mt8516",
14753 + MTK_EINT_FUNCTION(0, 113),
14754 + MTK_FUNCTION(0, "GPIO113"),
14755 + MTK_FUNCTION(1, "MSDC0_DAT4"),
14756 + MTK_FUNCTION(4, "NLD3")
14757 + ),
14758 + MTK_PIN(
14759 + PINCTRL_PIN(114, "MSDC0_RSTB"),
14760 + NULL, "mt8516",
14761 + MTK_EINT_FUNCTION(0, 114),
14762 + MTK_FUNCTION(0, "GPIO114"),
14763 + MTK_FUNCTION(1, "MSDC0_RSTB"),
14764 + MTK_FUNCTION(4, "NLD0")
14765 + ),
14766 + MTK_PIN(
14767 + PINCTRL_PIN(115, "MSDC0_CMD"),
14768 + NULL, "mt8516",
14769 + MTK_EINT_FUNCTION(0, 115),
14770 + MTK_FUNCTION(0, "GPIO115"),
14771 + MTK_FUNCTION(1, "MSDC0_CMD"),
14772 + MTK_FUNCTION(4, "NALE")
14773 + ),
14774 + MTK_PIN(
14775 + PINCTRL_PIN(116, "MSDC0_CLK"),
14776 + NULL, "mt8516",
14777 + MTK_EINT_FUNCTION(0, 116),
14778 + MTK_FUNCTION(0, "GPIO116"),
14779 + MTK_FUNCTION(1, "MSDC0_CLK"),
14780 + MTK_FUNCTION(4, "NWEB")
14781 + ),
14782 + MTK_PIN(
14783 + PINCTRL_PIN(117, "MSDC0_DAT3"),
14784 + NULL, "mt8516",
14785 + MTK_EINT_FUNCTION(0, 117),
14786 + MTK_FUNCTION(0, "GPIO117"),
14787 + MTK_FUNCTION(1, "MSDC0_DAT3"),
14788 + MTK_FUNCTION(4, "NLD1")
14789 + ),
14790 + MTK_PIN(
14791 + PINCTRL_PIN(118, "MSDC0_DAT2"),
14792 + NULL, "mt8516",
14793 + MTK_EINT_FUNCTION(0, 118),
14794 + MTK_FUNCTION(0, "GPIO118"),
14795 + MTK_FUNCTION(1, "MSDC0_DAT2"),
14796 + MTK_FUNCTION(4, "NLD5")
14797 + ),
14798 + MTK_PIN(
14799 + PINCTRL_PIN(119, "MSDC0_DAT1"),
14800 + NULL, "mt8516",
14801 + MTK_EINT_FUNCTION(0, 119),
14802 + MTK_FUNCTION(0, "GPIO119"),
14803 + MTK_FUNCTION(1, "MSDC0_DAT1"),
14804 + MTK_FUNCTION(4, "NLD8")
14805 + ),
14806 + MTK_PIN(
14807 + PINCTRL_PIN(120, "MSDC0_DAT0"),
14808 + NULL, "mt8516",
14809 + MTK_EINT_FUNCTION(0, 120),
14810 + MTK_FUNCTION(0, "GPIO120"),
14811 + MTK_FUNCTION(1, "MSDC0_DAT0"),
14812 + MTK_FUNCTION(4, "WATCHDOG"),
14813 + MTK_FUNCTION(5, "NLD2")
14814 + ),
14815 + MTK_PIN(
14816 + PINCTRL_PIN(121, "GPIO121"),
14817 + NULL, "mt8516",
14818 + MTK_EINT_FUNCTION(0, 121),
14819 + MTK_FUNCTION(0, "GPIO121")
14820 + ),
14821 + MTK_PIN(
14822 + PINCTRL_PIN(122, "GPIO122"),
14823 + NULL, "mt8516",
14824 + MTK_EINT_FUNCTION(0, 122),
14825 + MTK_FUNCTION(0, "GPIO122")
14826 + ),
14827 + MTK_PIN(
14828 + PINCTRL_PIN(123, "GPIO123"),
14829 + NULL, "mt8516",
14830 + MTK_EINT_FUNCTION(0, 123),
14831 + MTK_FUNCTION(0, "GPIO123")
14832 + ),
14833 + MTK_PIN(
14834 + PINCTRL_PIN(124, "GPIO124"),
14835 + NULL, "mt8516",
14836 + MTK_EINT_FUNCTION(0, 124),
14837 + MTK_FUNCTION(0, "GPIO124")
14838 + ),
14839 +};
14840 +
14841 +#endif /* __PINCTRL_MTK_MT8516_H */
14842 --- /dev/null
14843 +++ b/drivers/pinctrl/mediatek/pinctrl-paris.c
14844 @@ -0,0 +1,947 @@
14845 +// SPDX-License-Identifier: GPL-2.0
14846 +/*
14847 + * MediaTek Pinctrl Paris Driver, which implement the vendor per-pin
14848 + * bindings for MediaTek SoC.
14849 + *
14850 + * Copyright (C) 2018 MediaTek Inc.
14851 + * Author: Sean Wang <sean.wang@mediatek.com>
14852 + * Zhiyong Tao <zhiyong.tao@mediatek.com>
14853 + * Hongzhou.Yang <hongzhou.yang@mediatek.com>
14854 + */
14855 +
14856 +#include <linux/gpio/driver.h>
14857 +#include <dt-bindings/pinctrl/mt65xx.h>
14858 +#include "pinctrl-paris.h"
14859 +
14860 +#define PINCTRL_PINCTRL_DEV KBUILD_MODNAME
14861 +
14862 +/* Custom pinconf parameters */
14863 +#define MTK_PIN_CONFIG_TDSEL (PIN_CONFIG_END + 1)
14864 +#define MTK_PIN_CONFIG_RDSEL (PIN_CONFIG_END + 2)
14865 +#define MTK_PIN_CONFIG_PU_ADV (PIN_CONFIG_END + 3)
14866 +#define MTK_PIN_CONFIG_PD_ADV (PIN_CONFIG_END + 4)
14867 +#define MTK_PIN_CONFIG_DRV_ADV (PIN_CONFIG_END + 5)
14868 +
14869 +static const struct pinconf_generic_params mtk_custom_bindings[] = {
14870 + {"mediatek,tdsel", MTK_PIN_CONFIG_TDSEL, 0},
14871 + {"mediatek,rdsel", MTK_PIN_CONFIG_RDSEL, 0},
14872 + {"mediatek,pull-up-adv", MTK_PIN_CONFIG_PU_ADV, 1},
14873 + {"mediatek,pull-down-adv", MTK_PIN_CONFIG_PD_ADV, 1},
14874 + {"mediatek,drive-strength-adv", MTK_PIN_CONFIG_DRV_ADV, 2},
14875 +};
14876 +
14877 +#ifdef CONFIG_DEBUG_FS
14878 +static const struct pin_config_item mtk_conf_items[] = {
14879 + PCONFDUMP(MTK_PIN_CONFIG_TDSEL, "tdsel", NULL, true),
14880 + PCONFDUMP(MTK_PIN_CONFIG_RDSEL, "rdsel", NULL, true),
14881 + PCONFDUMP(MTK_PIN_CONFIG_PU_ADV, "pu-adv", NULL, true),
14882 + PCONFDUMP(MTK_PIN_CONFIG_PD_ADV, "pd-adv", NULL, true),
14883 + PCONFDUMP(MTK_PIN_CONFIG_DRV_ADV, "drive-strength-adv", NULL, true),
14884 +};
14885 +#endif
14886 +
14887 +static const char * const mtk_gpio_functions[] = {
14888 + "func0", "func1", "func2", "func3",
14889 + "func4", "func5", "func6", "func7",
14890 + "func8", "func9", "func10", "func11",
14891 + "func12", "func13", "func14", "func15",
14892 +};
14893 +
14894 +static int mtk_pinmux_gpio_request_enable(struct pinctrl_dev *pctldev,
14895 + struct pinctrl_gpio_range *range,
14896 + unsigned int pin)
14897 +{
14898 + struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
14899 + const struct mtk_pin_desc *desc;
14900 +
14901 + desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin];
14902 +
14903 + return mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_MODE,
14904 + hw->soc->gpio_m);
14905 +}
14906 +
14907 +static int mtk_pinmux_gpio_set_direction(struct pinctrl_dev *pctldev,
14908 + struct pinctrl_gpio_range *range,
14909 + unsigned int pin, bool input)
14910 +{
14911 + struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
14912 + const struct mtk_pin_desc *desc;
14913 +
14914 + desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin];
14915 +
14916 + /* hardware would take 0 as input direction */
14917 + return mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR, !input);
14918 +}
14919 +
14920 +static int mtk_pinconf_get(struct pinctrl_dev *pctldev,
14921 + unsigned int pin, unsigned long *config)
14922 +{
14923 + struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
14924 + u32 param = pinconf_to_config_param(*config);
14925 + int val, val2, err, reg, ret = 1;
14926 + const struct mtk_pin_desc *desc;
14927 +
14928 + desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin];
14929 +
14930 + switch (param) {
14931 + case PIN_CONFIG_BIAS_DISABLE:
14932 + if (hw->soc->bias_disable_get) {
14933 + err = hw->soc->bias_disable_get(hw, desc, &ret);
14934 + if (err)
14935 + return err;
14936 + } else {
14937 + return -ENOTSUPP;
14938 + }
14939 + break;
14940 + case PIN_CONFIG_BIAS_PULL_UP:
14941 + if (hw->soc->bias_get) {
14942 + err = hw->soc->bias_get(hw, desc, 1, &ret);
14943 + if (err)
14944 + return err;
14945 + } else {
14946 + return -ENOTSUPP;
14947 + }
14948 + break;
14949 + case PIN_CONFIG_BIAS_PULL_DOWN:
14950 + if (hw->soc->bias_get) {
14951 + err = hw->soc->bias_get(hw, desc, 0, &ret);
14952 + if (err)
14953 + return err;
14954 + } else {
14955 + return -ENOTSUPP;
14956 + }
14957 + break;
14958 + case PIN_CONFIG_SLEW_RATE:
14959 + err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_SR, &val);
14960 + if (err)
14961 + return err;
14962 +
14963 + if (!val)
14964 + return -EINVAL;
14965 +
14966 + break;
14967 + case PIN_CONFIG_INPUT_ENABLE:
14968 + case PIN_CONFIG_OUTPUT_ENABLE:
14969 + err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DIR, &val);
14970 + if (err)
14971 + return err;
14972 +
14973 + /* HW takes input mode as zero; output mode as non-zero */
14974 + if ((val && param == PIN_CONFIG_INPUT_ENABLE) ||
14975 + (!val && param == PIN_CONFIG_OUTPUT_ENABLE))
14976 + return -EINVAL;
14977 +
14978 + break;
14979 + case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
14980 + err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DIR, &val);
14981 + if (err)
14982 + return err;
14983 +
14984 + err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_SMT, &val2);
14985 + if (err)
14986 + return err;
14987 +
14988 + if (val || !val2)
14989 + return -EINVAL;
14990 +
14991 + break;
14992 + case PIN_CONFIG_DRIVE_STRENGTH:
14993 + if (hw->soc->drive_get) {
14994 + err = hw->soc->drive_get(hw, desc, &ret);
14995 + if (err)
14996 + return err;
14997 + } else {
14998 + err = -ENOTSUPP;
14999 + }
15000 + break;
15001 + case MTK_PIN_CONFIG_TDSEL:
15002 + case MTK_PIN_CONFIG_RDSEL:
15003 + reg = (param == MTK_PIN_CONFIG_TDSEL) ?
15004 + PINCTRL_PIN_REG_TDSEL : PINCTRL_PIN_REG_RDSEL;
15005 +
15006 + err = mtk_hw_get_value(hw, desc, reg, &val);
15007 + if (err)
15008 + return err;
15009 +
15010 + ret = val;
15011 +
15012 + break;
15013 + case MTK_PIN_CONFIG_PU_ADV:
15014 + case MTK_PIN_CONFIG_PD_ADV:
15015 + if (hw->soc->adv_pull_get) {
15016 + bool pullup;
15017 +
15018 + pullup = param == MTK_PIN_CONFIG_PU_ADV;
15019 + err = hw->soc->adv_pull_get(hw, desc, pullup, &ret);
15020 + if (err)
15021 + return err;
15022 + } else {
15023 + return -ENOTSUPP;
15024 + }
15025 + break;
15026 + case MTK_PIN_CONFIG_DRV_ADV:
15027 + if (hw->soc->adv_drive_get) {
15028 + err = hw->soc->adv_drive_get(hw, desc, &ret);
15029 + if (err)
15030 + return err;
15031 + } else {
15032 + return -ENOTSUPP;
15033 + }
15034 + break;
15035 + default:
15036 + return -ENOTSUPP;
15037 + }
15038 +
15039 + *config = pinconf_to_config_packed(param, ret);
15040 +
15041 + return 0;
15042 +}
15043 +
15044 +static int mtk_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
15045 + enum pin_config_param param,
15046 + enum pin_config_param arg)
15047 +{
15048 + struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
15049 + const struct mtk_pin_desc *desc;
15050 + int err = 0;
15051 + u32 reg;
15052 +
15053 + desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin];
15054 +
15055 + switch ((u32)param) {
15056 + case PIN_CONFIG_BIAS_DISABLE:
15057 + if (hw->soc->bias_disable_set) {
15058 + err = hw->soc->bias_disable_set(hw, desc);
15059 + if (err)
15060 + return err;
15061 + } else {
15062 + return -ENOTSUPP;
15063 + }
15064 + break;
15065 + case PIN_CONFIG_BIAS_PULL_UP:
15066 + if (hw->soc->bias_set) {
15067 + err = hw->soc->bias_set(hw, desc, 1);
15068 + if (err)
15069 + return err;
15070 + } else {
15071 + return -ENOTSUPP;
15072 + }
15073 + break;
15074 + case PIN_CONFIG_BIAS_PULL_DOWN:
15075 + if (hw->soc->bias_set) {
15076 + err = hw->soc->bias_set(hw, desc, 0);
15077 + if (err)
15078 + return err;
15079 + } else {
15080 + return -ENOTSUPP;
15081 + }
15082 + break;
15083 + case PIN_CONFIG_OUTPUT_ENABLE:
15084 + err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_SMT,
15085 + MTK_DISABLE);
15086 + if (err)
15087 + goto err;
15088 +
15089 + err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR,
15090 + MTK_OUTPUT);
15091 + if (err)
15092 + goto err;
15093 + break;
15094 + case PIN_CONFIG_INPUT_ENABLE:
15095 + if (hw->soc->ies_present) {
15096 + mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_IES,
15097 + MTK_ENABLE);
15098 + }
15099 +
15100 + err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR,
15101 + MTK_INPUT);
15102 + if (err)
15103 + goto err;
15104 + break;
15105 + case PIN_CONFIG_SLEW_RATE:
15106 + err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_SR,
15107 + arg);
15108 + if (err)
15109 + goto err;
15110 +
15111 + break;
15112 + case PIN_CONFIG_OUTPUT:
15113 + err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR,
15114 + MTK_OUTPUT);
15115 + if (err)
15116 + goto err;
15117 +
15118 + err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DO,
15119 + arg);
15120 + if (err)
15121 + goto err;
15122 + break;
15123 + case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
15124 + /* arg = 1: Input mode & SMT enable ;
15125 + * arg = 0: Output mode & SMT disable
15126 + */
15127 + arg = arg ? 2 : 1;
15128 + err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR,
15129 + arg & 1);
15130 + if (err)
15131 + goto err;
15132 +
15133 + err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_SMT,
15134 + !!(arg & 2));
15135 + if (err)
15136 + goto err;
15137 + break;
15138 + case PIN_CONFIG_DRIVE_STRENGTH:
15139 + if (hw->soc->drive_set) {
15140 + err = hw->soc->drive_set(hw, desc, arg);
15141 + if (err)
15142 + return err;
15143 + } else {
15144 + return -ENOTSUPP;
15145 + }
15146 + break;
15147 + case MTK_PIN_CONFIG_TDSEL:
15148 + case MTK_PIN_CONFIG_RDSEL:
15149 + reg = (param == MTK_PIN_CONFIG_TDSEL) ?
15150 + PINCTRL_PIN_REG_TDSEL : PINCTRL_PIN_REG_RDSEL;
15151 +
15152 + err = mtk_hw_set_value(hw, desc, reg, arg);
15153 + if (err)
15154 + goto err;
15155 + break;
15156 + case MTK_PIN_CONFIG_PU_ADV:
15157 + case MTK_PIN_CONFIG_PD_ADV:
15158 + if (hw->soc->adv_pull_set) {
15159 + bool pullup;
15160 +
15161 + pullup = param == MTK_PIN_CONFIG_PU_ADV;
15162 + err = hw->soc->adv_pull_set(hw, desc, pullup,
15163 + arg);
15164 + if (err)
15165 + return err;
15166 + } else {
15167 + return -ENOTSUPP;
15168 + }
15169 + break;
15170 + case MTK_PIN_CONFIG_DRV_ADV:
15171 + if (hw->soc->adv_drive_set) {
15172 + err = hw->soc->adv_drive_set(hw, desc, arg);
15173 + if (err)
15174 + return err;
15175 + } else {
15176 + return -ENOTSUPP;
15177 + }
15178 + break;
15179 + default:
15180 + err = -ENOTSUPP;
15181 + }
15182 +
15183 +err:
15184 + return err;
15185 +}
15186 +
15187 +static struct mtk_pinctrl_group *
15188 +mtk_pctrl_find_group_by_pin(struct mtk_pinctrl *hw, u32 pin)
15189 +{
15190 + int i;
15191 +
15192 + for (i = 0; i < hw->soc->ngrps; i++) {
15193 + struct mtk_pinctrl_group *grp = hw->groups + i;
15194 +
15195 + if (grp->pin == pin)
15196 + return grp;
15197 + }
15198 +
15199 + return NULL;
15200 +}
15201 +
15202 +static const struct mtk_func_desc *
15203 +mtk_pctrl_find_function_by_pin(struct mtk_pinctrl *hw, u32 pin_num, u32 fnum)
15204 +{
15205 + const struct mtk_pin_desc *pin = hw->soc->pins + pin_num;
15206 + const struct mtk_func_desc *func = pin->funcs;
15207 +
15208 + while (func && func->name) {
15209 + if (func->muxval == fnum)
15210 + return func;
15211 + func++;
15212 + }
15213 +
15214 + return NULL;
15215 +}
15216 +
15217 +static bool mtk_pctrl_is_function_valid(struct mtk_pinctrl *hw, u32 pin_num,
15218 + u32 fnum)
15219 +{
15220 + int i;
15221 +
15222 + for (i = 0; i < hw->soc->npins; i++) {
15223 + const struct mtk_pin_desc *pin = hw->soc->pins + i;
15224 +
15225 + if (pin->number == pin_num) {
15226 + const struct mtk_func_desc *func = pin->funcs;
15227 +
15228 + while (func && func->name) {
15229 + if (func->muxval == fnum)
15230 + return true;
15231 + func++;
15232 + }
15233 +
15234 + break;
15235 + }
15236 + }
15237 +
15238 + return false;
15239 +}
15240 +
15241 +static int mtk_pctrl_dt_node_to_map_func(struct mtk_pinctrl *pctl,
15242 + u32 pin, u32 fnum,
15243 + struct mtk_pinctrl_group *grp,
15244 + struct pinctrl_map **map,
15245 + unsigned *reserved_maps,
15246 + unsigned *num_maps)
15247 +{
15248 + bool ret;
15249 +
15250 + if (*num_maps == *reserved_maps)
15251 + return -ENOSPC;
15252 +
15253 + (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP;
15254 + (*map)[*num_maps].data.mux.group = grp->name;
15255 +
15256 + ret = mtk_pctrl_is_function_valid(pctl, pin, fnum);
15257 + if (!ret) {
15258 + dev_err(pctl->dev, "invalid function %d on pin %d .\n",
15259 + fnum, pin);
15260 + return -EINVAL;
15261 + }
15262 +
15263 + (*map)[*num_maps].data.mux.function = mtk_gpio_functions[fnum];
15264 + (*num_maps)++;
15265 +
15266 + return 0;
15267 +}
15268 +
15269 +static int mtk_pctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
15270 + struct device_node *node,
15271 + struct pinctrl_map **map,
15272 + unsigned *reserved_maps,
15273 + unsigned *num_maps)
15274 +{
15275 + struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
15276 + int num_pins, num_funcs, maps_per_pin, i, err;
15277 + struct mtk_pinctrl_group *grp;
15278 + unsigned int num_configs;
15279 + bool has_config = false;
15280 + unsigned long *configs;
15281 + u32 pinfunc, pin, func;
15282 + struct property *pins;
15283 + unsigned reserve = 0;
15284 +
15285 + pins = of_find_property(node, "pinmux", NULL);
15286 + if (!pins) {
15287 + dev_err(hw->dev, "missing pins property in node %pOFn .\n",
15288 + node);
15289 + return -EINVAL;
15290 + }
15291 +
15292 + err = pinconf_generic_parse_dt_config(node, pctldev, &configs,
15293 + &num_configs);
15294 + if (err)
15295 + return err;
15296 +
15297 + if (num_configs)
15298 + has_config = true;
15299 +
15300 + num_pins = pins->length / sizeof(u32);
15301 + num_funcs = num_pins;
15302 + maps_per_pin = 0;
15303 + if (num_funcs)
15304 + maps_per_pin++;
15305 + if (has_config && num_pins >= 1)
15306 + maps_per_pin++;
15307 +
15308 + if (!num_pins || !maps_per_pin) {
15309 + err = -EINVAL;
15310 + goto exit;
15311 + }
15312 +
15313 + reserve = num_pins * maps_per_pin;
15314 +
15315 + err = pinctrl_utils_reserve_map(pctldev, map, reserved_maps, num_maps,
15316 + reserve);
15317 + if (err < 0)
15318 + goto exit;
15319 +
15320 + for (i = 0; i < num_pins; i++) {
15321 + err = of_property_read_u32_index(node, "pinmux", i, &pinfunc);
15322 + if (err)
15323 + goto exit;
15324 +
15325 + pin = MTK_GET_PIN_NO(pinfunc);
15326 + func = MTK_GET_PIN_FUNC(pinfunc);
15327 +
15328 + if (pin >= hw->soc->npins ||
15329 + func >= ARRAY_SIZE(mtk_gpio_functions)) {
15330 + dev_err(hw->dev, "invalid pins value.\n");
15331 + err = -EINVAL;
15332 + goto exit;
15333 + }
15334 +
15335 + grp = mtk_pctrl_find_group_by_pin(hw, pin);
15336 + if (!grp) {
15337 + dev_err(hw->dev, "unable to match pin %d to group\n",
15338 + pin);
15339 + err = -EINVAL;
15340 + goto exit;
15341 + }
15342 +
15343 + err = mtk_pctrl_dt_node_to_map_func(hw, pin, func, grp, map,
15344 + reserved_maps, num_maps);
15345 + if (err < 0)
15346 + goto exit;
15347 +
15348 + if (has_config) {
15349 + err = pinctrl_utils_add_map_configs(pctldev, map,
15350 + reserved_maps,
15351 + num_maps,
15352 + grp->name,
15353 + configs,
15354 + num_configs,
15355 + PIN_MAP_TYPE_CONFIGS_GROUP);
15356 + if (err < 0)
15357 + goto exit;
15358 + }
15359 + }
15360 +
15361 + err = 0;
15362 +
15363 +exit:
15364 + kfree(configs);
15365 + return err;
15366 +}
15367 +
15368 +static int mtk_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
15369 + struct device_node *np_config,
15370 + struct pinctrl_map **map,
15371 + unsigned *num_maps)
15372 +{
15373 + struct device_node *np;
15374 + unsigned reserved_maps;
15375 + int ret;
15376 +
15377 + *map = NULL;
15378 + *num_maps = 0;
15379 + reserved_maps = 0;
15380 +
15381 + for_each_child_of_node(np_config, np) {
15382 + ret = mtk_pctrl_dt_subnode_to_map(pctldev, np, map,
15383 + &reserved_maps,
15384 + num_maps);
15385 + if (ret < 0) {
15386 + pinctrl_utils_free_map(pctldev, *map, *num_maps);
15387 + of_node_put(np);
15388 + return ret;
15389 + }
15390 + }
15391 +
15392 + return 0;
15393 +}
15394 +
15395 +static int mtk_pctrl_get_groups_count(struct pinctrl_dev *pctldev)
15396 +{
15397 + struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
15398 +
15399 + return hw->soc->ngrps;
15400 +}
15401 +
15402 +static const char *mtk_pctrl_get_group_name(struct pinctrl_dev *pctldev,
15403 + unsigned group)
15404 +{
15405 + struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
15406 +
15407 + return hw->groups[group].name;
15408 +}
15409 +
15410 +static int mtk_pctrl_get_group_pins(struct pinctrl_dev *pctldev,
15411 + unsigned group, const unsigned **pins,
15412 + unsigned *num_pins)
15413 +{
15414 + struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
15415 +
15416 + *pins = (unsigned *)&hw->groups[group].pin;
15417 + *num_pins = 1;
15418 +
15419 + return 0;
15420 +}
15421 +
15422 +static const struct pinctrl_ops mtk_pctlops = {
15423 + .dt_node_to_map = mtk_pctrl_dt_node_to_map,
15424 + .dt_free_map = pinctrl_utils_free_map,
15425 + .get_groups_count = mtk_pctrl_get_groups_count,
15426 + .get_group_name = mtk_pctrl_get_group_name,
15427 + .get_group_pins = mtk_pctrl_get_group_pins,
15428 +};
15429 +
15430 +static int mtk_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev)
15431 +{
15432 + return ARRAY_SIZE(mtk_gpio_functions);
15433 +}
15434 +
15435 +static const char *mtk_pmx_get_func_name(struct pinctrl_dev *pctldev,
15436 + unsigned selector)
15437 +{
15438 + return mtk_gpio_functions[selector];
15439 +}
15440 +
15441 +static int mtk_pmx_get_func_groups(struct pinctrl_dev *pctldev,
15442 + unsigned function,
15443 + const char * const **groups,
15444 + unsigned * const num_groups)
15445 +{
15446 + struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
15447 +
15448 + *groups = hw->grp_names;
15449 + *num_groups = hw->soc->ngrps;
15450 +
15451 + return 0;
15452 +}
15453 +
15454 +static int mtk_pmx_set_mux(struct pinctrl_dev *pctldev,
15455 + unsigned function,
15456 + unsigned group)
15457 +{
15458 + struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
15459 + struct mtk_pinctrl_group *grp = hw->groups + group;
15460 + const struct mtk_func_desc *desc_func;
15461 + const struct mtk_pin_desc *desc;
15462 + bool ret;
15463 +
15464 + ret = mtk_pctrl_is_function_valid(hw, grp->pin, function);
15465 + if (!ret) {
15466 + dev_err(hw->dev, "invalid function %d on group %d .\n",
15467 + function, group);
15468 + return -EINVAL;
15469 + }
15470 +
15471 + desc_func = mtk_pctrl_find_function_by_pin(hw, grp->pin, function);
15472 + if (!desc_func)
15473 + return -EINVAL;
15474 +
15475 + desc = (const struct mtk_pin_desc *)&hw->soc->pins[grp->pin];
15476 + mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_MODE, desc_func->muxval);
15477 +
15478 + return 0;
15479 +}
15480 +
15481 +static const struct pinmux_ops mtk_pmxops = {
15482 + .get_functions_count = mtk_pmx_get_funcs_cnt,
15483 + .get_function_name = mtk_pmx_get_func_name,
15484 + .get_function_groups = mtk_pmx_get_func_groups,
15485 + .set_mux = mtk_pmx_set_mux,
15486 + .gpio_set_direction = mtk_pinmux_gpio_set_direction,
15487 + .gpio_request_enable = mtk_pinmux_gpio_request_enable,
15488 +};
15489 +
15490 +static int mtk_pconf_group_get(struct pinctrl_dev *pctldev, unsigned group,
15491 + unsigned long *config)
15492 +{
15493 + struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
15494 +
15495 + *config = hw->groups[group].config;
15496 +
15497 + return 0;
15498 +}
15499 +
15500 +static int mtk_pconf_group_set(struct pinctrl_dev *pctldev, unsigned group,
15501 + unsigned long *configs, unsigned num_configs)
15502 +{
15503 + struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
15504 + struct mtk_pinctrl_group *grp = &hw->groups[group];
15505 + int i, ret;
15506 +
15507 + for (i = 0; i < num_configs; i++) {
15508 + ret = mtk_pinconf_set(pctldev, grp->pin,
15509 + pinconf_to_config_param(configs[i]),
15510 + pinconf_to_config_argument(configs[i]));
15511 + if (ret < 0)
15512 + return ret;
15513 +
15514 + grp->config = configs[i];
15515 + }
15516 +
15517 + return 0;
15518 +}
15519 +
15520 +static const struct pinconf_ops mtk_confops = {
15521 + .pin_config_get = mtk_pinconf_get,
15522 + .pin_config_group_get = mtk_pconf_group_get,
15523 + .pin_config_group_set = mtk_pconf_group_set,
15524 +};
15525 +
15526 +static struct pinctrl_desc mtk_desc = {
15527 + .name = PINCTRL_PINCTRL_DEV,
15528 + .pctlops = &mtk_pctlops,
15529 + .pmxops = &mtk_pmxops,
15530 + .confops = &mtk_confops,
15531 + .owner = THIS_MODULE,
15532 +};
15533 +
15534 +static int mtk_gpio_get_direction(struct gpio_chip *chip, unsigned int gpio)
15535 +{
15536 + struct mtk_pinctrl *hw = gpiochip_get_data(chip);
15537 + const struct mtk_pin_desc *desc;
15538 + int value, err;
15539 +
15540 + desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio];
15541 +
15542 + err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DIR, &value);
15543 + if (err)
15544 + return err;
15545 +
15546 + return !value;
15547 +}
15548 +
15549 +static int mtk_gpio_get(struct gpio_chip *chip, unsigned int gpio)
15550 +{
15551 + struct mtk_pinctrl *hw = gpiochip_get_data(chip);
15552 + const struct mtk_pin_desc *desc;
15553 + int value, err;
15554 +
15555 + desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio];
15556 +
15557 + err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DI, &value);
15558 + if (err)
15559 + return err;
15560 +
15561 + return !!value;
15562 +}
15563 +
15564 +static void mtk_gpio_set(struct gpio_chip *chip, unsigned int gpio, int value)
15565 +{
15566 + struct mtk_pinctrl *hw = gpiochip_get_data(chip);
15567 + const struct mtk_pin_desc *desc;
15568 +
15569 + desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio];
15570 +
15571 + mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DO, !!value);
15572 +}
15573 +
15574 +static int mtk_gpio_direction_input(struct gpio_chip *chip, unsigned int gpio)
15575 +{
15576 + return pinctrl_gpio_direction_input(chip->base + gpio);
15577 +}
15578 +
15579 +static int mtk_gpio_direction_output(struct gpio_chip *chip, unsigned int gpio,
15580 + int value)
15581 +{
15582 + mtk_gpio_set(chip, gpio, value);
15583 +
15584 + return pinctrl_gpio_direction_output(chip->base + gpio);
15585 +}
15586 +
15587 +static int mtk_gpio_to_irq(struct gpio_chip *chip, unsigned int offset)
15588 +{
15589 + struct mtk_pinctrl *hw = gpiochip_get_data(chip);
15590 + const struct mtk_pin_desc *desc;
15591 +
15592 + if (!hw->eint)
15593 + return -ENOTSUPP;
15594 +
15595 + desc = (const struct mtk_pin_desc *)&hw->soc->pins[offset];
15596 +
15597 + if (desc->eint.eint_n == EINT_NA)
15598 + return -ENOTSUPP;
15599 +
15600 + return mtk_eint_find_irq(hw->eint, desc->eint.eint_n);
15601 +}
15602 +
15603 +static int mtk_gpio_set_config(struct gpio_chip *chip, unsigned int offset,
15604 + unsigned long config)
15605 +{
15606 + struct mtk_pinctrl *hw = gpiochip_get_data(chip);
15607 + const struct mtk_pin_desc *desc;
15608 + u32 debounce;
15609 +
15610 + desc = (const struct mtk_pin_desc *)&hw->soc->pins[offset];
15611 +
15612 + if (!hw->eint ||
15613 + pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE ||
15614 + desc->eint.eint_n == EINT_NA)
15615 + return -ENOTSUPP;
15616 +
15617 + debounce = pinconf_to_config_argument(config);
15618 +
15619 + return mtk_eint_set_debounce(hw->eint, desc->eint.eint_n, debounce);
15620 +}
15621 +
15622 +static int mtk_build_gpiochip(struct mtk_pinctrl *hw, struct device_node *np)
15623 +{
15624 + struct gpio_chip *chip = &hw->chip;
15625 + int ret;
15626 +
15627 + chip->label = PINCTRL_PINCTRL_DEV;
15628 + chip->parent = hw->dev;
15629 + chip->request = gpiochip_generic_request;
15630 + chip->free = gpiochip_generic_free;
15631 + chip->get_direction = mtk_gpio_get_direction;
15632 + chip->direction_input = mtk_gpio_direction_input;
15633 + chip->direction_output = mtk_gpio_direction_output;
15634 + chip->get = mtk_gpio_get;
15635 + chip->set = mtk_gpio_set;
15636 + chip->to_irq = mtk_gpio_to_irq,
15637 + chip->set_config = mtk_gpio_set_config,
15638 + chip->base = -1;
15639 + chip->ngpio = hw->soc->npins;
15640 + chip->of_node = np;
15641 + chip->of_gpio_n_cells = 2;
15642 +
15643 + ret = gpiochip_add_data(chip, hw);
15644 + if (ret < 0)
15645 + return ret;
15646 +
15647 + return 0;
15648 +}
15649 +
15650 +static int mtk_pctrl_build_state(struct platform_device *pdev)
15651 +{
15652 + struct mtk_pinctrl *hw = platform_get_drvdata(pdev);
15653 + int i;
15654 +
15655 + /* Allocate groups */
15656 + hw->groups = devm_kmalloc_array(&pdev->dev, hw->soc->ngrps,
15657 + sizeof(*hw->groups), GFP_KERNEL);
15658 + if (!hw->groups)
15659 + return -ENOMEM;
15660 +
15661 + /* We assume that one pin is one group, use pin name as group name. */
15662 + hw->grp_names = devm_kmalloc_array(&pdev->dev, hw->soc->ngrps,
15663 + sizeof(*hw->grp_names), GFP_KERNEL);
15664 + if (!hw->grp_names)
15665 + return -ENOMEM;
15666 +
15667 + for (i = 0; i < hw->soc->npins; i++) {
15668 + const struct mtk_pin_desc *pin = hw->soc->pins + i;
15669 + struct mtk_pinctrl_group *group = hw->groups + i;
15670 +
15671 + group->name = pin->name;
15672 + group->pin = pin->number;
15673 +
15674 + hw->grp_names[i] = pin->name;
15675 + }
15676 +
15677 + return 0;
15678 +}
15679 +
15680 +int mtk_paris_pinctrl_probe(struct platform_device *pdev,
15681 + const struct mtk_pin_soc *soc)
15682 +{
15683 + struct pinctrl_pin_desc *pins;
15684 + struct mtk_pinctrl *hw;
15685 + struct resource *res;
15686 + int err, i;
15687 +
15688 + hw = devm_kzalloc(&pdev->dev, sizeof(*hw), GFP_KERNEL);
15689 + if (!hw)
15690 + return -ENOMEM;
15691 +
15692 + platform_set_drvdata(pdev, hw);
15693 + hw->soc = soc;
15694 + hw->dev = &pdev->dev;
15695 +
15696 + if (!hw->soc->nbase_names) {
15697 + dev_err(&pdev->dev,
15698 + "SoC should be assigned at least one register base\n");
15699 + return -EINVAL;
15700 + }
15701 +
15702 + hw->base = devm_kmalloc_array(&pdev->dev, hw->soc->nbase_names,
15703 + sizeof(*hw->base), GFP_KERNEL);
15704 + if (!hw->base)
15705 + return -ENOMEM;
15706 +
15707 + for (i = 0; i < hw->soc->nbase_names; i++) {
15708 + res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
15709 + hw->soc->base_names[i]);
15710 + if (!res) {
15711 + dev_err(&pdev->dev, "missing IO resource\n");
15712 + return -ENXIO;
15713 + }
15714 +
15715 + hw->base[i] = devm_ioremap_resource(&pdev->dev, res);
15716 + if (IS_ERR(hw->base[i]))
15717 + return PTR_ERR(hw->base[i]);
15718 + }
15719 +
15720 + hw->nbase = hw->soc->nbase_names;
15721 +
15722 + err = mtk_pctrl_build_state(pdev);
15723 + if (err) {
15724 + dev_err(&pdev->dev, "build state failed: %d\n", err);
15725 + return -EINVAL;
15726 + }
15727 +
15728 + /* Copy from internal struct mtk_pin_desc to register to the core */
15729 + pins = devm_kmalloc_array(&pdev->dev, hw->soc->npins, sizeof(*pins),
15730 + GFP_KERNEL);
15731 + if (!pins)
15732 + return -ENOMEM;
15733 +
15734 + for (i = 0; i < hw->soc->npins; i++) {
15735 + pins[i].number = hw->soc->pins[i].number;
15736 + pins[i].name = hw->soc->pins[i].name;
15737 + }
15738 +
15739 + /* Setup pins descriptions per SoC types */
15740 + mtk_desc.pins = (const struct pinctrl_pin_desc *)pins;
15741 + mtk_desc.npins = hw->soc->npins;
15742 + mtk_desc.num_custom_params = ARRAY_SIZE(mtk_custom_bindings);
15743 + mtk_desc.custom_params = mtk_custom_bindings;
15744 +#ifdef CONFIG_DEBUG_FS
15745 + mtk_desc.custom_conf_items = mtk_conf_items;
15746 +#endif
15747 +
15748 + err = devm_pinctrl_register_and_init(&pdev->dev, &mtk_desc, hw,
15749 + &hw->pctrl);
15750 + if (err)
15751 + return err;
15752 +
15753 + err = pinctrl_enable(hw->pctrl);
15754 + if (err)
15755 + return err;
15756 +
15757 + err = mtk_build_eint(hw, pdev);
15758 + if (err)
15759 + dev_warn(&pdev->dev,
15760 + "Failed to add EINT, but pinctrl still can work\n");
15761 +
15762 + /* Build gpiochip should be after pinctrl_enable is done */
15763 + err = mtk_build_gpiochip(hw, pdev->dev.of_node);
15764 + if (err) {
15765 + dev_err(&pdev->dev, "Failed to add gpio_chip\n");
15766 + return err;
15767 + }
15768 +
15769 + platform_set_drvdata(pdev, hw);
15770 +
15771 + return 0;
15772 +}
15773 +
15774 +static int mtk_paris_pinctrl_suspend(struct device *device)
15775 +{
15776 + struct mtk_pinctrl *pctl = dev_get_drvdata(device);
15777 +
15778 + return mtk_eint_do_suspend(pctl->eint);
15779 +}
15780 +
15781 +static int mtk_paris_pinctrl_resume(struct device *device)
15782 +{
15783 + struct mtk_pinctrl *pctl = dev_get_drvdata(device);
15784 +
15785 + return mtk_eint_do_resume(pctl->eint);
15786 +}
15787 +
15788 +const struct dev_pm_ops mtk_paris_pinctrl_pm_ops = {
15789 + .suspend_noirq = mtk_paris_pinctrl_suspend,
15790 + .resume_noirq = mtk_paris_pinctrl_resume,
15791 +};
15792 --- /dev/null
15793 +++ b/drivers/pinctrl/mediatek/pinctrl-paris.h
15794 @@ -0,0 +1,65 @@
15795 +/* SPDX-License-Identifier: GPL-2.0 */
15796 +/*
15797 + * Copyright (C) 2018 MediaTek Inc.
15798 + *
15799 + * Author: Sean Wang <sean.wang@mediatek.com>
15800 + * Zhiyong Tao <zhiyong.tao@mediatek.com>
15801 + * Hongzhou.Yang <hongzhou.yang@mediatek.com>
15802 + */
15803 +#ifndef __PINCTRL_PARIS_H
15804 +#define __PINCTRL_PARIS_H
15805 +
15806 +#include <linux/io.h>
15807 +#include <linux/init.h>
15808 +#include <linux/of.h>
15809 +#include <linux/of_platform.h>
15810 +#include <linux/platform_device.h>
15811 +#include <linux/pinctrl/pinctrl.h>
15812 +#include <linux/pinctrl/pinmux.h>
15813 +#include <linux/pinctrl/pinconf.h>
15814 +#include <linux/pinctrl/pinconf-generic.h>
15815 +
15816 +#include "../core.h"
15817 +#include "../pinconf.h"
15818 +#include "../pinctrl-utils.h"
15819 +#include "../pinmux.h"
15820 +#include "mtk-eint.h"
15821 +#include "pinctrl-mtk-common-v2.h"
15822 +
15823 +#define MTK_RANGE(_a) { .range = (_a), .nranges = ARRAY_SIZE(_a), }
15824 +
15825 +#define MTK_EINT_FUNCTION(_eintmux, _eintnum) \
15826 + { \
15827 + .eint_m = _eintmux, \
15828 + .eint_n = _eintnum, \
15829 + }
15830 +
15831 +#define MTK_FUNCTION(_val, _name) \
15832 + { \
15833 + .muxval = _val, \
15834 + .name = _name, \
15835 + }
15836 +
15837 +#define MTK_PIN(_number, _name, _eint, _drv_n, ...) { \
15838 + .number = _number, \
15839 + .name = _name, \
15840 + .eint = _eint, \
15841 + .drv_n = _drv_n, \
15842 + .funcs = (struct mtk_func_desc[]){ \
15843 + __VA_ARGS__, { } }, \
15844 + }
15845 +
15846 +#define PINCTRL_PIN_GROUP(name, id) \
15847 + { \
15848 + name, \
15849 + id##_pins, \
15850 + ARRAY_SIZE(id##_pins), \
15851 + id##_funcs, \
15852 + }
15853 +
15854 +int mtk_paris_pinctrl_probe(struct platform_device *pdev,
15855 + const struct mtk_pin_soc *soc);
15856 +
15857 +extern const struct dev_pm_ops mtk_paris_pinctrl_pm_ops;
15858 +
15859 +#endif /* __PINCTRL_PARIS_H */
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