1 From 05be818061b9f2a0fa5ad0cde6881917ff14a2f2 Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Wed, 6 Jan 2016 21:55:10 +0100
4 Subject: [PATCH 024/102] dt-bindings: add MediaTek PCIe binding documentation
6 Signed-off-by: John Crispin <blogic@openwrt.org>
8 .../devicetree/bindings/pci/mediatek-pcie.txt | 140 ++++++++++++++++++++
9 1 file changed, 140 insertions(+)
10 create mode 100644 Documentation/devicetree/bindings/pci/mediatek-pcie.txt
12 diff --git a/Documentation/devicetree/bindings/pci/mediatek-pcie.txt b/Documentation/devicetree/bindings/pci/mediatek-pcie.txt
14 index 0000000..8fea3ed
16 +++ b/Documentation/devicetree/bindings/pci/mediatek-pcie.txt
18 +Mediatek PCIe controller
21 +- compatible: Should be one of:
22 + - "mediatek,mt2701-pcie"
23 + - "mediatek,mt7623-pcie"
24 +- device_type: Must be "pci"
25 +- reg: A list of physical base address and length for each set of controller
26 + registers. A list of register ranges to use. Must contain an
27 + entry for each entry in the reg-names property.
28 +- reg-names: Must include the following entries:
29 + "pcie": PCIe registers
30 + "pcie phy0": PCIe PHY0 registers
31 + "pcie phy1": PCIe PHY0 registers
32 + "pcie phy2": PCIe PHY0 registers
33 +- interrupts: A list of interrupt outputs of the controller. Must contain an
34 + entry for each entry in the interrupt-names property.
35 +- interrupt-names: Must include the following entries:
36 + "pcie0": The interrupt that is asserted for port0
37 + "pcie1": The interrupt that is asserted for port1
38 + "pcie2": The interrupt that is asserted for port2
39 +- bus-range: Range of bus numbers associated with this controller
40 +- #address-cells: Address representation for root ports (must be 3)
41 +- #size-cells: Size representation for root ports (must be 2)
42 +- ranges: Describes the translation of addresses for root ports and standard
43 + PCI regions. The entries must be 6 cells each.
44 + Please refer to the standard PCI bus binding document for a more detailed
46 +- #interrupt-cells: Size representation for interrupts (must be 1)
47 +- clocks: Must contain an entry for each entry in clock-names.
48 + See ../clocks/clock-bindings.txt for details.
49 +- clock-names: Must include the following entries:
53 +- resets: Must contain an entry for each entry in reset-names.
54 + See ../reset/reset.txt for details.
55 +- reset-names: Must include the following entries:
59 +- mediatek,hifsys: Must contain a phandle to the HIFSYS syscon range.
60 +Root ports are defined as subnodes of the PCIe controller node.
63 +- device_type: Must be "pci"
64 +- assigned-addresses: Address and size of the port configuration registers
65 +- reg: PCI bus address of the root port
66 +- #address-cells: Must be 3
67 +- #size-cells: Must be 2
68 +- ranges: Sub-ranges distributed from the PCIe controller node. An empty
69 + property is sufficient.
75 + hifsys: clock-controller@1a000000 {
76 + compatible = "mediatek,mt7623-hifsys",
77 + "mediatek,mt2701-hifsys",
79 + reg = <0 0x1a000000 0 0x1000>;
84 + pcie-controller@1a140000 {
85 + compatible = "mediatek,mt7623-pcie";
86 + device_type = "pci";
87 + reg = <0 0x1a140000 0 0x8000>, /* PCI-Express registers */
88 + <0 0x1a149000 0 0x1000>, /* PCI-Express PHY0 */
89 + <0 0x1a14a000 0 0x1000>, /* PCI-Express PHY1 */
90 + <0 0x1a244000 0 0x1000>; /* PCI-Express PHY2 */
91 + reg-names = "pcie", "pcie phy0", "pcie phy1", "pcie phy2";
92 + interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>,
93 + <GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>,
94 + <GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
95 + interrupt-names = "pcie0", "pcie1", "pcie2";
96 + clocks = <&topckgen CLK_TOP_ETHIF_SEL>;
97 + clock-names = "pcie";
98 + power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
99 + resets = <&hifsys MT2701_HIFSYS_PCIE0_RST>,
100 + <&hifsys MT2701_HIFSYS_PCIE1_RST>,
101 + <&hifsys MT2701_HIFSYS_PCIE2_RST>;
102 + reset-names = "pcie0", "pice1", "pcie2";
104 + bus-range = <0x00 0xff>;
105 + #address-cells = <3>;
108 + mediatek,hifsys = <&hifsys>;
110 + ranges = <0x81000000 0 0x1a160000 0 0x1a160000 0 0x00010000 /* io space */
111 + 0x83000000 0 0x60000000 0 0x60000000 0 0x10000000>; /* pci memory */
113 + status = "disabled";
116 + device_type = "pci";
117 + reg = <0x0800 0 0 0 0>;
119 + #address-cells = <3>;
123 + status = "disabled";
127 + device_type = "pci";
128 + reg = <0x1000 0 0 0 0>;
130 + #address-cells = <3>;
134 + status = "disabled";
138 + device_type = "pci";
139 + reg = <0x1800 0 0 0 0>;
141 + #address-cells = <3>;
145 + status = "disabled";