1 From 8ab1d4e0a9a68e03f472dee1c036a01d0198c20c Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Tue, 5 Jan 2016 20:20:04 +0100
4 Subject: [PATCH 025/102] PCI: mediatek: add support for PCIe found on
7 Add PCIe controller support on MediaTek MT2701/MT7623. The driver supports
8 a single Root complex (RC) with 3 Root Ports. The SoCs supports a Gen2
9 1-lan Link on each port.
11 Signed-off-by: John Crispin <blogic@openwrt.org>
13 arch/arm/mach-mediatek/Kconfig | 1 +
14 drivers/pci/host/Kconfig | 11 +
15 drivers/pci/host/Makefile | 1 +
16 drivers/pci/host/pcie-mediatek.c | 641 ++++++++++++++++++++++++++++++++++++++
17 4 files changed, 654 insertions(+)
18 create mode 100644 drivers/pci/host/pcie-mediatek.c
20 diff --git a/arch/arm/mach-mediatek/Kconfig b/arch/arm/mach-mediatek/Kconfig
21 index 7fb605e..a7fef77 100644
22 --- a/arch/arm/mach-mediatek/Kconfig
23 +++ b/arch/arm/mach-mediatek/Kconfig
24 @@ -24,6 +24,7 @@ config MACH_MT6592
26 bool "MediaTek MT7623 SoCs support"
28 + select MIGHT_HAVE_PCI
31 bool "MediaTek MT8127 SoCs support"
32 diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig
33 index f131ba9..912f0e1 100644
34 --- a/drivers/pci/host/Kconfig
35 +++ b/drivers/pci/host/Kconfig
36 @@ -172,4 +172,15 @@ config PCI_HISI
38 Say Y here if you want PCIe controller support on HiSilicon HIP05 SoC
41 + bool "Mediatek PCIe Controller"
42 + depends on MACH_MT2701 || MACH_MT7623
46 + Say Y here if you want to enable PCI controller support on Mediatek MT7623.
47 + MT7623 PCIe supports single Root complex (RC) with 3 Root Ports.
48 + Each port supports a Gen2 1-lan Link.
49 + PCIe include one Host/PCI bridge and 3 PCIe MAC.
52 diff --git a/drivers/pci/host/Makefile b/drivers/pci/host/Makefile
53 index 9d4d3c6..3b53374 100644
54 --- a/drivers/pci/host/Makefile
55 +++ b/drivers/pci/host/Makefile
56 @@ -20,3 +20,4 @@ obj-$(CONFIG_PCIE_IPROC_BCMA) += pcie-iproc-bcma.o
57 obj-$(CONFIG_PCIE_ALTERA) += pcie-altera.o
58 obj-$(CONFIG_PCIE_ALTERA_MSI) += pcie-altera-msi.o
59 obj-$(CONFIG_PCI_HISI) += pcie-hisi.o
60 +obj-$(CONFIG_PCIE_MTK) += pcie-mediatek.o
61 diff --git a/drivers/pci/host/pcie-mediatek.c b/drivers/pci/host/pcie-mediatek.c
63 index 0000000..ef03952
65 +++ b/drivers/pci/host/pcie-mediatek.c
68 + * Mediatek MT2701/MT7623 SoC PCIE support
70 + * Copyright (C) 2015 Mediatek
71 + * Copyright (C) 2015 Ziv Huang <ziv.huang@mediatek.com>
72 + * Copyright (C) 2015 John Crispin <blogic@openwrt.org>
74 + * This program is free software; you can redistribute it and/or modify it
75 + * under the terms of the GNU General Public License version 2 as published
76 + * by the Free Software Foundation.
79 +#include <linux/kernel.h>
80 +#include <linux/pci.h>
81 +#include <linux/ioport.h>
82 +#include <linux/interrupt.h>
83 +#include <linux/spinlock.h>
84 +#include <linux/init.h>
85 +#include <linux/device.h>
86 +#include <linux/io.h>
87 +#include <linux/delay.h>
89 +#include <asm/mach/pci.h>
90 +#include <linux/module.h>
91 +#include <linux/of.h>
92 +#include <linux/of_address.h>
93 +#include <linux/of_pci.h>
94 +#include <linux/of_platform.h>
95 +#include <linux/of_irq.h>
96 +#include <linux/reset.h>
97 +#include <linux/platform_device.h>
98 +#include <linux/regulator/consumer.h>
99 +#include <linux/pm_runtime.h>
100 +#include <linux/clk.h>
101 +#include <linux/regmap.h>
102 +#include <linux/mfd/syscon.h>
104 +#define MEMORY_BASE 0x80000000
106 +/* PCIE Registers */
110 +#define CFGADDR 0x20
111 +#define CFGDATA 0x24
112 +#define MEMBASE 0x28
115 +/* per Port Registers */
116 +#define BAR0SETUP 0x10
117 +#define IMBASEBAR0 0x18
118 +#define PCIE_CLASS 0x34
119 +#define PCIE_SISTAT 0x50
121 +#define MTK_PCIE_HIGH_PERF BIT(14)
122 +#define PCIEP0_BASE 0x2000
123 +#define PCIEP1_BASE 0x3000
124 +#define PCIEP2_BASE 0x4000
126 +#define PHY_P0_CTL 0x9000
127 +#define PHY_P1_CTL 0xa000
128 +#define PHY_P2_CTL 0x4000
130 +#define RSTCTL_PCIE0_RST BIT(24)
131 +#define RSTCTL_PCIE1_RST BIT(25)
132 +#define RSTCTL_PCIE2_RST BIT(26)
134 +#define HIFSYS_SYSCFG1 0x14
135 +#define HIFSYS_SYSCFG1_PHY2_MASK (0x3 << 20)
137 +#define MTK_PHY_CLK 0xb00
138 +#define MTK_PHY_CLKDRV_OFFSET BIT(2)
139 +#define MTK_PHY_CLKDRV_OFFSET_MASK 0xe
140 +#define MTK_PHY_PLL 0xb04
141 +#define MTK_PHY_CLKDRV_AMP BIT(30)
142 +#define MTK_PHY_CLKDRV_AMP_MASK 0xe0000000
143 +#define MTK_PHY_REFCLK_SEL 0xc00
144 +#define MTK_PHY_XTAL_EXT_EN (BIT(17) | BIT(12))
145 +#define MTK_PHY_XTAL_EXT_EN_MASK 0x33000
146 +#define MTK_PHY_PLL_BC 0xc08
147 +#define MTK_PHY_PLL_BC_PE2H 0xc0
148 +#define MTK_PHY_PLL_BC_PE2H_MASK 0x380000
149 +#define MTK_PHY_PLL_IC 0xc0c
150 +#define MTK_PHY_PLL_IC_BR_PE2H BIT(28)
151 +#define MTK_PHY_PLL_IC_BR_PE2H_MASK 0x30000000
152 +#define MTK_PHY_PLL_IC_PE2H BIT(12)
153 +#define MTK_PHY_PLL_IC_PE2H_MASK 0xf000
154 +#define MTK_PHY_PLL_IR 0xc10
155 +#define MTK_PHY_PLL_IR_PE2H BIT(17)
156 +#define MTK_PHY_PLL_IR_PE2H_MASK 0xf0000
157 +#define MTK_PHY_PLL_BP 0xc14
158 +#define MTK_PHY_PLL_BP_PE2H (BIT(19) | BIT(17))
159 +#define MTK_PHY_PLL_BP_PE2H_MASK 0xf0000
160 +#define MTK_PHY_SSC_DELTA1 0xc3c
161 +#define MTK_PHY_SSC_DELTA1_PE2H (0x3c << 16)
162 +#define MTK_PHY_SSC_DELTA1_PE2H_MASK 0xffff0000
163 +#define MTK_PHY_SSC_DELTA 0xc48
164 +#define MTK_PHY_SSC_DELTA_PE2H 0x36
165 +#define MTK_PHY_SSC_DELTA_PE2H_MASK 0xffff
167 +#define MAX_PORT_NUM 3
169 +struct mtk_pcie_port {
174 + void __iomem *phy_base;
175 + struct reset_control *rstc;
178 +#define mtk_foreach_port(pcie, p) \
179 + for ((p) = pcie->port; \
180 + (p) != &pcie->port[MAX_PORT_NUM]; (p)++)
183 + struct device *dev;
184 + void __iomem *pcie_base;
185 + struct regmap *hifsys;
187 + struct resource io;
188 + struct resource pio;
189 + struct resource mem;
190 + struct resource prefetch;
191 + struct resource busn;
198 + struct mtk_pcie_port port[MAX_PORT_NUM];
199 + int pcie_card_link;
202 +static struct mtk_pcie_port_data {
206 +} mtk_pcie_port_data[MAX_PORT_NUM] = {
207 + { PCIEP0_BASE, BIT(1), BIT(20) },
208 + { PCIEP1_BASE, BIT(2), BIT(21) },
209 + { PCIEP2_BASE, BIT(3), BIT(22) },
212 +static const struct mtk_phy_init {
216 +} mtk_phy_init[] = {
217 + { MTK_PHY_REFCLK_SEL, MTK_PHY_XTAL_EXT_EN_MASK, MTK_PHY_XTAL_EXT_EN },
218 + { MTK_PHY_PLL, MTK_PHY_CLKDRV_AMP_MASK, MTK_PHY_CLKDRV_AMP },
219 + { MTK_PHY_CLK, MTK_PHY_CLKDRV_OFFSET_MASK, MTK_PHY_CLKDRV_OFFSET },
220 + { MTK_PHY_SSC_DELTA1, MTK_PHY_SSC_DELTA1_PE2H_MASK, MTK_PHY_SSC_DELTA1_PE2H },
221 + { MTK_PHY_SSC_DELTA, MTK_PHY_SSC_DELTA_PE2H_MASK, MTK_PHY_SSC_DELTA_PE2H },
222 + { MTK_PHY_PLL_IC, MTK_PHY_PLL_IC_BR_PE2H_MASK, MTK_PHY_PLL_IC_BR_PE2H },
223 + { MTK_PHY_PLL_BC, MTK_PHY_PLL_BC_PE2H_MASK, MTK_PHY_PLL_BC_PE2H },
224 + { MTK_PHY_PLL_IR, MTK_PHY_PLL_IR_PE2H_MASK, MTK_PHY_PLL_IR_PE2H },
225 + { MTK_PHY_PLL_IC, MTK_PHY_PLL_IC_PE2H_MASK, MTK_PHY_PLL_IC_PE2H },
226 + { MTK_PHY_PLL_BP, MTK_PHY_PLL_BP_PE2H_MASK, MTK_PHY_PLL_BP_PE2H },
229 +static struct mtk_pcie *sys_to_pcie(struct pci_sys_data *sys)
231 + return sys->private_data;
234 +static void pcie_w32(struct mtk_pcie *pcie, u32 val, unsigned reg)
236 + iowrite32(val, pcie->pcie_base + reg);
239 +static u32 pcie_r32(struct mtk_pcie *pcie, unsigned reg)
241 + return ioread32(pcie->pcie_base + reg);
244 +static void pcie_m32(struct mtk_pcie *pcie, u32 mask, u32 val, unsigned reg)
246 + u32 v = pcie_r32(pcie, reg);
250 + pcie_w32(pcie, v, reg);
253 +static int pcie_config_read(struct pci_bus *bus, unsigned int devfn, int where,
254 + int size, u32 *val)
256 + struct mtk_pcie *pcie = sys_to_pcie(bus->sysdata);
257 + unsigned int slot = PCI_SLOT(devfn);
258 + u8 func = PCI_FUNC(devfn);
266 + address = (((where & 0xf00) >> 8) << 24) |
272 + pcie_w32(pcie, address, CFGADDR);
273 + data = pcie_r32(pcie, CFGDATA);
277 + *val = (data >> ((where & 3) << 3)) & 0xff;
280 + *val = (data >> ((where & 3) << 3)) & 0xffff;
287 + return PCIBIOS_SUCCESSFUL;
290 +static int pcie_config_write(struct pci_bus *bus, unsigned int devfn, int where,
293 + struct mtk_pcie *pcie = sys_to_pcie(bus->sysdata);
294 + unsigned int slot = PCI_SLOT(devfn);
295 + u8 func = PCI_FUNC(devfn);
303 + address = (((where & 0xf00) >> 8) << 24) |
304 + (num << 16) | (slot << 11) | (func << 8) | (where & 0xfc);
305 + pcie_w32(pcie, address, CFGADDR);
306 + data = pcie_r32(pcie, CFGDATA);
310 + data = (data & ~(0xff << ((where & 3) << 3))) |
311 + (val << ((where & 3) << 3));
314 + data = (data & ~(0xffff << ((where & 3) << 3))) |
315 + (val << ((where & 3) << 3));
321 + pcie_w32(pcie, data, CFGDATA);
323 + return PCIBIOS_SUCCESSFUL;
326 +static struct pci_ops mtk_pcie_ops = {
327 + .read = pcie_config_read,
328 + .write = pcie_config_write,
331 +static int __init mtk_pcie_setup(int nr, struct pci_sys_data *sys)
333 + struct mtk_pcie *pcie = sys_to_pcie(sys);
335 + request_resource(&ioport_resource, &pcie->pio);
336 + request_resource(&iomem_resource, &pcie->mem);
338 + pci_add_resource_offset(&sys->resources, &pcie->mem, sys->mem_offset);
339 + pci_add_resource_offset(&sys->resources, &pcie->pio, sys->io_offset);
340 + pci_add_resource(&sys->resources, &pcie->busn);
345 +static struct pci_bus * __init mtk_pcie_scan_bus(int nr,
346 + struct pci_sys_data *sys)
348 + struct mtk_pcie *pcie = sys_to_pcie(sys);
349 + struct pci_bus *bus;
351 + bus = pci_create_root_bus(pcie->dev, sys->busnr, &mtk_pcie_ops, sys,
356 + pci_scan_child_bus(bus);
361 +static int __init mtk_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
363 + struct mtk_pcie *pcie = sys_to_pcie(dev->bus->sysdata);
364 + struct mtk_pcie_port *port;
367 + mtk_foreach_port(pcie, port)
368 + if (port->id == slot)
374 +static void mtk_pcie_configure_phy(struct mtk_pcie *pcie,
375 + struct mtk_pcie_port *port)
379 + for (i = 0; i < ARRAY_SIZE(mtk_phy_init); i++) {
380 + void __iomem *phy_addr = port->phy_base + mtk_phy_init[i].reg;
381 + u32 val = ioread32(phy_addr);
383 + val &= ~mtk_phy_init[i].mask;
384 + val |= mtk_phy_init[i].val;
385 + iowrite32(val, phy_addr);
387 + usleep_range(5000, 6000);
390 +static void mtk_pcie_configure_rc(struct mtk_pcie *pcie,
391 + struct mtk_pcie_port *port,
392 + struct pci_bus *bus)
396 + pcie_config_write(bus,
398 + PCI_BASE_ADDRESS_0, 4, MEMORY_BASE);
400 + pcie_config_read(bus,
401 + port->id << 3, PCI_BASE_ADDRESS_0, 4, &val);
403 + /* Configure RC Credit */
404 + pcie_config_read(bus, port->id << 3, 0x73c, 4, &val);
405 + val &= ~(0x9fff) << 16;
406 + val |= 0x806c << 16;
407 + pcie_config_write(bus, port->id << 3, 0x73c, 4, val);
409 + /* Configure RC FTS number */
410 + pcie_config_read(bus, port->id << 3, 0x70c, 4, &val);
411 + val &= ~(0xff3) << 8;
413 + pcie_config_write(bus, port->id << 3, 0x70c, 4, val);
416 +static int mtk_pcie_preinit(struct mtk_pcie *pcie)
418 + struct mtk_pcie_port *port;
420 + struct pci_bus bus;
421 + struct pci_sys_data sys;
423 + memset(&bus, 0, sizeof(bus));
424 + memset(&sys, 0, sizeof(sys));
425 + bus.sysdata = (void *)&sys;
426 + sys.private_data = (void *)pcie;
428 + pcibios_min_io = 0;
429 + pcibios_min_mem = 0;
431 + /* The PHY on Port 2 is shared with USB */
432 + if (pcie->port[2].enable)
433 + regmap_update_bits(pcie->hifsys, HIFSYS_SYSCFG1,
434 + HIFSYS_SYSCFG1_PHY2_MASK, 0x0);
436 + /* PCIe RC Reset */
437 + mtk_foreach_port(pcie, port)
439 + reset_control_assert(port->rstc);
440 + usleep_range(1000, 2000);
441 + mtk_foreach_port(pcie, port)
443 + reset_control_deassert(port->rstc);
444 + usleep_range(1000, 2000);
446 + /* Configure PCIe PHY */
447 + mtk_foreach_port(pcie, port)
449 + mtk_pcie_configure_phy(pcie, port);
451 + /* PCIe EP reset */
453 + mtk_foreach_port(pcie, port)
455 + val |= mtk_pcie_port_data[port->id].perst_n;
456 + pcie_w32(pcie, pcie_r32(pcie, PCICFG) | val, PCICFG);
457 + usleep_range(1000, 2000);
458 + pcie_w32(pcie, pcie_r32(pcie, PCICFG) & ~val, PCICFG);
459 + usleep_range(1000, 2000);
462 + /* check the link status */
464 + mtk_foreach_port(pcie, port) {
465 + if (port->enable) {
466 + u32 base = mtk_pcie_port_data[port->id].base;
468 + if ((pcie_r32(pcie, base + PCIE_SISTAT) & 0x1))
471 + reset_control_assert(port->rstc);
475 + mtk_foreach_port(pcie, port)
477 + pcie->pcie_card_link++;
479 + if (!pcie->pcie_card_link)
482 + pcie_w32(pcie, pcie->mem_bus_addr, MEMBASE);
483 + pcie_w32(pcie, pcie->io_bus_addr, IOBASE);
485 + mtk_foreach_port(pcie, port) {
487 + u32 base = mtk_pcie_port_data[port->id].base;
488 + u32 inte = mtk_pcie_port_data[port->id].interrupt_en;
490 + pcie_m32(pcie, 0, inte, PCIENA);
491 + pcie_w32(pcie, 0x7fff0001, base + BAR0SETUP);
492 + pcie_w32(pcie, MEMORY_BASE, base + IMBASEBAR0);
493 + pcie_w32(pcie, 0x06040001, base + PCIE_CLASS);
497 + mtk_foreach_port(pcie, port)
499 + mtk_pcie_configure_rc(pcie, port, &bus);
504 +static int mtk_pcie_parse_dt(struct mtk_pcie *pcie)
506 + struct device_node *np = pcie->dev->of_node, *port;
507 + struct of_pci_range_parser parser;
508 + struct of_pci_range range;
509 + struct resource res;
512 + pcie->hifsys = syscon_regmap_lookup_by_phandle(np, "mediatek,hifsys");
513 + if (IS_ERR(pcie->hifsys)) {
514 + dev_err(pcie->dev, "missing \"mediatek,hifsys\" phandle\n");
515 + return PTR_ERR(pcie->hifsys);
518 + if (of_pci_range_parser_init(&parser, np)) {
519 + dev_err(pcie->dev, "missing \"ranges\" property\n");
523 + for_each_of_pci_range(&parser, &range) {
524 + err = of_pci_range_to_resource(&range, np, &res);
526 + dev_err(pcie->dev, "failed to read resource range\n");
530 + switch (res.flags & IORESOURCE_TYPE_BITS) {
531 + case IORESOURCE_IO:
532 + memcpy(&pcie->pio, &res, sizeof(res));
533 + pcie->pio.start = (resource_size_t)range.pci_addr;
534 + pcie->pio.end = (resource_size_t)
535 + (range.pci_addr + range.size - 1);
536 + pcie->io_bus_addr = (resource_size_t)range.cpu_addr;
539 + case IORESOURCE_MEM:
540 + if (res.flags & IORESOURCE_PREFETCH) {
541 + memcpy(&pcie->prefetch, &res, sizeof(res));
542 + pcie->prefetch.name = "prefetchable";
543 + pcie->prefetch.start =
544 + (resource_size_t)range.pci_addr;
545 + pcie->prefetch.end = (resource_size_t)
546 + (range.pci_addr + range.size - 1);
548 + memcpy(&pcie->mem, &res, sizeof(res));
549 + pcie->mem.name = "non-prefetchable";
550 + pcie->mem.start = (resource_size_t)
552 + pcie->prefetch.end = (resource_size_t)
553 + (range.pci_addr + range.size - 1);
554 + pcie->mem_bus_addr = (resource_size_t)
561 + err = of_pci_parse_bus_range(np, &pcie->busn);
563 + dev_err(pcie->dev, "failed to parse ranges property: %d\n",
565 + pcie->busn.name = np->name;
566 + pcie->busn.start = 0;
567 + pcie->busn.end = 0xff;
568 + pcie->busn.flags = IORESOURCE_BUS;
571 + /* parse root ports */
572 + for_each_child_of_node(np, port) {
573 + unsigned int index;
574 + char rst[] = "pcie0";
576 + err = of_pci_get_devfn(port);
578 + dev_err(pcie->dev, "failed to parse address: %d\n",
583 + index = PCI_SLOT(err);
584 + if (index > MAX_PORT_NUM) {
585 + dev_err(pcie->dev, "invalid port number: %d\n", index);
589 + pcie->port[index].id = index;
591 + if (!of_device_is_available(port))
595 + pcie->port[index].rstc = devm_reset_control_get(pcie->dev,
597 + if (!IS_ERR(pcie->port[index].rstc))
598 + pcie->port[index].enable = 1;
603 +static int mtk_pcie_get_resources(struct mtk_pcie *pcie)
605 + struct platform_device *pdev = to_platform_device(pcie->dev);
606 + struct mtk_pcie_port *port;
607 + struct resource *res;
609 + pcie->clk = devm_clk_get(&pdev->dev, "pcie");
610 + if (IS_ERR(pcie->clk)) {
611 + dev_err(&pdev->dev, "Failed to get pcie clk\n");
612 + return PTR_ERR(pcie->clk);
615 + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
616 + pcie->pcie_base = devm_ioremap_resource(&pdev->dev, res);
617 + if (IS_ERR(pcie->pcie_base)) {
618 + dev_err(&pdev->dev, "Failed to get pcie range\n");
619 + return PTR_ERR(pcie->pcie_base);
622 + mtk_foreach_port(pcie, port) {
625 + res = platform_get_resource(pdev, IORESOURCE_MEM, port->id + 1);
626 + port->phy_base = devm_ioremap_resource(&pdev->dev, res);
627 + if (IS_ERR(port->phy_base)) {
628 + dev_err(&pdev->dev, "Failed to get pcie phy%d range %p\n",
629 + port->id, port->phy_base);
630 + return PTR_ERR(port->phy_base);
632 + port->irq = platform_get_irq(pdev, port->id);
635 + return clk_prepare_enable(pcie->clk);
638 +static int mtk_pcie_probe(struct platform_device *pdev)
640 + struct mtk_pcie *pcie;
644 + pcie = devm_kzalloc(&pdev->dev, sizeof(*pcie), GFP_KERNEL);
648 + pcie->dev = &pdev->dev;
649 + ret = mtk_pcie_parse_dt(pcie);
653 + pm_runtime_enable(&pdev->dev);
654 + pm_runtime_get_sync(&pdev->dev);
656 + ret = mtk_pcie_get_resources(pcie);
658 + dev_err(&pdev->dev, "failed to request resources: %d\n", ret);
662 + ret = mtk_pcie_preinit(pcie);
666 + memset(&hw, 0, sizeof(hw));
667 + hw.nr_controllers = 1;
668 + hw.private_data = (void **)&pcie;
669 + hw.setup = mtk_pcie_setup;
670 + hw.map_irq = mtk_pcie_map_irq;
671 + hw.scan = mtk_pcie_scan_bus;
673 + pci_common_init_dev(pcie->dev, &hw);
674 + platform_set_drvdata(pdev, pcie);
679 + clk_disable_unprepare(pcie->clk);
680 + pm_runtime_put_sync(&pdev->dev);
681 + pm_runtime_disable(&pdev->dev);
686 +static const struct of_device_id mtk_pcie_ids[] = {
687 + { .compatible = "mediatek,mt2701-pcie" },
688 + { .compatible = "mediatek,mt7623-pcie" },
691 +MODULE_DEVICE_TABLE(of, mtk_pcie_ids);
693 +static struct platform_driver mtk_pcie_driver = {
694 + .probe = mtk_pcie_probe,
696 + .name = "mediatek-pcie",
697 + .owner = THIS_MODULE,
698 + .of_match_table = of_match_ptr(mtk_pcie_ids),
702 +static int __init mtk_pcie_init(void)
704 + return platform_driver_register(&mtk_pcie_driver);
707 +module_init(mtk_pcie_init);