1 From b79b0519fb67c22cbed341c5e9dca5ad0aa4d15c Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Wed, 2 Mar 2016 07:18:52 +0100
4 Subject: [PATCH 48/81] net-next: mediatek: document MediaTek SoC ethernet
7 This adds the binding documentation for the MediaTek Ethernet
10 Signed-off-by: John Crispin <blogic@openwrt.org>
11 Acked-by: Rob Herring <robh@kernel.org>
12 Cc: devicetree@vger.kernel.org
14 .../devicetree/bindings/net/mediatek-net.txt | 77 ++++++++++++++++++++
15 1 file changed, 77 insertions(+)
16 create mode 100644 Documentation/devicetree/bindings/net/mediatek-net.txt
18 diff --git a/Documentation/devicetree/bindings/net/mediatek-net.txt b/Documentation/devicetree/bindings/net/mediatek-net.txt
20 index 0000000..5ca7929
22 +++ b/Documentation/devicetree/bindings/net/mediatek-net.txt
24 +MediaTek Frame Engine Ethernet controller
25 +=========================================
27 +The frame engine ethernet controller can be found on MediaTek SoCs. These SoCs
28 +have dual GMAC each represented by a child node..
30 +* Ethernet controller node
33 +- compatible: Should be "mediatek,mt7623-eth"
34 +- reg: Address and length of the register set for the device
35 +- interrupts: Should contain the frame engines interrupt
36 +- clocks: the clock used by the core
37 +- clock-names: the names of the clock listed in the clocks property. These are
38 + "ethif", "esw", "gp2", "gp1"
39 +- power-domains: phandle to the power domain that the ethernet is part of
40 +- resets: Should contain a phandle to the ethsys reset signal
41 +- reset-names: Should contain the reset signal name "eth"
42 +- mediatek,ethsys: phandle to the syscon node that handles the port setup
43 +- mediatek,pctl: phandle to the syscon node that handles the ports slew rate
47 +- interrupt-parent: Should be the phandle for the interrupt controller
48 + that services interrupts for this device
54 +- compatible: Should be "mediatek,eth-mac"
55 +- reg: The number of the MAC
56 +- phy-handle: see ethernet.txt file in the same directory.
60 +eth: ethernet@1b100000 {
61 + compatible = "mediatek,mt7623-eth";
62 + reg = <0 0x1b100000 0 0x20000>;
63 + clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
64 + <ðsys CLK_ETHSYS_ESW>,
65 + <ðsys CLK_ETHSYS_GP2>,
66 + <ðsys CLK_ETHSYS_GP1>;
67 + clock-names = "ethif", "esw", "gp2", "gp1";
68 + interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_LOW>;
69 + power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
70 + resets = <ðsys MT2701_ETHSYS_ETH_RST>;
71 + reset-names = "eth";
72 + mediatek,ethsys = <ðsys>;
73 + mediatek,pctl = <&syscfg_pctl_a>;
74 + #address-cells = <1>;
78 + compatible = "mediatek,eth-mac";
80 + phy-handle = <&phy0>;
84 + compatible = "mediatek,eth-mac";
86 + phy-handle = <&phy1>;
90 + phy0: ethernet-phy@0 {
95 + phy1: ethernet-phy@1 {