1 From 1387d4f0ebf4b48c09f2ea0d27a02936c3fa0010 Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Thu, 31 Mar 2016 02:26:37 +0200
4 Subject: [PATCH 054/102] clk: mediatek: Export CPU mux clocks for CPU
7 This patch adds CPU mux clocks which are used by Mediatek cpufreq driver
8 for intermediate clock source switching.
10 Signed-off-by: Pi-Cheng Chen <pi-cheng.chen@linaro.org>
12 drivers/clk/mediatek/Makefile | 2 +-
13 drivers/clk/mediatek/clk-cpumux.c | 127 ++++++++++++++++++++++++++++++++
14 drivers/clk/mediatek/clk-cpumux.h | 22 ++++++
15 drivers/clk/mediatek/clk-mt2701.c | 8 ++
16 drivers/clk/mediatek/clk-mt8173.c | 23 ++++++
17 include/dt-bindings/clock/mt2701-clk.h | 3 +-
18 include/dt-bindings/clock/mt8173-clk.h | 4 +-
19 7 files changed, 186 insertions(+), 3 deletions(-)
20 create mode 100644 drivers/clk/mediatek/clk-cpumux.c
21 create mode 100644 drivers/clk/mediatek/clk-cpumux.h
23 --- a/drivers/clk/mediatek/Makefile
24 +++ b/drivers/clk/mediatek/Makefile
26 -obj-$(CONFIG_COMMON_CLK_MEDIATEK) += clk-mtk.o clk-pll.o clk-gate.o clk-apmixed.o
27 +obj-$(CONFIG_COMMON_CLK_MEDIATEK) += clk-mtk.o clk-pll.o clk-gate.o clk-apmixed.o clk-cpumux.o
28 obj-$(CONFIG_RESET_CONTROLLER) += reset.o
29 obj-$(CONFIG_COMMON_CLK_MT2701) += clk-mt2701.o
30 obj-$(CONFIG_COMMON_CLK_MT8135) += clk-mt8135.o
32 +++ b/drivers/clk/mediatek/clk-cpumux.c
35 + * Copyright (c) 2015 Linaro Ltd.
36 + * Author: Pi-Cheng Chen <pi-cheng.chen@linaro.org>
38 + * This program is free software; you can redistribute it and/or modify
39 + * it under the terms of the GNU General Public License version 2 as
40 + * published by the Free Software Foundation.
42 + * This program is distributed in the hope that it will be useful,
43 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
44 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
45 + * GNU General Public License for more details.
48 +#include <linux/clk-provider.h>
49 +#include <linux/mfd/syscon.h>
50 +#include <linux/slab.h>
53 +#include "clk-cpumux.h"
55 +struct mtk_clk_cpumux {
57 + struct regmap *regmap;
63 +static inline struct mtk_clk_cpumux *to_clk_mux(struct clk_hw *_hw)
65 + return container_of(_hw, struct mtk_clk_cpumux, hw);
68 +static u8 clk_cpumux_get_parent(struct clk_hw *hw)
70 + struct mtk_clk_cpumux *mux = to_clk_mux(hw);
71 + int num_parents = clk_hw_get_num_parents(hw);
74 + regmap_read(mux->regmap, mux->reg, &val);
79 + if (val >= num_parents)
85 +static int clk_cpumux_set_parent(struct clk_hw *hw, u8 index)
87 + struct mtk_clk_cpumux *mux = to_clk_mux(hw);
90 + val = index << mux->shift;
91 + mask = mux->mask << mux->shift;
93 + return regmap_update_bits(mux->regmap, mux->reg, mask, val);
96 +static const struct clk_ops clk_cpumux_ops = {
97 + .get_parent = clk_cpumux_get_parent,
98 + .set_parent = clk_cpumux_set_parent,
101 +static struct clk __init *mtk_clk_register_cpumux(const struct mtk_composite *mux,
102 + struct regmap *regmap)
104 + struct mtk_clk_cpumux *cpumux;
106 + struct clk_init_data init;
108 + cpumux = kzalloc(sizeof(*cpumux), GFP_KERNEL);
110 + return ERR_PTR(-ENOMEM);
112 + init.name = mux->name;
113 + init.ops = &clk_cpumux_ops;
114 + init.parent_names = mux->parent_names;
115 + init.num_parents = mux->num_parents;
116 + init.flags = mux->flags;
118 + cpumux->reg = mux->mux_reg;
119 + cpumux->shift = mux->mux_shift;
120 + cpumux->mask = BIT(mux->mux_width) - 1;
121 + cpumux->regmap = regmap;
122 + cpumux->hw.init = &init;
124 + clk = clk_register(NULL, &cpumux->hw);
131 +int __init mtk_clk_register_cpumuxes(struct device_node *node,
132 + const struct mtk_composite *clks, int num,
133 + struct clk_onecell_data *clk_data)
137 + struct regmap *regmap;
139 + regmap = syscon_node_to_regmap(node);
140 + if (IS_ERR(regmap)) {
141 + pr_err("Cannot find regmap for %s: %ld\n", node->full_name,
143 + return PTR_ERR(regmap);
146 + for (i = 0; i < num; i++) {
147 + const struct mtk_composite *mux = &clks[i];
149 + clk = mtk_clk_register_cpumux(mux, regmap);
151 + pr_err("Failed to register clk %s: %ld\n",
152 + mux->name, PTR_ERR(clk));
156 + clk_data->clks[mux->id] = clk;
162 +++ b/drivers/clk/mediatek/clk-cpumux.h
165 + * Copyright (c) 2015 Linaro Ltd.
166 + * Author: Pi-Cheng Chen <pi-cheng.chen@linaro.org>
168 + * This program is free software; you can redistribute it and/or modify
169 + * it under the terms of the GNU General Public License version 2 as
170 + * published by the Free Software Foundation.
172 + * This program is distributed in the hope that it will be useful,
173 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
174 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
175 + * GNU General Public License for more details.
178 +#ifndef __DRV_CLK_CPUMUX_H
179 +#define __DRV_CLK_CPUMUX_H
181 +int mtk_clk_register_cpumuxes(struct device_node *node,
182 + const struct mtk_composite *clks, int num,
183 + struct clk_onecell_data *clk_data);
185 +#endif /* __DRV_CLK_CPUMUX_H */
186 --- a/drivers/clk/mediatek/clk-mt2701.c
187 +++ b/drivers/clk/mediatek/clk-mt2701.c
191 #include "clk-gate.h"
192 +#include "clk-cpumux.h"
194 #include <dt-bindings/clock/mt2701-clk.h>
196 @@ -465,6 +466,10 @@ static const char * const cpu_parents[]
200 +static const struct mtk_composite cpu_muxes[] __initconst = {
201 + MUX(CLK_INFRA_CPUSEL, "infra_cpu_sel", cpu_parents, 0x0000, 2, 2),
204 static const struct mtk_composite top_muxes[] __initconst = {
205 MUX_GATE(CLK_TOP_AXI_SEL, "axi_sel", axi_parents,
206 0x0040, 0, 3, INVALID_MUX_GATE_BIT),
207 @@ -677,6 +682,9 @@ static void __init mtk_infrasys_init(str
208 mtk_clk_register_factors(infra_fixed_divs, ARRAY_SIZE(infra_fixed_divs),
211 + mtk_clk_register_cpumuxes(node, cpu_muxes, ARRAY_SIZE(cpu_muxes),
214 r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
216 pr_err("%s(): could not register clock provider: %d\n",
217 --- a/drivers/clk/mediatek/clk-mt8173.c
218 +++ b/drivers/clk/mediatek/clk-mt8173.c
222 #include "clk-gate.h"
223 +#include "clk-cpumux.h"
225 #include <dt-bindings/clock/mt8173-clk.h>
227 @@ -526,6 +527,25 @@ static const char * const i2s3_b_ck_pare
231 +static const char * const ca53_parents[] __initconst = {
238 +static const char * const ca57_parents[] __initconst = {
245 +static const struct mtk_composite cpu_muxes[] __initconst = {
246 + MUX(CLK_INFRA_CA53SEL, "infra_ca53_sel", ca53_parents, 0x0000, 0, 2),
247 + MUX(CLK_INFRA_CA57SEL, "infra_ca57_sel", ca57_parents, 0x0000, 2, 2),
250 static const struct mtk_composite top_muxes[] __initconst = {
252 MUX(CLK_TOP_AXI_SEL, "axi_sel", axi_parents, 0x0040, 0, 3),
253 @@ -945,6 +965,9 @@ static void __init mtk_infrasys_init(str
255 mtk_clk_register_factors(infra_divs, ARRAY_SIZE(infra_divs), clk_data);
257 + mtk_clk_register_cpumuxes(node, cpu_muxes, ARRAY_SIZE(cpu_muxes),
260 r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
262 pr_err("%s(): could not register clock provider: %d\n",
263 --- a/include/dt-bindings/clock/mt2701-clk.h
264 +++ b/include/dt-bindings/clock/mt2701-clk.h
266 #define CLK_INFRA_PMICWRAP 17
267 #define CLK_INFRA_DDCCI 18
268 #define CLK_INFRA_CLK_13M 19
269 -#define CLK_INFRA_NR 20
270 +#define CLK_INFRA_CPUSEL 20
271 +#define CLK_INFRA_NR 21
275 --- a/include/dt-bindings/clock/mt8173-clk.h
276 +++ b/include/dt-bindings/clock/mt8173-clk.h
278 #define CLK_INFRA_PMICSPI 10
279 #define CLK_INFRA_PMICWRAP 11
280 #define CLK_INFRA_CLK_13M 12
281 -#define CLK_INFRA_NR_CLK 13
282 +#define CLK_INFRA_CA53SEL 13
283 +#define CLK_INFRA_CA57SEL 14
284 +#define CLK_INFRA_NR_CLK 15