1 From 5e1c00983efeca4522ac2e8574e3e3997d26a203 Mon Sep 17 00:00:00 2001
2 From: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
3 Date: Fri, 29 Apr 2016 12:17:21 -0400
4 Subject: [PATCH 074/102] mtd: mediatek: device tree docs for MTK Smart Device
7 This patch adds documentation support for Smart Device Gen1 type of
10 Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
12 Documentation/devicetree/bindings/mtd/mtk-nand.txt | 161 ++++++++++++++++++++
13 1 file changed, 161 insertions(+)
14 create mode 100644 Documentation/devicetree/bindings/mtd/mtk-nand.txt
17 +++ b/Documentation/devicetree/bindings/mtd/mtk-nand.txt
19 +MTK SoCs NAND FLASH controller (NFC) DT binding
21 +This file documents the device tree bindings for MTK SoCs NAND controllers.
22 +The functional split of the controller requires two drivers to operate:
23 +the nand controller interface driver and the ECC engine driver.
25 +The hardware description for both devices must be captured as device
28 +1) NFC NAND Controller Interface (NFI):
29 +=======================================
31 +The first part of NFC is NAND Controller Interface (NFI) HW.
32 +Required NFI properties:
33 +- compatible: Should be "mediatek,mtxxxx-nfc".
34 +- reg: Base physical address and size of NFI.
35 +- interrupts: Interrupts of NFI.
36 +- clocks: NFI required clocks.
37 +- clock-names: NFI clocks internal name.
38 +- status: Disabled default. Then set "okay" by platform.
39 +- ecc-engine: Required ECC Engine node.
40 +- #address-cells: NAND chip index, should be 1.
41 +- #size-cells: Should be 0.
45 + nandc: nfi@1100d000 {
46 + compatible = "mediatek,mt2701-nfc";
47 + reg = <0 0x1100d000 0 0x1000>;
48 + interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_LOW>;
49 + clocks = <&pericfg CLK_PERI_NFI>,
50 + <&pericfg CLK_PERI_NFI_PAD>;
51 + clock-names = "nfi_clk", "pad_clk";
52 + status = "disabled";
53 + ecc-engine = <&bch>;
54 + #address-cells = <1>;
58 +Platform related properties, should be set in {platform_name}.dts:
59 +- children nodes: NAND chips.
61 +Children nodes properties:
62 +- reg: Chip Select Signal, default 0.
63 + Set as reg = <0>, <1> when need 2 CS.
65 +- nand-on-flash-bbt: Store BBT on NAND Flash.
66 +- nand-ecc-mode: the NAND ecc mode (check driver for supported modes)
67 +- nand-ecc-step-size: Number of data bytes covered by a single ECC step.
68 + The controller only supports 512 and 1024.
69 + For large page NANDs ther recommended value is 1024.
70 +- nand-ecc-strength: Number of bits to correct per ECC step.
71 + The valid values that the controller supports are: 4, 6,
72 + 8, 10, 12, 14, 16, 18, 20, 22, 24, 28, 32, 36, 40, 44,
74 + The strength should be calculated as follows:
75 + E = (S - F) * 8 / 14
77 + E :nand-ecc-strength;
78 + S :spare size per sector;
79 + F : FDM size, should be in the range [1,8].
80 + It is used to store free oob data.
83 + Q :nand-ecc-step-size
84 + If the result does not match any one of the listed
85 + choices above, please select the smaller valid value from
87 + (otherwise the driver will do the clamping at runtime).
88 +- vmch-supply: NAND power supply.
89 +- pinctrl-names: Default NAND pin GPIO setting name.
90 +- pinctrl-0: GPIO setting node.
94 + nand_pins_default: nanddefault {
96 + pinmux = <MT2701_PIN_111_MSDC0_DAT7__FUNC_NLD7>,
97 + <MT2701_PIN_112_MSDC0_DAT6__FUNC_NLD6>,
98 + <MT2701_PIN_114_MSDC0_DAT4__FUNC_NLD4>,
99 + <MT2701_PIN_118_MSDC0_DAT3__FUNC_NLD3>,
100 + <MT2701_PIN_121_MSDC0_DAT0__FUNC_NLD0>,
101 + <MT2701_PIN_120_MSDC0_DAT1__FUNC_NLD1>,
102 + <MT2701_PIN_113_MSDC0_DAT5__FUNC_NLD5>,
103 + <MT2701_PIN_115_MSDC0_RSTB__FUNC_NLD8>,
104 + <MT2701_PIN_119_MSDC0_DAT2__FUNC_NLD2>;
106 + drive-strength = <MTK_DRIVE_8mA>;
111 + pinmux = <MT2701_PIN_117_MSDC0_CLK__FUNC_NWEB>;
112 + drive-strength = <MTK_DRIVE_8mA>;
113 + bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
117 + pinmux = <MT2701_PIN_116_MSDC0_CMD__FUNC_NALE>;
118 + drive-strength = <MTK_DRIVE_8mA>;
119 + bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
126 + pinctrl-names = "default";
127 + pinctrl-0 = <&nand_pins_default>;
131 + nand-ecc-mode = "hw";
132 + nand-ecc-strength = <24>;
133 + nand-ecc-step-size = <1024>;
137 +NAND chip optional subnodes:
138 +- Partitions, see Documentation/devicetree/bindings/mtd/partition.txt
143 + compatible = "fixed-partitions";
144 + #address-cells = <1>;
150 + reg = <0x00000000 0x00400000>;
152 + android@0x00400000 {
154 + reg = <0x00400000 0x12c00000>;
162 +Required BCH properties:
163 +- compatible: Should be "mediatek,mtxxxx-ecc".
164 +- reg: Base physical address and size of ECC.
165 +- interrupts: Interrupts of ECC.
166 +- clocks: ECC required clocks.
167 +- clock-names: ECC clocks internal name.
168 +- status: Disabled default. Then set "okay" by platform.
172 + bch: ecc@1100e000 {
173 + compatible = "mediatek,mt2701-ecc";
174 + reg = <0 0x1100e000 0 0x1000>;
175 + interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_LOW>;
176 + clocks = <&pericfg CLK_PERI_NFI_ECC>;
177 + clock-names = "nfiecc_clk";
178 + status = "disabled";