1 From de18239fc971cfc17c53320c66ae64dd5ade032d Mon Sep 17 00:00:00 2001
2 From: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
3 Date: Fri, 29 Apr 2016 12:17:22 -0400
4 Subject: [PATCH 075/102] mtd: mediatek: driver for MTK Smart Device Gen1 NAND
6 This patch adds support for mediatek's SDG1 NFC nand controller
9 Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
11 drivers/mtd/nand/Kconfig | 7 +
12 drivers/mtd/nand/Makefile | 1 +
13 drivers/mtd/nand/mtk_ecc.c | 527 ++++++++++++++++
14 drivers/mtd/nand/mtk_ecc.h | 53 ++
15 drivers/mtd/nand/mtk_nand.c | 1432 +++++++++++++++++++++++++++++++++++++++++++
16 5 files changed, 2020 insertions(+)
17 create mode 100644 drivers/mtd/nand/mtk_ecc.c
18 create mode 100644 drivers/mtd/nand/mtk_ecc.h
19 create mode 100644 drivers/mtd/nand/mtk_nand.c
21 diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
22 index f05e0e9..3c26e89 100644
23 --- a/drivers/mtd/nand/Kconfig
24 +++ b/drivers/mtd/nand/Kconfig
25 @@ -563,4 +563,11 @@ config MTD_NAND_QCOM
26 Enables support for NAND flash chips on SoCs containing the EBI2 NAND
27 controller. This controller is found on IPQ806x SoC.
30 + tristate "Support for NAND controller on MTK SoCs"
33 + Enables support for NAND controller on MTK SoCs.
34 + This controller is found on mt27xx, mt81xx, mt65xx SoCs.
37 diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
38 index f553353..cafde6f 100644
39 --- a/drivers/mtd/nand/Makefile
40 +++ b/drivers/mtd/nand/Makefile
41 @@ -57,5 +57,6 @@ obj-$(CONFIG_MTD_NAND_SUNXI) += sunxi_nand.o
42 obj-$(CONFIG_MTD_NAND_HISI504) += hisi504_nand.o
43 obj-$(CONFIG_MTD_NAND_BRCMNAND) += brcmnand/
44 obj-$(CONFIG_MTD_NAND_QCOM) += qcom_nandc.o
45 +obj-$(CONFIG_MTD_NAND_MTK) += mtk_nand.o mtk_ecc.o
47 nand-objs := nand_base.o nand_bbt.o nand_timings.o
48 diff --git a/drivers/mtd/nand/mtk_ecc.c b/drivers/mtd/nand/mtk_ecc.c
50 index 0000000..28769f1
52 +++ b/drivers/mtd/nand/mtk_ecc.c
55 + * MTK ECC controller driver.
56 + * Copyright (C) 2016 MediaTek Inc.
57 + * Authors: Xiaolei Li <xiaolei.li@mediatek.com>
58 + * Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
60 + * This program is free software; you can redistribute it and/or modify
61 + * it under the terms of the GNU General Public License version 2 as
62 + * published by the Free Software Foundation.
64 + * This program is distributed in the hope that it will be useful,
65 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
66 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
67 + * GNU General Public License for more details.
70 +#include <linux/platform_device.h>
71 +#include <linux/dma-mapping.h>
72 +#include <linux/interrupt.h>
73 +#include <linux/clk.h>
74 +#include <linux/module.h>
75 +#include <linux/iopoll.h>
76 +#include <linux/of.h>
77 +#include <linux/of_platform.h>
78 +#include <linux/semaphore.h>
82 +#define ECC_ENCCON (0x00)
85 +#define ECC_ENCCNFG (0x04)
86 +#define ECC_CNFG_4BIT (0)
87 +#define ECC_CNFG_6BIT (1)
88 +#define ECC_CNFG_8BIT (2)
89 +#define ECC_CNFG_10BIT (3)
90 +#define ECC_CNFG_12BIT (4)
91 +#define ECC_CNFG_14BIT (5)
92 +#define ECC_CNFG_16BIT (6)
93 +#define ECC_CNFG_18BIT (7)
94 +#define ECC_CNFG_20BIT (8)
95 +#define ECC_CNFG_22BIT (9)
96 +#define ECC_CNFG_24BIT (0xa)
97 +#define ECC_CNFG_28BIT (0xb)
98 +#define ECC_CNFG_32BIT (0xc)
99 +#define ECC_CNFG_36BIT (0xd)
100 +#define ECC_CNFG_40BIT (0xe)
101 +#define ECC_CNFG_44BIT (0xf)
102 +#define ECC_CNFG_48BIT (0x10)
103 +#define ECC_CNFG_52BIT (0x11)
104 +#define ECC_CNFG_56BIT (0x12)
105 +#define ECC_CNFG_60BIT (0x13)
106 +#define ECC_MODE_SHIFT (5)
107 +#define ECC_MS_SHIFT (16)
108 +#define ECC_ENCDIADDR (0x08)
109 +#define ECC_ENCIDLE (0x0C)
110 +#define ENC_IDLE BIT(0)
111 +#define ECC_ENCPAR(x) (0x10 + (x) * sizeof(u32))
112 +#define ECC_ENCIRQ_EN (0x80)
113 +#define ENC_IRQEN BIT(0)
114 +#define ECC_ENCIRQ_STA (0x84)
115 +#define ECC_DECCON (0x100)
118 +#define ECC_DECCNFG (0x104)
119 +#define DEC_EMPTY_EN BIT(31)
120 +#define DEC_CNFG_CORRECT (0x3 << 12)
121 +#define ECC_DECIDLE (0x10C)
122 +#define DEC_IDLE BIT(0)
123 +#define ECC_DECENUM0 (0x114)
124 +#define ERR_MASK (0x3f)
125 +#define ECC_DECDONE (0x124)
126 +#define ECC_DECIRQ_EN (0x200)
127 +#define DEC_IRQEN BIT(0)
128 +#define ECC_DECIRQ_STA (0x204)
130 +#define ECC_TIMEOUT (500000)
132 +#define ECC_IDLE_REG(x) ((x) == ECC_ENC ? ECC_ENCIDLE : ECC_DECIDLE)
133 +#define ECC_IDLE_MASK(x) ((x) == ECC_ENC ? ENC_IDLE : DEC_IDLE)
134 +#define ECC_IRQ_REG(x) ((x) == ECC_ENC ? ECC_ENCIRQ_EN : ECC_DECIRQ_EN)
135 +#define ECC_IRQ_EN(x) ((x) == ECC_ENC ? ENC_IRQEN : DEC_IRQEN)
136 +#define ECC_CTL_REG(x) ((x) == ECC_ENC ? ECC_ENCCON : ECC_DECCON)
137 +#define ECC_CODEC_ENABLE(x) ((x) == ECC_ENC ? ENC_EN : DEC_EN)
138 +#define ECC_CODEC_DISABLE(x) ((x) == ECC_ENC ? ENC_DE : DEC_DE)
141 + struct device *dev;
142 + void __iomem *regs;
145 + struct completion done;
146 + struct semaphore sem;
150 +static inline void mtk_ecc_codec_wait_idle(struct mtk_ecc *ecc,
151 + enum mtk_ecc_codec codec)
153 + struct device *dev = ecc->dev;
157 + ret = readl_poll_timeout_atomic(ecc->regs + ECC_IDLE_REG(codec), val,
158 + val & ECC_IDLE_MASK(codec),
161 + dev_warn(dev, "%s NOT idle\n",
162 + codec == ECC_ENC ? "encoder" : "decoder");
165 +static irqreturn_t mtk_ecc_irq(int irq, void *id)
167 + struct mtk_ecc *ecc = id;
168 + enum mtk_ecc_codec codec;
171 + dec = readw(ecc->regs + ECC_DECIRQ_STA) & DEC_IRQEN;
174 + dec = readw(ecc->regs + ECC_DECDONE);
175 + if (dec & ecc->sec_mask) {
177 + complete(&ecc->done);
179 + return IRQ_HANDLED;
181 + enc = readl(ecc->regs + ECC_ENCIRQ_STA) & ENC_IRQEN;
184 + complete(&ecc->done);
189 + writel(0, ecc->regs + ECC_IRQ_REG(codec));
191 + return IRQ_HANDLED;
194 +static void mtk_ecc_config(struct mtk_ecc *ecc, struct mtk_ecc_config *config)
196 + u32 ecc_bit = ECC_CNFG_4BIT, dec_sz, enc_sz;
199 + switch (config->strength) {
201 + ecc_bit = ECC_CNFG_4BIT;
204 + ecc_bit = ECC_CNFG_6BIT;
207 + ecc_bit = ECC_CNFG_8BIT;
210 + ecc_bit = ECC_CNFG_10BIT;
213 + ecc_bit = ECC_CNFG_12BIT;
216 + ecc_bit = ECC_CNFG_14BIT;
219 + ecc_bit = ECC_CNFG_16BIT;
222 + ecc_bit = ECC_CNFG_18BIT;
225 + ecc_bit = ECC_CNFG_20BIT;
228 + ecc_bit = ECC_CNFG_22BIT;
231 + ecc_bit = ECC_CNFG_24BIT;
234 + ecc_bit = ECC_CNFG_28BIT;
237 + ecc_bit = ECC_CNFG_32BIT;
240 + ecc_bit = ECC_CNFG_36BIT;
243 + ecc_bit = ECC_CNFG_40BIT;
246 + ecc_bit = ECC_CNFG_44BIT;
249 + ecc_bit = ECC_CNFG_48BIT;
252 + ecc_bit = ECC_CNFG_52BIT;
255 + ecc_bit = ECC_CNFG_56BIT;
258 + ecc_bit = ECC_CNFG_60BIT;
261 + dev_err(ecc->dev, "invalid strength %d\n", config->strength);
264 + if (config->codec == ECC_ENC) {
265 + /* configure ECC encoder (in bits) */
266 + enc_sz = config->enc_len << 3;
268 + reg = ecc_bit | (config->ecc_mode << ECC_MODE_SHIFT);
269 + reg |= (enc_sz << ECC_MS_SHIFT);
270 + writel(reg, ecc->regs + ECC_ENCCNFG);
272 + if (config->ecc_mode != ECC_NFI_MODE)
273 + writel(lower_32_bits(config->addr),
274 + ecc->regs + ECC_ENCDIADDR);
277 + /* configure ECC decoder (in bits) */
278 + dec_sz = config->dec_len;
280 + reg = ecc_bit | (config->ecc_mode << ECC_MODE_SHIFT);
281 + reg |= (dec_sz << ECC_MS_SHIFT) | DEC_CNFG_CORRECT;
282 + reg |= DEC_EMPTY_EN;
283 + writel(reg, ecc->regs + ECC_DECCNFG);
285 + if (config->sec_mask)
286 + ecc->sec_mask = 1 << (config->sec_mask - 1);
290 +void mtk_ecc_get_stats(struct mtk_ecc *ecc, struct mtk_ecc_stats *stats,
293 + u32 offset, i, err;
296 + stats->corrected = 0;
299 + for (i = 0; i < sectors; i++) {
300 + offset = (i >> 2) << 2;
301 + err = readl(ecc->regs + ECC_DECENUM0 + offset);
302 + err = err >> ((i % 4) * 8);
304 + if (err == ERR_MASK) {
305 + /* uncorrectable errors */
310 + stats->corrected += err;
311 + bitflips = max_t(u32, bitflips, err);
314 + stats->bitflips = bitflips;
316 +EXPORT_SYMBOL(mtk_ecc_get_stats);
318 +void mtk_ecc_release(struct mtk_ecc *ecc)
320 + clk_disable_unprepare(ecc->clk);
321 + put_device(ecc->dev);
323 +EXPORT_SYMBOL(mtk_ecc_release);
325 +static struct mtk_ecc *mtk_ecc_get(struct device_node *np)
327 + struct platform_device *pdev;
328 + struct mtk_ecc *ecc;
330 + pdev = of_find_device_by_node(np);
331 + if (!pdev || !platform_get_drvdata(pdev))
332 + return ERR_PTR(-EPROBE_DEFER);
334 + get_device(&pdev->dev);
335 + ecc = platform_get_drvdata(pdev);
336 + clk_prepare_enable(ecc->clk);
337 + mtk_ecc_hw_init(ecc);
342 +struct mtk_ecc *of_mtk_ecc_get(struct device_node *of_node)
344 + struct mtk_ecc *ecc = NULL;
345 + struct device_node *np;
347 + np = of_parse_phandle(of_node, "ecc-engine", 0);
349 + ecc = mtk_ecc_get(np);
355 +EXPORT_SYMBOL(of_mtk_ecc_get);
357 +int mtk_ecc_enable(struct mtk_ecc *ecc, struct mtk_ecc_config *config)
359 + enum mtk_ecc_codec codec = config->codec;
362 + ret = down_interruptible(&ecc->sem);
364 + dev_err(ecc->dev, "interrupted when attempting to lock\n");
368 + mtk_ecc_codec_wait_idle(ecc, codec);
369 + mtk_ecc_config(ecc, config);
370 + writew(ECC_CODEC_ENABLE(codec), ecc->regs + ECC_CTL_REG(codec));
372 + init_completion(&ecc->done);
373 + writew(ECC_IRQ_EN(codec), ecc->regs + ECC_IRQ_REG(codec));
377 +EXPORT_SYMBOL(mtk_ecc_enable);
379 +void mtk_ecc_disable(struct mtk_ecc *ecc, struct mtk_ecc_config *config)
381 + enum mtk_ecc_codec codec = config->codec;
383 + mtk_ecc_codec_wait_idle(ecc, codec);
384 + writew(0, ecc->regs + ECC_IRQ_REG(codec));
385 + writew(ECC_CODEC_DISABLE(codec), ecc->regs + ECC_CTL_REG(codec));
388 +EXPORT_SYMBOL(mtk_ecc_disable);
390 +int mtk_ecc_wait_irq_done(struct mtk_ecc *ecc, enum mtk_ecc_codec codec)
394 + ret = wait_for_completion_timeout(&ecc->done, msecs_to_jiffies(500));
396 + dev_err(ecc->dev, "%s timeout - interrupt did not arrive)\n",
397 + (codec == ECC_ENC) ? "encoder" : "decoder");
403 +EXPORT_SYMBOL(mtk_ecc_wait_irq_done);
405 +int mtk_ecc_encode_non_nfi_mode(struct mtk_ecc *ecc,
406 + struct mtk_ecc_config *config, u8 *data, u32 bytes)
412 + addr = dma_map_single(ecc->dev, data, bytes, DMA_TO_DEVICE);
413 + ret = dma_mapping_error(ecc->dev, addr);
415 + dev_err(ecc->dev, "dma mapping error\n");
419 + config->codec = ECC_ENC;
420 + config->addr = addr;
421 + ret = mtk_ecc_enable(ecc, config);
423 + dma_unmap_single(ecc->dev, addr, bytes, DMA_TO_DEVICE);
427 + ret = mtk_ecc_wait_irq_done(ecc, ECC_ENC);
431 + mtk_ecc_codec_wait_idle(ecc, ECC_ENC);
433 + /* Program ECC bytes to OOB: per sector oob = FDM + ECC + SPARE */
434 + len = (config->strength * ECC_PARITY_BITS + 7) >> 3;
435 + p = (u32 *) (data + bytes);
437 + /* write the parity bytes generated by the ECC back to the OOB region */
438 + for (i = 0; i < len; i++)
439 + p[i] = readl(ecc->regs + ECC_ENCPAR(i));
442 + dma_unmap_single(ecc->dev, addr, bytes, DMA_TO_DEVICE);
443 + mtk_ecc_disable(ecc, config);
447 +EXPORT_SYMBOL(mtk_ecc_encode_non_nfi_mode);
449 +void mtk_ecc_hw_init(struct mtk_ecc *ecc)
451 + mtk_ecc_codec_wait_idle(ecc, ECC_ENC);
452 + writew(ENC_DE, ecc->regs + ECC_ENCCON);
454 + mtk_ecc_codec_wait_idle(ecc, ECC_DEC);
455 + writel(DEC_DE, ecc->regs + ECC_DECCON);
458 +void mtk_ecc_update_strength(u32 *p)
460 + u32 ecc[] = {4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 28, 32, 36,
461 + 40, 44, 48, 52, 56, 60};
464 + for (i = 0; i < ARRAY_SIZE(ecc); i++) {
465 + if (*p <= ecc[i]) {
468 + else if (*p != ecc[i])
474 + *p = ecc[ARRAY_SIZE(ecc) - 1];
476 +EXPORT_SYMBOL(mtk_ecc_update_strength);
478 +static int mtk_ecc_probe(struct platform_device *pdev)
480 + struct device *dev = &pdev->dev;
481 + struct mtk_ecc *ecc;
482 + struct resource *res;
485 + ecc = devm_kzalloc(dev, sizeof(*ecc), GFP_KERNEL);
489 + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
490 + ecc->regs = devm_ioremap_resource(dev, res);
491 + if (IS_ERR(ecc->regs)) {
492 + dev_err(dev, "failed to map regs: %ld\n", PTR_ERR(ecc->regs));
493 + return PTR_ERR(ecc->regs);
496 + ecc->clk = devm_clk_get(dev, NULL);
497 + if (IS_ERR(ecc->clk)) {
498 + dev_err(dev, "failed to get clock: %ld\n", PTR_ERR(ecc->clk));
499 + return PTR_ERR(ecc->clk);
502 + irq = platform_get_irq(pdev, 0);
504 + dev_err(dev, "failed to get irq\n");
508 + ret = dma_set_mask(dev, DMA_BIT_MASK(32));
510 + dev_err(dev, "failed to set DMA mask\n");
514 + ret = devm_request_irq(dev, irq, mtk_ecc_irq, 0x0, "mtk-ecc", ecc);
516 + dev_err(dev, "failed to request irq\n");
521 + sema_init(&ecc->sem, 1);
522 + platform_set_drvdata(pdev, ecc);
523 + dev_info(dev, "probed\n");
528 +#ifdef CONFIG_PM_SLEEP
529 +static int mtk_ecc_suspend(struct device *dev)
531 + struct mtk_ecc *ecc = dev_get_drvdata(dev);
533 + clk_disable_unprepare(ecc->clk);
538 +static int mtk_ecc_resume(struct device *dev)
540 + struct mtk_ecc *ecc = dev_get_drvdata(dev);
543 + ret = clk_prepare_enable(ecc->clk);
545 + dev_err(dev, "failed to enable clk\n");
549 + mtk_ecc_hw_init(ecc);
554 +static SIMPLE_DEV_PM_OPS(mtk_ecc_pm_ops, mtk_ecc_suspend, mtk_ecc_resume);
557 +static const struct of_device_id mtk_ecc_dt_match[] = {
558 + { .compatible = "mediatek,mt2701-ecc" },
562 +MODULE_DEVICE_TABLE(of, mtk_ecc_dt_match);
564 +static struct platform_driver mtk_ecc_driver = {
565 + .probe = mtk_ecc_probe,
568 + .of_match_table = of_match_ptr(mtk_ecc_dt_match),
569 +#ifdef CONFIG_PM_SLEEP
570 + .pm = &mtk_ecc_pm_ops,
575 +module_platform_driver(mtk_ecc_driver);
577 +MODULE_AUTHOR("Xiaolei Li <xiaolei.li@mediatek.com>");
578 +MODULE_AUTHOR("Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>");
579 +MODULE_DESCRIPTION("MTK Nand ECC Driver");
580 +MODULE_LICENSE("GPL");
581 diff --git a/drivers/mtd/nand/mtk_ecc.h b/drivers/mtd/nand/mtk_ecc.h
583 index 0000000..434826f
585 +++ b/drivers/mtd/nand/mtk_ecc.h
588 + * MTK SDG1 ECC controller
590 + * Copyright (c) 2016 Mediatek
591 + * Authors: Xiaolei Li <xiaolei.li@mediatek.com>
592 + * Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
593 + * This program is free software; you can redistribute it and/or modify it
594 + * under the terms of the GNU General Public License version 2 as published
595 + * by the Free Software Foundation.
598 +#ifndef __DRIVERS_MTD_NAND_MTK_ECC_H__
599 +#define __DRIVERS_MTD_NAND_MTK_ECC_H__
601 +#include <linux/types.h>
603 +#define ECC_PARITY_BITS (14)
605 +enum mtk_ecc_mode {ECC_DMA_MODE = 0, ECC_NFI_MODE = 1};
606 +enum mtk_ecc_codec {ECC_ENC, ECC_DEC};
611 +struct mtk_ecc_stats {
617 +struct mtk_ecc_config {
618 + enum mtk_ecc_mode ecc_mode;
619 + enum mtk_ecc_codec codec;
627 +int mtk_ecc_enable(struct mtk_ecc *, struct mtk_ecc_config *);
628 +void mtk_ecc_disable(struct mtk_ecc *, struct mtk_ecc_config *);
629 +int mtk_ecc_encode_non_nfi_mode(struct mtk_ecc *, struct mtk_ecc_config *,
631 +void mtk_ecc_get_stats(struct mtk_ecc *, struct mtk_ecc_stats *, int);
632 +int mtk_ecc_wait_irq_done(struct mtk_ecc *, enum mtk_ecc_codec);
633 +void mtk_ecc_hw_init(struct mtk_ecc *);
634 +void mtk_ecc_update_strength(u32 *);
636 +struct mtk_ecc *of_mtk_ecc_get(struct device_node *);
637 +void mtk_ecc_release(struct mtk_ecc *);
640 diff --git a/drivers/mtd/nand/mtk_nand.c b/drivers/mtd/nand/mtk_nand.c
642 index 0000000..907b90c
644 +++ b/drivers/mtd/nand/mtk_nand.c
647 + * MTK NAND Flash controller driver.
648 + * Copyright (C) 2016 MediaTek Inc.
649 + * Authors: Xiaolei Li <xiaolei.li@mediatek.com>
650 + * Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
652 + * This program is free software; you can redistribute it and/or modify
653 + * it under the terms of the GNU General Public License version 2 as
654 + * published by the Free Software Foundation.
656 + * This program is distributed in the hope that it will be useful,
657 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
658 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
659 + * GNU General Public License for more details.
662 +#include <linux/platform_device.h>
663 +#include <linux/dma-mapping.h>
664 +#include <linux/interrupt.h>
665 +#include <linux/delay.h>
666 +#include <linux/clk.h>
667 +#include <linux/mtd/nand.h>
668 +#include <linux/mtd/mtd.h>
669 +#include <linux/module.h>
670 +#include <linux/iopoll.h>
671 +#include <linux/of.h>
672 +#include "mtk_ecc.h"
674 +/* NAND controller register definition */
675 +#define NFI_CNFG (0x00)
676 +#define CNFG_AHB BIT(0)
677 +#define CNFG_READ_EN BIT(1)
678 +#define CNFG_DMA_BURST_EN BIT(2)
679 +#define CNFG_BYTE_RW BIT(6)
680 +#define CNFG_HW_ECC_EN BIT(8)
681 +#define CNFG_AUTO_FMT_EN BIT(9)
682 +#define CNFG_OP_CUST (6 << 12)
683 +#define NFI_PAGEFMT (0x04)
684 +#define PAGEFMT_FDM_ECC_SHIFT (12)
685 +#define PAGEFMT_FDM_SHIFT (8)
686 +#define PAGEFMT_SPARE_16 (0)
687 +#define PAGEFMT_SPARE_26 (1)
688 +#define PAGEFMT_SPARE_27 (2)
689 +#define PAGEFMT_SPARE_28 (3)
690 +#define PAGEFMT_SPARE_32 (4)
691 +#define PAGEFMT_SPARE_36 (5)
692 +#define PAGEFMT_SPARE_40 (6)
693 +#define PAGEFMT_SPARE_44 (7)
694 +#define PAGEFMT_SPARE_48 (8)
695 +#define PAGEFMT_SPARE_49 (9)
696 +#define PAGEFMT_SPARE_50 (0xa)
697 +#define PAGEFMT_SPARE_51 (0xb)
698 +#define PAGEFMT_SPARE_52 (0xc)
699 +#define PAGEFMT_SPARE_62 (0xd)
700 +#define PAGEFMT_SPARE_63 (0xe)
701 +#define PAGEFMT_SPARE_64 (0xf)
702 +#define PAGEFMT_SPARE_SHIFT (4)
703 +#define PAGEFMT_SEC_SEL_512 BIT(2)
704 +#define PAGEFMT_512_2K (0)
705 +#define PAGEFMT_2K_4K (1)
706 +#define PAGEFMT_4K_8K (2)
707 +#define PAGEFMT_8K_16K (3)
709 +#define NFI_CON (0x08)
710 +#define CON_FIFO_FLUSH BIT(0)
711 +#define CON_NFI_RST BIT(1)
712 +#define CON_BRD BIT(8) /* burst read */
713 +#define CON_BWR BIT(9) /* burst write */
714 +#define CON_SEC_SHIFT (12)
715 +/* Timming control register */
716 +#define NFI_ACCCON (0x0C)
717 +#define NFI_INTR_EN (0x10)
718 +#define INTR_AHB_DONE_EN BIT(6)
719 +#define NFI_INTR_STA (0x14)
720 +#define NFI_CMD (0x20)
721 +#define NFI_ADDRNOB (0x30)
722 +#define NFI_COLADDR (0x34)
723 +#define NFI_ROWADDR (0x38)
724 +#define NFI_STRDATA (0x40)
727 +#define NFI_CNRNB (0x44)
728 +#define NFI_DATAW (0x50)
729 +#define NFI_DATAR (0x54)
730 +#define NFI_PIO_DIRDY (0x58)
731 +#define PIO_DI_RDY (0x01)
732 +#define NFI_STA (0x60)
733 +#define STA_CMD BIT(0)
734 +#define STA_ADDR BIT(1)
735 +#define STA_BUSY BIT(8)
736 +#define STA_EMP_PAGE BIT(12)
737 +#define NFI_FSM_CUSTDATA (0xe << 16)
738 +#define NFI_FSM_MASK (0xf << 16)
739 +#define NFI_ADDRCNTR (0x70)
740 +#define CNTR_MASK GENMASK(16, 12)
741 +#define NFI_STRADDR (0x80)
742 +#define NFI_BYTELEN (0x84)
743 +#define NFI_CSEL (0x90)
744 +#define NFI_FDML(x) (0xA0 + (x) * sizeof(u32) * 2)
745 +#define NFI_FDMM(x) (0xA4 + (x) * sizeof(u32) * 2)
746 +#define NFI_FDM_MAX_SIZE (8)
747 +#define NFI_MASTER_STA (0x224)
748 +#define MASTER_STA_MASK (0x0FFF)
749 +#define NFI_EMPTY_THRESH (0x23C)
751 +#define MTK_NAME "mtk-nand"
752 +#define KB(x) ((x) * 1024UL)
753 +#define MB(x) (KB(x) * 1024UL)
755 +#define MTK_TIMEOUT (500000)
756 +#define MTK_RESET_TIMEOUT (1000000)
757 +#define MTK_MAX_SECTOR (16)
758 +#define MTK_NAND_MAX_NSELS (2)
760 +typedef void (*bad_mark_swap)(struct mtd_info *, uint8_t *buf, int raw);
761 +struct mtk_nfc_bad_mark_ctl {
762 + bad_mark_swap bm_swap;
768 + * FDM: region used to store free OOB data
770 +struct mtk_nfc_fdm {
775 +struct mtk_nfc_nand_chip {
776 + struct list_head node;
777 + struct nand_chip nand;
779 + struct mtk_nfc_bad_mark_ctl bad_mark;
780 + struct mtk_nfc_fdm fdm;
781 + u32 spare_per_sector;
785 + /* nothing after this field */
788 +struct mtk_nfc_clk {
789 + struct clk *nfi_clk;
790 + struct clk *pad_clk;
794 + struct nand_hw_control controller;
795 + struct mtk_ecc_config ecc_cfg;
796 + struct mtk_nfc_clk clk;
797 + struct mtk_ecc *ecc;
799 + struct device *dev;
800 + void __iomem *regs;
802 + struct completion done;
803 + struct list_head chips;
808 +static inline struct mtk_nfc_nand_chip *to_mtk_nand(struct nand_chip *nand)
810 + return container_of(nand, struct mtk_nfc_nand_chip, nand);
813 +static inline uint8_t *data_ptr(struct nand_chip *chip, const uint8_t *p, int i)
815 + return (uint8_t *) p + i * chip->ecc.size;
818 +static inline uint8_t *oob_ptr(struct nand_chip *chip, int i)
820 + struct mtk_nfc_nand_chip *mtk_nand = to_mtk_nand(chip);
823 + if (i < mtk_nand->bad_mark.sec)
824 + poi = chip->oob_poi + (i + 1) * mtk_nand->fdm.reg_size;
825 + else if (i == mtk_nand->bad_mark.sec)
826 + poi = chip->oob_poi;
828 + poi = chip->oob_poi + i * mtk_nand->fdm.reg_size;
833 +static inline int mtk_data_len(struct nand_chip *chip)
835 + struct mtk_nfc_nand_chip *mtk_nand = to_mtk_nand(chip);
837 + return chip->ecc.size + mtk_nand->spare_per_sector;
840 +static inline uint8_t *mtk_data_ptr(struct nand_chip *chip, int i)
842 + struct mtk_nfc *nfc = nand_get_controller_data(chip);
844 + return nfc->buffer + i * mtk_data_len(chip);
847 +static inline uint8_t *mtk_oob_ptr(struct nand_chip *chip, int i)
849 + struct mtk_nfc *nfc = nand_get_controller_data(chip);
851 + return nfc->buffer + i * mtk_data_len(chip) + chip->ecc.size;
854 +static inline void nfi_writel(struct mtk_nfc *nfc, u32 val, u32 reg)
856 + writel(val, nfc->regs + reg);
859 +static inline void nfi_writew(struct mtk_nfc *nfc, u16 val, u32 reg)
861 + writew(val, nfc->regs + reg);
864 +static inline void nfi_writeb(struct mtk_nfc *nfc, u8 val, u32 reg)
866 + writeb(val, nfc->regs + reg);
869 +static inline u32 nfi_readl(struct mtk_nfc *nfc, u32 reg)
871 + return readl_relaxed(nfc->regs + reg);
874 +static inline u16 nfi_readw(struct mtk_nfc *nfc, u32 reg)
876 + return readw_relaxed(nfc->regs + reg);
879 +static inline u8 nfi_readb(struct mtk_nfc *nfc, u32 reg)
881 + return readb_relaxed(nfc->regs + reg);
884 +static void mtk_nfc_hw_reset(struct mtk_nfc *nfc)
886 + struct device *dev = nfc->dev;
890 + /* reset all registers and force the NFI master to terminate */
891 + nfi_writel(nfc, CON_FIFO_FLUSH | CON_NFI_RST, NFI_CON);
893 + /* wait for the master to finish the last transaction */
894 + ret = readl_poll_timeout(nfc->regs + NFI_MASTER_STA, val,
895 + !(val & MASTER_STA_MASK), 50, MTK_RESET_TIMEOUT);
897 + dev_warn(dev, "master active in reset [0x%x] = 0x%x\n",
898 + NFI_MASTER_STA, val);
900 + /* ensure any status register affected by the NFI master is reset */
901 + nfi_writel(nfc, CON_FIFO_FLUSH | CON_NFI_RST, NFI_CON);
902 + nfi_writew(nfc, STAR_DE, NFI_STRDATA);
905 +static int mtk_nfc_send_command(struct mtk_nfc *nfc, u8 command)
907 + struct device *dev = nfc->dev;
911 + nfi_writel(nfc, command, NFI_CMD);
913 + ret = readl_poll_timeout_atomic(nfc->regs + NFI_STA, val,
914 + !(val & STA_CMD), 10, MTK_TIMEOUT);
916 + dev_warn(dev, "nfi core timed out entering command mode\n");
923 +static int mtk_nfc_send_address(struct mtk_nfc *nfc, int addr)
925 + struct device *dev = nfc->dev;
929 + nfi_writel(nfc, addr, NFI_COLADDR);
930 + nfi_writel(nfc, 0, NFI_ROWADDR);
931 + nfi_writew(nfc, 1, NFI_ADDRNOB);
933 + ret = readl_poll_timeout_atomic(nfc->regs + NFI_STA, val,
934 + !(val & STA_ADDR), 10, MTK_TIMEOUT);
936 + dev_warn(dev, "nfi core timed out entering address mode\n");
943 +static int mtk_nfc_hw_runtime_config(struct mtd_info *mtd)
945 + struct nand_chip *chip = mtd_to_nand(mtd);
946 + struct mtk_nfc_nand_chip *mtk_nand = to_mtk_nand(chip);
947 + struct mtk_nfc *nfc = nand_get_controller_data(chip);
950 + if (!mtd->writesize)
953 + spare = mtk_nand->spare_per_sector;
955 + switch (mtd->writesize) {
957 + fmt = PAGEFMT_512_2K | PAGEFMT_SEC_SEL_512;
960 + if (chip->ecc.size == 512)
961 + fmt = PAGEFMT_2K_4K | PAGEFMT_SEC_SEL_512;
963 + fmt = PAGEFMT_512_2K;
966 + if (chip->ecc.size == 512)
967 + fmt = PAGEFMT_4K_8K | PAGEFMT_SEC_SEL_512;
969 + fmt = PAGEFMT_2K_4K;
972 + if (chip->ecc.size == 512)
973 + fmt = PAGEFMT_8K_16K | PAGEFMT_SEC_SEL_512;
975 + fmt = PAGEFMT_4K_8K;
978 + fmt = PAGEFMT_8K_16K;
981 + dev_err(nfc->dev, "invalid page len: %d\n", mtd->writesize);
985 + /* the hardware doubles the value for this eccsize so let's halve it */
986 + if (chip->ecc.size == 1024)
991 + fmt |= (PAGEFMT_SPARE_16 << PAGEFMT_SPARE_SHIFT);
994 + fmt |= (PAGEFMT_SPARE_26 << PAGEFMT_SPARE_SHIFT);
997 + fmt |= (PAGEFMT_SPARE_27 << PAGEFMT_SPARE_SHIFT);
1000 + fmt |= (PAGEFMT_SPARE_28 << PAGEFMT_SPARE_SHIFT);
1003 + fmt |= (PAGEFMT_SPARE_32 << PAGEFMT_SPARE_SHIFT);
1006 + fmt |= (PAGEFMT_SPARE_36 << PAGEFMT_SPARE_SHIFT);
1009 + fmt |= (PAGEFMT_SPARE_40 << PAGEFMT_SPARE_SHIFT);
1012 + fmt |= (PAGEFMT_SPARE_44 << PAGEFMT_SPARE_SHIFT);
1015 + fmt |= (PAGEFMT_SPARE_48 << PAGEFMT_SPARE_SHIFT);
1018 + fmt |= (PAGEFMT_SPARE_49 << PAGEFMT_SPARE_SHIFT);
1021 + fmt |= (PAGEFMT_SPARE_50 << PAGEFMT_SPARE_SHIFT);
1024 + fmt |= (PAGEFMT_SPARE_51 << PAGEFMT_SPARE_SHIFT);
1027 + fmt |= (PAGEFMT_SPARE_52 << PAGEFMT_SPARE_SHIFT);
1030 + fmt |= (PAGEFMT_SPARE_62 << PAGEFMT_SPARE_SHIFT);
1033 + fmt |= (PAGEFMT_SPARE_63 << PAGEFMT_SPARE_SHIFT);
1036 + fmt |= (PAGEFMT_SPARE_64 << PAGEFMT_SPARE_SHIFT);
1039 + dev_err(nfc->dev, "invalid spare per sector %d\n", spare);
1043 + fmt |= mtk_nand->fdm.reg_size << PAGEFMT_FDM_SHIFT;
1044 + fmt |= mtk_nand->fdm.ecc_size << PAGEFMT_FDM_ECC_SHIFT;
1045 + nfi_writew(nfc, fmt, NFI_PAGEFMT);
1047 + nfc->ecc_cfg.strength = chip->ecc.strength;
1048 + nfc->ecc_cfg.enc_len = chip->ecc.size + mtk_nand->fdm.ecc_size;
1049 + nfc->ecc_cfg.dec_len = (nfc->ecc_cfg.enc_len << 3)
1050 + + chip->ecc.strength * ECC_PARITY_BITS;
1055 +static void mtk_nfc_select_chip(struct mtd_info *mtd, int chip)
1057 + struct nand_chip *nand = mtd_to_nand(mtd);
1058 + struct mtk_nfc *nfc = nand_get_controller_data(nand);
1059 + struct mtk_nfc_nand_chip *mtk_nand = to_mtk_nand(nand);
1064 + mtk_nfc_hw_runtime_config(mtd);
1066 + nfi_writel(nfc, mtk_nand->sels[chip], NFI_CSEL);
1069 +static int mtk_nfc_dev_ready(struct mtd_info *mtd)
1071 + struct mtk_nfc *nfc = nand_get_controller_data(mtd_to_nand(mtd));
1073 + if (nfi_readl(nfc, NFI_STA) & STA_BUSY)
1079 +static void mtk_nfc_cmd_ctrl(struct mtd_info *mtd, int dat, unsigned int ctrl)
1081 + struct mtk_nfc *nfc = nand_get_controller_data(mtd_to_nand(mtd));
1083 + if (ctrl & NAND_ALE)
1084 + mtk_nfc_send_address(nfc, dat);
1085 + else if (ctrl & NAND_CLE) {
1086 + mtk_nfc_hw_reset(nfc);
1088 + nfi_writew(nfc, CNFG_OP_CUST, NFI_CNFG);
1089 + mtk_nfc_send_command(nfc, dat);
1093 +static inline void mtk_nfc_wait_ioready(struct mtk_nfc *nfc)
1098 + rc = readb_poll_timeout_atomic(nfc->regs + NFI_PIO_DIRDY, val,
1099 + val & PIO_DI_RDY, 10, MTK_TIMEOUT);
1101 + dev_err(nfc->dev, "data not ready\n");
1104 +static inline uint8_t mtk_nfc_read_byte(struct mtd_info *mtd)
1106 + struct nand_chip *chip = mtd_to_nand(mtd);
1107 + struct mtk_nfc *nfc = nand_get_controller_data(chip);
1110 + reg = nfi_readl(nfc, NFI_STA) & NFI_FSM_MASK;
1111 + if (reg != NFI_FSM_CUSTDATA) {
1112 + reg = nfi_readw(nfc, NFI_CNFG);
1113 + reg |= CNFG_BYTE_RW | CNFG_READ_EN;
1114 + nfi_writew(nfc, reg, NFI_CNFG);
1116 + reg = (MTK_MAX_SECTOR << CON_SEC_SHIFT) | CON_BRD;
1117 + nfi_writel(nfc, reg, NFI_CON);
1119 + /* trigger to fetch data */
1120 + nfi_writew(nfc, STAR_EN, NFI_STRDATA);
1123 + mtk_nfc_wait_ioready(nfc);
1125 + return nfi_readb(nfc, NFI_DATAR);
1128 +static void mtk_nfc_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
1132 + for (i = 0; i < len; i++)
1133 + buf[i] = mtk_nfc_read_byte(mtd);
1136 +static void mtk_nfc_write_byte(struct mtd_info *mtd, uint8_t byte)
1138 + struct mtk_nfc *nfc = nand_get_controller_data(mtd_to_nand(mtd));
1141 + reg = nfi_readl(nfc, NFI_STA) & NFI_FSM_MASK;
1143 + if (reg != NFI_FSM_CUSTDATA) {
1144 + reg = nfi_readw(nfc, NFI_CNFG) | CNFG_BYTE_RW;
1145 + nfi_writew(nfc, reg, NFI_CNFG);
1147 + reg = MTK_MAX_SECTOR << CON_SEC_SHIFT | CON_BWR;
1148 + nfi_writel(nfc, reg, NFI_CON);
1150 + nfi_writew(nfc, STAR_EN, NFI_STRDATA);
1153 + mtk_nfc_wait_ioready(nfc);
1154 + nfi_writeb(nfc, byte, NFI_DATAW);
1157 +static void mtk_nfc_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
1161 + for (i = 0; i < len; i++)
1162 + mtk_nfc_write_byte(mtd, buf[i]);
1165 +static int mtk_nfc_sector_encode(struct nand_chip *chip, u8 *data)
1167 + struct mtk_nfc *nfc = nand_get_controller_data(chip);
1168 + struct mtk_nfc_nand_chip *mtk_nand = to_mtk_nand(chip);
1169 + int size = chip->ecc.size + mtk_nand->fdm.reg_size;
1171 + nfc->ecc_cfg.ecc_mode = ECC_DMA_MODE;
1172 + nfc->ecc_cfg.codec = ECC_ENC;
1173 + return mtk_ecc_encode_non_nfi_mode(nfc->ecc, &nfc->ecc_cfg, data, size);
1176 +static void mtk_nfc_no_bad_mark_swap(struct mtd_info *a, uint8_t *b, int c)
1181 +static void mtk_nfc_bad_mark_swap(struct mtd_info *mtd, uint8_t *buf, int raw)
1183 + struct nand_chip *chip = mtd_to_nand(mtd);
1184 + struct mtk_nfc_nand_chip *nand = to_mtk_nand(chip);
1185 + u32 bad_pos = nand->bad_mark.pos;
1188 + bad_pos += nand->bad_mark.sec * mtk_data_len(chip);
1190 + bad_pos += nand->bad_mark.sec * chip->ecc.size;
1192 + swap(chip->oob_poi[0], buf[bad_pos]);
1195 +static int mtk_nfc_format_subpage(struct mtd_info *mtd, uint32_t offset,
1196 + uint32_t len, const uint8_t *buf)
1198 + struct nand_chip *chip = mtd_to_nand(mtd);
1199 + struct mtk_nfc_nand_chip *mtk_nand = to_mtk_nand(chip);
1200 + struct mtk_nfc *nfc = nand_get_controller_data(chip);
1201 + struct mtk_nfc_fdm *fdm = &mtk_nand->fdm;
1205 + start = offset / chip->ecc.size;
1206 + end = DIV_ROUND_UP(offset + len, chip->ecc.size);
1208 + memset(nfc->buffer, 0xff, mtd->writesize + mtd->oobsize);
1209 + for (i = 0; i < chip->ecc.steps; i++) {
1211 + memcpy(mtk_data_ptr(chip, i), data_ptr(chip, buf, i),
1214 + if (start > i || i >= end)
1217 + if (i == mtk_nand->bad_mark.sec)
1218 + mtk_nand->bad_mark.bm_swap(mtd, nfc->buffer, 1);
1220 + memcpy(mtk_oob_ptr(chip, i), oob_ptr(chip, i), fdm->reg_size);
1222 + /* program the CRC back to the OOB */
1223 + ret = mtk_nfc_sector_encode(chip, mtk_data_ptr(chip, i));
1231 +static void mtk_nfc_format_page(struct mtd_info *mtd, const uint8_t *buf)
1233 + struct nand_chip *chip = mtd_to_nand(mtd);
1234 + struct mtk_nfc_nand_chip *mtk_nand = to_mtk_nand(chip);
1235 + struct mtk_nfc *nfc = nand_get_controller_data(chip);
1236 + struct mtk_nfc_fdm *fdm = &mtk_nand->fdm;
1239 + memset(nfc->buffer, 0xff, mtd->writesize + mtd->oobsize);
1240 + for (i = 0; i < chip->ecc.steps; i++) {
1242 + memcpy(mtk_data_ptr(chip, i), data_ptr(chip, buf, i),
1245 + if (i == mtk_nand->bad_mark.sec)
1246 + mtk_nand->bad_mark.bm_swap(mtd, nfc->buffer, 1);
1248 + memcpy(mtk_oob_ptr(chip, i), oob_ptr(chip, i), fdm->reg_size);
1252 +static inline void mtk_nfc_read_fdm(struct nand_chip *chip, u32 start,
1255 + struct mtk_nfc *nfc = nand_get_controller_data(chip);
1259 + for (i = 0; i < sectors; i++) {
1260 + p = (u32 *) oob_ptr(chip, start + i);
1261 + p[0] = nfi_readl(nfc, NFI_FDML(i));
1262 + p[1] = nfi_readl(nfc, NFI_FDMM(i));
1266 +static inline void mtk_nfc_write_fdm(struct nand_chip *chip)
1268 + struct mtk_nfc *nfc = nand_get_controller_data(chip);
1272 + for (i = 0; i < chip->ecc.steps ; i++) {
1273 + p = (u32 *) oob_ptr(chip, i);
1274 + nfi_writel(nfc, p[0], NFI_FDML(i));
1275 + nfi_writel(nfc, p[1], NFI_FDMM(i));
1279 +static int mtk_nfc_do_write_page(struct mtd_info *mtd, struct nand_chip *chip,
1280 + const uint8_t *buf, int page, int len)
1283 + struct mtk_nfc *nfc = nand_get_controller_data(chip);
1284 + struct device *dev = nfc->dev;
1289 + addr = dma_map_single(dev, (void *) buf, len, DMA_TO_DEVICE);
1290 + ret = dma_mapping_error(nfc->dev, addr);
1292 + dev_err(nfc->dev, "dma mapping error\n");
1296 + reg = nfi_readw(nfc, NFI_CNFG) | CNFG_AHB | CNFG_DMA_BURST_EN;
1297 + nfi_writew(nfc, reg, NFI_CNFG);
1299 + nfi_writel(nfc, chip->ecc.steps << CON_SEC_SHIFT, NFI_CON);
1300 + nfi_writel(nfc, lower_32_bits(addr), NFI_STRADDR);
1301 + nfi_writew(nfc, INTR_AHB_DONE_EN, NFI_INTR_EN);
1303 + init_completion(&nfc->done);
1305 + reg = nfi_readl(nfc, NFI_CON) | CON_BWR;
1306 + nfi_writel(nfc, reg, NFI_CON);
1307 + nfi_writew(nfc, STAR_EN, NFI_STRDATA);
1309 + ret = wait_for_completion_timeout(&nfc->done, msecs_to_jiffies(500));
1311 + dev_err(dev, "program ahb done timeout\n");
1312 + nfi_writew(nfc, 0, NFI_INTR_EN);
1317 + ret = readl_poll_timeout_atomic(nfc->regs + NFI_ADDRCNTR, reg,
1318 + (reg & CNTR_MASK) >= chip->ecc.steps, 10, MTK_TIMEOUT);
1320 + dev_err(dev, "hwecc write timeout\n");
1324 + dma_unmap_single(nfc->dev, addr, len, DMA_TO_DEVICE);
1325 + nfi_writel(nfc, 0, NFI_CON);
1330 +static int mtk_nfc_write_page(struct mtd_info *mtd, struct nand_chip *chip,
1331 + const uint8_t *buf, int page, int raw)
1333 + struct mtk_nfc *nfc = nand_get_controller_data(chip);
1334 + struct mtk_nfc_nand_chip *mtk_nand = to_mtk_nand(chip);
1341 + /* OOB => FDM: from register, ECC: from HW */
1342 + reg = nfi_readw(nfc, NFI_CNFG) | CNFG_AUTO_FMT_EN;
1343 + nfi_writew(nfc, reg | CNFG_HW_ECC_EN, NFI_CNFG);
1345 + nfc->ecc_cfg.codec = ECC_ENC;
1346 + nfc->ecc_cfg.ecc_mode = ECC_NFI_MODE;
1347 + ret = mtk_ecc_enable(nfc->ecc, &nfc->ecc_cfg);
1349 + /* clear NFI config */
1350 + reg = nfi_readw(nfc, NFI_CNFG);
1351 + reg &= ~(CNFG_AUTO_FMT_EN | CNFG_HW_ECC_EN);
1352 + nfi_writew(nfc, reg, NFI_CNFG);
1357 + memcpy(nfc->buffer, buf, mtd->writesize);
1358 + mtk_nand->bad_mark.bm_swap(mtd, nfc->buffer, raw);
1359 + bufpoi = nfc->buffer;
1361 + /* write OOB into the FDM registers (OOB area in MTK NAND) */
1362 + mtk_nfc_write_fdm(chip);
1366 + len = mtd->writesize + (raw ? mtd->oobsize : 0);
1367 + ret = mtk_nfc_do_write_page(mtd, chip, bufpoi, page, len);
1370 + mtk_ecc_disable(nfc->ecc, &nfc->ecc_cfg);
1375 +static int mtk_nfc_write_page_hwecc(struct mtd_info *mtd,
1376 + struct nand_chip *chip, const uint8_t *buf, int oob_on, int page)
1378 + return mtk_nfc_write_page(mtd, chip, buf, page, 0);
1381 +static int mtk_nfc_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1382 + const uint8_t *buf, int oob_on, int pg)
1384 + struct mtk_nfc *nfc = nand_get_controller_data(chip);
1386 + mtk_nfc_format_page(mtd, buf);
1387 + return mtk_nfc_write_page(mtd, chip, nfc->buffer, pg, 1);
1390 +static int mtk_nfc_write_subpage_hwecc(struct mtd_info *mtd,
1391 + struct nand_chip *chip, uint32_t offset, uint32_t data_len,
1392 + const uint8_t *buf, int oob_on, int page)
1394 + struct mtk_nfc *nfc = nand_get_controller_data(chip);
1397 + ret = mtk_nfc_format_subpage(mtd, offset, data_len, buf);
1401 + /* use the data in the private buffer (now with FDM and CRC) */
1402 + return mtk_nfc_write_page(mtd, chip, nfc->buffer, page, 1);
1405 +static int mtk_nfc_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1410 + chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
1412 + ret = mtk_nfc_write_page_raw(mtd, chip, NULL, 1, page);
1416 + chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1417 + ret = chip->waitfunc(mtd, chip);
1419 + return ret & NAND_STATUS_FAIL ? -EIO : 0;
1422 +static int mtk_nfc_update_ecc_stats(struct mtd_info *mtd, u8 *buf, u32 sectors)
1424 + struct nand_chip *chip = mtd_to_nand(mtd);
1425 + struct mtk_nfc *nfc = nand_get_controller_data(chip);
1426 + struct mtk_nfc_nand_chip *mtk_nand = to_mtk_nand(chip);
1427 + struct mtk_ecc_stats stats;
1430 + rc = nfi_readl(nfc, NFI_STA) & STA_EMP_PAGE;
1432 + memset(buf, 0xff, sectors * chip->ecc.size);
1433 + for (i = 0; i < sectors; i++)
1434 + memset(oob_ptr(chip, i), 0xff, mtk_nand->fdm.reg_size);
1438 + mtk_ecc_get_stats(nfc->ecc, &stats, sectors);
1439 + mtd->ecc_stats.corrected += stats.corrected;
1440 + mtd->ecc_stats.failed += stats.failed;
1442 + return stats.bitflips;
1445 +static int mtk_nfc_read_subpage(struct mtd_info *mtd, struct nand_chip *chip,
1446 + uint32_t data_offs, uint32_t readlen, uint8_t *bufpoi,
1447 + int page, int raw)
1449 + struct mtk_nfc *nfc = nand_get_controller_data(chip);
1450 + struct mtk_nfc_nand_chip *mtk_nand = to_mtk_nand(chip);
1451 + u32 spare = mtk_nand->spare_per_sector;
1452 + u32 column, sectors, start, end, reg;
1459 + start = data_offs / chip->ecc.size;
1460 + end = DIV_ROUND_UP(data_offs + readlen, chip->ecc.size);
1462 + sectors = end - start;
1463 + column = start * (chip->ecc.size + spare);
1465 + len = sectors * chip->ecc.size + (raw ? sectors * spare : 0);
1466 + buf = bufpoi + start * chip->ecc.size;
1469 + chip->cmdfunc(mtd, NAND_CMD_RNDOUT, column, -1);
1471 + addr = dma_map_single(nfc->dev, buf, len, DMA_FROM_DEVICE);
1472 + rc = dma_mapping_error(nfc->dev, addr);
1474 + dev_err(nfc->dev, "dma mapping error\n");
1479 + reg = nfi_readw(nfc, NFI_CNFG);
1480 + reg |= CNFG_READ_EN | CNFG_DMA_BURST_EN | CNFG_AHB;
1482 + reg |= CNFG_AUTO_FMT_EN | CNFG_HW_ECC_EN;
1483 + nfi_writew(nfc, reg, NFI_CNFG);
1485 + nfc->ecc_cfg.ecc_mode = ECC_NFI_MODE;
1486 + nfc->ecc_cfg.sec_mask = sectors;
1487 + nfc->ecc_cfg.codec = ECC_DEC;
1488 + rc = mtk_ecc_enable(nfc->ecc, &nfc->ecc_cfg);
1490 + dev_err(nfc->dev, "ecc enable\n");
1491 + /* clear NFI_CNFG */
1492 + reg &= ~(CNFG_DMA_BURST_EN | CNFG_AHB | CNFG_READ_EN |
1493 + CNFG_AUTO_FMT_EN | CNFG_HW_ECC_EN);
1494 + nfi_writew(nfc, reg, NFI_CNFG);
1495 + dma_unmap_single(nfc->dev, addr, len, DMA_FROM_DEVICE);
1500 + nfi_writew(nfc, reg, NFI_CNFG);
1502 + nfi_writel(nfc, sectors << CON_SEC_SHIFT, NFI_CON);
1503 + nfi_writew(nfc, INTR_AHB_DONE_EN, NFI_INTR_EN);
1504 + nfi_writel(nfc, lower_32_bits(addr), NFI_STRADDR);
1506 + init_completion(&nfc->done);
1507 + reg = nfi_readl(nfc, NFI_CON) | CON_BRD;
1508 + nfi_writel(nfc, reg, NFI_CON);
1509 + nfi_writew(nfc, STAR_EN, NFI_STRDATA);
1511 + rc = wait_for_completion_timeout(&nfc->done, msecs_to_jiffies(500));
1513 + dev_warn(nfc->dev, "read ahb/dma done timeout\n");
1515 + rc = readl_poll_timeout_atomic(nfc->regs + NFI_BYTELEN, reg,
1516 + (reg & CNTR_MASK) >= sectors, 10, MTK_TIMEOUT);
1518 + dev_err(nfc->dev, "subpage done timeout\n");
1523 + rc = mtk_ecc_wait_irq_done(nfc->ecc, ECC_DEC);
1524 + bitflips = rc < 0 ? -ETIMEDOUT :
1525 + mtk_nfc_update_ecc_stats(mtd, buf, sectors);
1526 + mtk_nfc_read_fdm(chip, start, sectors);
1530 + dma_unmap_single(nfc->dev, addr, len, DMA_FROM_DEVICE);
1535 + mtk_ecc_disable(nfc->ecc, &nfc->ecc_cfg);
1537 + if (clamp(mtk_nand->bad_mark.sec, start, end) == mtk_nand->bad_mark.sec)
1538 + mtk_nand->bad_mark.bm_swap(mtd, bufpoi, raw);
1540 + nfi_writel(nfc, 0, NFI_CON);
1545 +static int mtk_nfc_read_subpage_hwecc(struct mtd_info *mtd,
1546 + struct nand_chip *chip, uint32_t off, uint32_t len, uint8_t *p, int pg)
1548 + return mtk_nfc_read_subpage(mtd, chip, off, len, p, pg, 0);
1551 +static int mtk_nfc_read_page_hwecc(struct mtd_info *mtd,
1552 + struct nand_chip *chip, uint8_t *p, int oob_on, int pg)
1554 + return mtk_nfc_read_subpage(mtd, chip, 0, mtd->writesize, p, pg, 0);
1557 +static int mtk_nfc_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1558 + uint8_t *buf, int oob_on, int page)
1560 + struct mtk_nfc_nand_chip *mtk_nand = to_mtk_nand(chip);
1561 + struct mtk_nfc *nfc = nand_get_controller_data(chip);
1562 + struct mtk_nfc_fdm *fdm = &mtk_nand->fdm;
1565 + memset(nfc->buffer, 0xff, mtd->writesize + mtd->oobsize);
1566 + ret = mtk_nfc_read_subpage(mtd, chip, 0, mtd->writesize, nfc->buffer,
1571 + for (i = 0; i < chip->ecc.steps; i++) {
1572 + memcpy(oob_ptr(chip, i), mtk_oob_ptr(chip, i), fdm->reg_size);
1573 + if (i == mtk_nand->bad_mark.sec)
1574 + mtk_nand->bad_mark.bm_swap(mtd, nfc->buffer, 1);
1577 + memcpy(data_ptr(chip, buf, i), mtk_data_ptr(chip, i),
1584 +static int mtk_nfc_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1587 + chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
1589 + return mtk_nfc_read_page_raw(mtd, chip, NULL, 1, page);
1592 +static inline void mtk_nfc_hw_init(struct mtk_nfc *nfc)
1594 + nfi_writel(nfc, 0x10804211, NFI_ACCCON);
1595 + nfi_writew(nfc, 0xf1, NFI_CNRNB);
1596 + nfi_writew(nfc, PAGEFMT_8K_16K, NFI_PAGEFMT);
1598 + mtk_nfc_hw_reset(nfc);
1600 + nfi_readl(nfc, NFI_INTR_STA);
1601 + nfi_writel(nfc, 0, NFI_INTR_EN);
1604 +static irqreturn_t mtk_nfc_irq(int irq, void *id)
1606 + struct mtk_nfc *nfc = id;
1609 + sta = nfi_readw(nfc, NFI_INTR_STA);
1610 + ien = nfi_readw(nfc, NFI_INTR_EN);
1615 + nfi_writew(nfc, ~sta & ien, NFI_INTR_EN);
1616 + complete(&nfc->done);
1618 + return IRQ_HANDLED;
1621 +static int mtk_nfc_enable_clk(struct device *dev, struct mtk_nfc_clk *clk)
1625 + ret = clk_prepare_enable(clk->nfi_clk);
1627 + dev_err(dev, "failed to enable nfi clk\n");
1631 + ret = clk_prepare_enable(clk->pad_clk);
1633 + dev_err(dev, "failed to enable pad clk\n");
1634 + clk_disable_unprepare(clk->nfi_clk);
1641 +static void mtk_nfc_disable_clk(struct mtk_nfc_clk *clk)
1643 + clk_disable_unprepare(clk->nfi_clk);
1644 + clk_disable_unprepare(clk->pad_clk);
1647 +static int mtk_nfc_ooblayout_free(struct mtd_info *mtd, int section,
1648 + struct mtd_oob_region *oob_region)
1650 + struct nand_chip *chip = mtd_to_nand(mtd);
1651 + struct mtk_nfc_nand_chip *mtk_nand = to_mtk_nand(chip);
1652 + struct mtk_nfc_fdm *fdm = &mtk_nand->fdm;
1655 + eccsteps = mtd->writesize / chip->ecc.size;
1657 + if (section >= eccsteps)
1660 + oob_region->length = fdm->reg_size - fdm->ecc_size;
1661 + oob_region->offset = section * fdm->reg_size + fdm->ecc_size;
1666 +static int mtk_nfc_ooblayout_ecc(struct mtd_info *mtd, int section,
1667 + struct mtd_oob_region *oob_region)
1669 + struct nand_chip *chip = mtd_to_nand(mtd);
1670 + struct mtk_nfc_nand_chip *mtk_nand = to_mtk_nand(chip);
1676 + eccsteps = mtd->writesize / chip->ecc.size;
1677 + oob_region->offset = mtk_nand->fdm.reg_size * eccsteps;
1678 + oob_region->length = mtd->oobsize - oob_region->offset;
1683 +static const struct mtd_ooblayout_ops mtk_nfc_ooblayout_ops = {
1684 + .free = mtk_nfc_ooblayout_free,
1685 + .ecc = mtk_nfc_ooblayout_ecc,
1688 +static void mtk_nfc_set_fdm(struct mtk_nfc_fdm *fdm, struct mtd_info *mtd)
1690 + struct nand_chip *nand = mtd_to_nand(mtd);
1691 + struct mtk_nfc_nand_chip *chip = to_mtk_nand(nand);
1694 + ecc_bytes = DIV_ROUND_UP(nand->ecc.strength * ECC_PARITY_BITS, 8);
1696 + fdm->reg_size = chip->spare_per_sector - ecc_bytes;
1697 + if (fdm->reg_size > NFI_FDM_MAX_SIZE)
1698 + fdm->reg_size = NFI_FDM_MAX_SIZE;
1700 + /* bad block mark storage */
1701 + fdm->ecc_size = 1;
1704 +static void mtk_nfc_set_bad_mark_ctl(struct mtk_nfc_bad_mark_ctl *bm_ctl,
1705 + struct mtd_info *mtd)
1707 + struct nand_chip *nand = mtd_to_nand(mtd);
1709 + if (mtd->writesize == 512)
1710 + bm_ctl->bm_swap = mtk_nfc_no_bad_mark_swap;
1712 + bm_ctl->bm_swap = mtk_nfc_bad_mark_swap;
1713 + bm_ctl->sec = mtd->writesize / mtk_data_len(nand);
1714 + bm_ctl->pos = mtd->writesize % mtk_data_len(nand);
1718 +static void mtk_nfc_set_spare_per_sector(u32 *sps, struct mtd_info *mtd)
1720 + struct nand_chip *nand = mtd_to_nand(mtd);
1721 + u32 spare[] = {16, 26, 27, 28, 32, 36, 40, 44,
1722 + 48, 49, 50, 51, 52, 62, 63, 64};
1725 + eccsteps = mtd->writesize / nand->ecc.size;
1726 + *sps = mtd->oobsize / eccsteps;
1728 + if (nand->ecc.size == 1024)
1731 + for (i = 0; i < ARRAY_SIZE(spare); i++) {
1732 + if (*sps <= spare[i]) {
1735 + else if (*sps != spare[i])
1736 + *sps = spare[i - 1];
1741 + if (i >= ARRAY_SIZE(spare))
1742 + *sps = spare[ARRAY_SIZE(spare) - 1];
1744 + if (nand->ecc.size == 1024)
1748 +static int mtk_nfc_ecc_init(struct device *dev, struct mtd_info *mtd)
1750 + struct nand_chip *nand = mtd_to_nand(mtd);
1753 + /* support only ecc hw mode */
1754 + if (nand->ecc.mode != NAND_ECC_HW) {
1755 + dev_err(dev, "ecc.mode not supported\n");
1759 + /* if optional DT settings are not present */
1760 + if (!nand->ecc.size || !nand->ecc.strength) {
1762 + /* controller only supports sizes 512 and 1024 */
1763 + nand->ecc.size = (mtd->writesize > 512) ? 1024 : 512;
1765 + /* get controller valid values */
1766 + mtk_nfc_set_spare_per_sector(&spare, mtd);
1767 + spare = spare - NFI_FDM_MAX_SIZE;
1768 + nand->ecc.strength = (spare << 3) / ECC_PARITY_BITS;
1771 + mtk_ecc_update_strength(&nand->ecc.strength);
1773 + dev_info(dev, "eccsize %d eccstrength %d\n",
1774 + nand->ecc.size, nand->ecc.strength);
1779 +static int mtk_nfc_nand_chip_init(struct device *dev, struct mtk_nfc *nfc,
1780 + struct device_node *np)
1782 + struct mtk_nfc_nand_chip *chip;
1783 + struct nand_chip *nand;
1784 + struct mtd_info *mtd;
1790 + if (!of_get_property(np, "reg", &nsels))
1793 + nsels /= sizeof(u32);
1794 + if (!nsels || nsels > MTK_NAND_MAX_NSELS) {
1795 + dev_err(dev, "invalid reg property size %d\n", nsels);
1799 + chip = devm_kzalloc(dev,
1800 + sizeof(*chip) + nsels * sizeof(u8), GFP_KERNEL);
1804 + chip->nsels = nsels;
1805 + for (i = 0; i < nsels; i++) {
1806 + ret = of_property_read_u32_index(np, "reg", i, &tmp);
1808 + dev_err(dev, "reg property failure : %d\n", ret);
1811 + chip->sels[i] = tmp;
1814 + nand = &chip->nand;
1815 + nand->controller = &nfc->controller;
1817 + nand_set_flash_node(nand, np);
1818 + nand_set_controller_data(nand, nfc);
1820 + nand->options |= NAND_USE_BOUNCE_BUFFER | NAND_SUBPAGE_READ;
1821 + nand->dev_ready = mtk_nfc_dev_ready;
1822 + nand->select_chip = mtk_nfc_select_chip;
1823 + nand->write_byte = mtk_nfc_write_byte;
1824 + nand->write_buf = mtk_nfc_write_buf;
1825 + nand->read_byte = mtk_nfc_read_byte;
1826 + nand->read_buf = mtk_nfc_read_buf;
1827 + nand->cmd_ctrl = mtk_nfc_cmd_ctrl;
1829 + /* set default mode in case dt entry is missing */
1830 + nand->ecc.mode = NAND_ECC_HW;
1832 + nand->ecc.write_subpage = mtk_nfc_write_subpage_hwecc;
1833 + nand->ecc.write_page_raw = mtk_nfc_write_page_raw;
1834 + nand->ecc.write_page = mtk_nfc_write_page_hwecc;
1835 + nand->ecc.write_oob_raw = mtk_nfc_write_oob_std;
1836 + nand->ecc.write_oob = mtk_nfc_write_oob_std;
1838 + nand->ecc.read_subpage = mtk_nfc_read_subpage_hwecc;
1839 + nand->ecc.read_page_raw = mtk_nfc_read_page_raw;
1840 + nand->ecc.read_page = mtk_nfc_read_page_hwecc;
1841 + nand->ecc.read_oob_raw = mtk_nfc_read_oob_std;
1842 + nand->ecc.read_oob = mtk_nfc_read_oob_std;
1844 + mtd = nand_to_mtd(nand);
1845 + mtd->owner = THIS_MODULE;
1846 + mtd->dev.parent = dev;
1847 + mtd->name = MTK_NAME;
1848 + mtd_set_ooblayout(mtd, &mtk_nfc_ooblayout_ops);
1850 + mtk_nfc_hw_init(nfc);
1852 + ret = nand_scan_ident(mtd, nsels, NULL);
1856 + /* store bbt magic in page, cause OOB is not protected */
1857 + if (nand->bbt_options & NAND_BBT_USE_FLASH)
1858 + nand->bbt_options |= NAND_BBT_NO_OOB;
1860 + ret = mtk_nfc_ecc_init(dev, mtd);
1864 + mtk_nfc_set_spare_per_sector(&chip->spare_per_sector, mtd);
1865 + mtk_nfc_set_fdm(&chip->fdm, mtd);
1866 + mtk_nfc_set_bad_mark_ctl(&chip->bad_mark, mtd);
1868 + len = mtd->writesize + mtd->oobsize;
1869 + nfc->buffer = devm_kzalloc(dev, len, GFP_KERNEL);
1873 + ret = nand_scan_tail(mtd);
1877 + ret = mtd_device_parse_register(mtd, NULL, NULL, NULL, 0);
1879 + dev_err(dev, "mtd parse partition error\n");
1880 + nand_release(mtd);
1884 + list_add_tail(&chip->node, &nfc->chips);
1889 +static int mtk_nfc_nand_chips_init(struct device *dev, struct mtk_nfc *nfc)
1891 + struct device_node *np = dev->of_node;
1892 + struct device_node *nand_np;
1895 + for_each_child_of_node(np, nand_np) {
1896 + ret = mtk_nfc_nand_chip_init(dev, nfc, nand_np);
1898 + of_node_put(nand_np);
1906 +static int mtk_nfc_probe(struct platform_device *pdev)
1908 + struct device *dev = &pdev->dev;
1909 + struct device_node *np = dev->of_node;
1910 + struct mtk_nfc *nfc;
1911 + struct resource *res;
1914 + nfc = devm_kzalloc(dev, sizeof(*nfc), GFP_KERNEL);
1918 + spin_lock_init(&nfc->controller.lock);
1919 + init_waitqueue_head(&nfc->controller.wq);
1920 + INIT_LIST_HEAD(&nfc->chips);
1922 + /* probe defer if not ready */
1923 + nfc->ecc = of_mtk_ecc_get(np);
1924 + if (IS_ERR(nfc->ecc))
1925 + return PTR_ERR(nfc->ecc);
1926 + else if (!nfc->ecc)
1931 + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1932 + nfc->regs = devm_ioremap_resource(dev, res);
1933 + if (IS_ERR(nfc->regs)) {
1934 + ret = PTR_ERR(nfc->regs);
1935 + dev_err(dev, "no nfi base\n");
1939 + nfc->clk.nfi_clk = devm_clk_get(dev, "nfi_clk");
1940 + if (IS_ERR(nfc->clk.nfi_clk)) {
1941 + dev_err(dev, "no clk\n");
1942 + ret = PTR_ERR(nfc->clk.nfi_clk);
1946 + nfc->clk.pad_clk = devm_clk_get(dev, "pad_clk");
1947 + if (IS_ERR(nfc->clk.pad_clk)) {
1948 + dev_err(dev, "no pad clk\n");
1949 + ret = PTR_ERR(nfc->clk.pad_clk);
1953 + ret = mtk_nfc_enable_clk(dev, &nfc->clk);
1957 + irq = platform_get_irq(pdev, 0);
1959 + dev_err(dev, "no nfi irq resource\n");
1964 + ret = devm_request_irq(dev, irq, mtk_nfc_irq, 0x0, "mtk-nand", nfc);
1966 + dev_err(dev, "failed to request nfi irq\n");
1970 + ret = dma_set_mask(dev, DMA_BIT_MASK(32));
1972 + dev_err(dev, "failed to set dma mask\n");
1976 + platform_set_drvdata(pdev, nfc);
1978 + ret = mtk_nfc_nand_chips_init(dev, nfc);
1980 + dev_err(dev, "failed to init nand chips\n");
1987 + mtk_nfc_disable_clk(&nfc->clk);
1990 + mtk_ecc_release(nfc->ecc);
1995 +static int mtk_nfc_remove(struct platform_device *pdev)
1997 + struct mtk_nfc *nfc = platform_get_drvdata(pdev);
1998 + struct mtk_nfc_nand_chip *chip;
2000 + while (!list_empty(&nfc->chips)) {
2001 + chip = list_first_entry(&nfc->chips, struct mtk_nfc_nand_chip,
2003 + nand_release(nand_to_mtd(&chip->nand));
2004 + list_del(&chip->node);
2007 + mtk_ecc_release(nfc->ecc);
2008 + mtk_nfc_disable_clk(&nfc->clk);
2013 +#ifdef CONFIG_PM_SLEEP
2014 +static int mtk_nfc_suspend(struct device *dev)
2016 + struct mtk_nfc *nfc = dev_get_drvdata(dev);
2018 + mtk_nfc_disable_clk(&nfc->clk);
2023 +static int mtk_nfc_resume(struct device *dev)
2025 + struct mtk_nfc *nfc = dev_get_drvdata(dev);
2026 + struct mtk_nfc_nand_chip *chip;
2027 + struct nand_chip *nand;
2028 + struct mtd_info *mtd;
2034 + ret = mtk_nfc_enable_clk(dev, &nfc->clk);
2038 + mtk_nfc_hw_init(nfc);
2040 + list_for_each_entry(chip, &nfc->chips, node) {
2041 + nand = &chip->nand;
2042 + mtd = nand_to_mtd(nand);
2043 + for (i = 0; i < chip->nsels; i++) {
2044 + nand->select_chip(mtd, i);
2045 + nand->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2051 +static SIMPLE_DEV_PM_OPS(mtk_nfc_pm_ops, mtk_nfc_suspend, mtk_nfc_resume);
2054 +static const struct of_device_id mtk_nfc_id_table[] = {
2055 + { .compatible = "mediatek,mt2701-nfc" },
2058 +MODULE_DEVICE_TABLE(of, mtk_nfc_id_table);
2060 +static struct platform_driver mtk_nfc_driver = {
2061 + .probe = mtk_nfc_probe,
2062 + .remove = mtk_nfc_remove,
2065 + .of_match_table = mtk_nfc_id_table,
2066 +#ifdef CONFIG_PM_SLEEP
2067 + .pm = &mtk_nfc_pm_ops,
2072 +module_platform_driver(mtk_nfc_driver);
2074 +MODULE_LICENSE("GPL");
2075 +MODULE_AUTHOR("Xiaolei Li <xiaolei.li@mediatek.com>");
2076 +MODULE_AUTHOR("Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>");
2077 +MODULE_DESCRIPTION("MTK Nand Flash Controller Driver");