1 From 5077ac38a86023124ebbe24cd1b7ecbd0f8edaff Mon Sep 17 00:00:00 2001
2 From: John Crispin <john@phrozen.org>
3 Date: Tue, 3 May 2016 03:06:59 +0200
4 Subject: [PATCH 086/102] net-next: mediatek: add next data pointer coherency
7 The QDMA engine can fail to update the register pointing to the next TX
8 descriptor if this bit does not get set in the QDMA configuration register.
9 Not setting this bit can result in invalid values inside the TX rings
10 registers which will causes TX stalls.
12 Signed-off-by: Sean Wang <keyhaede@gmail.com>
13 Signed-off-by: John Crispin <john@phrozen.org>
15 drivers/net/ethernet/mediatek/mtk_eth_soc.c | 2 +-
16 drivers/net/ethernet/mediatek/mtk_eth_soc.h | 1 +
17 2 files changed, 2 insertions(+), 1 deletion(-)
19 diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
20 index aadd748..72908b2 100644
21 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
22 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
23 @@ -1292,7 +1292,7 @@ static int mtk_start_dma(struct mtk_eth *eth)
25 MTK_TX_WB_DDONE | MTK_RX_DMA_EN | MTK_TX_DMA_EN |
26 MTK_RX_2B_OFFSET | MTK_DMA_SIZE_16DWORDS |
28 + MTK_RX_BT_32DWORDS | MTK_NDP_CO_PRO,
32 diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.h b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
33 index 57f7e8a..a5eb7c6 100644
34 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
35 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
37 #define MTK_QDMA_GLO_CFG 0x1A04
38 #define MTK_RX_2B_OFFSET BIT(31)
39 #define MTK_RX_BT_32DWORDS (3 << 11)
40 +#define MTK_NDP_CO_PRO BIT(10)
41 #define MTK_TX_WB_DDONE BIT(6)
42 #define MTK_DMA_SIZE_16DWORDS (2 << 4)
43 #define MTK_RX_DMA_BUSY BIT(3)