1 From 660c13dfbacbf37f090a66a2b14f0c5ce7cbec81 Mon Sep 17 00:00:00 2001
2 From: John Crispin <john@phrozen.org>
3 Date: Thu, 10 Aug 2017 16:38:27 +0200
4 Subject: [PATCH 57/57] net: mediatek: add HW QoS support
6 Signed-off-by: John Crispin <john@phrozen.org>
8 drivers/net/ethernet/mediatek/Kconfig | 7 ++++
9 drivers/net/ethernet/mediatek/mtk_eth_soc.c | 60 ++++++++++++++++++++++++++++-
10 drivers/net/ethernet/mediatek/mtk_eth_soc.h | 2 +-
11 3 files changed, 66 insertions(+), 3 deletions(-)
13 --- a/drivers/net/ethernet/mediatek/Kconfig
14 +++ b/drivers/net/ethernet/mediatek/Kconfig
15 @@ -21,4 +21,11 @@ config NET_MEDIATEK_HNAT
16 This driver supports the hardwaer NAT in the
17 MediaTek MT2701/MT7623 chipset family.
19 +config NET_MEDIATEK_HW_QOS
20 + tristate "MediaTek MT7623 hardware QoS support"
21 + depends on NET_MEDIATEK_SOC
23 + This driver supports the hardware QoS in the
24 + MediaTek MT2701/MT7623 chipset family.
26 endif #NET_VENDOR_MEDIATEK
27 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
28 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
30 #include <linux/reset.h>
31 #include <linux/tcp.h>
33 +#if defined(CONFIG_NET_MEDIATEK_HW_QOS)
34 +struct mtk_ioctl_reg {
39 +#define REG_HQOS_MAX 0x3FFF
40 +#define RAETH_QDMA_REG_READ 0x89F8
41 +#define RAETH_QDMA_REG_WRITE 0x89F9
44 #if defined(CONFIG_NET_MEDIATEK_HNAT) || defined(CONFIG_NET_MEDIATEK_HNAT_MODULE)
45 #include "mtk_hnat/nf_hnat_mtk.h"
47 @@ -646,7 +657,7 @@ static int mtk_tx_map(struct sk_buff *sk
48 dma_addr_t mapped_addr;
49 unsigned int nr_frags;
51 - u32 txd4 = 0, fport;
52 + u32 txd3 = 0, txd4 = 0, fport;
54 itxd = ring->next_free;
55 if (itxd == ring->last_free)
56 @@ -675,6 +686,12 @@ static int mtk_tx_map(struct sk_buff *sk
57 // if (skb_vlan_tag_present(skb))
58 // txd4 |= TX_DMA_INS_VLAN | skb_vlan_tag_get(skb);
60 +#ifdef CONFIG_NET_MEDIATEK_HW_QOS
61 + txd3 |= skb->mark & 0x7;
66 mapped_addr = dma_map_single(eth->dev, skb->data,
67 skb_headlen(skb), DMA_TO_DEVICE);
68 if (unlikely(dma_mapping_error(eth->dev, mapped_addr)))
69 @@ -718,7 +735,8 @@ static int mtk_tx_map(struct sk_buff *sk
70 WRITE_ONCE(txd->txd1, mapped_addr);
71 WRITE_ONCE(txd->txd3, (TX_DMA_SWC |
72 TX_DMA_PLEN0(frag_map_size) |
73 - last_frag * TX_DMA_LS0));
74 + last_frag * TX_DMA_LS0 |
76 WRITE_ONCE(txd->txd4, fport);
78 tx_buf = mtk_desc_to_tx_buf(ring, txd);
79 @@ -2029,7 +2047,31 @@ static void mtk_uninit(struct net_device
81 static int mtk_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
83 +#if defined(CONFIG_NET_MEDIATEK_HW_QOS)
84 + struct mtk_mac *mac = netdev_priv(dev);
85 + struct mtk_eth *eth = mac->hw;
86 + struct mtk_ioctl_reg reg;
90 +#if defined(CONFIG_NET_MEDIATEK_HW_QOS)
91 + case RAETH_QDMA_REG_READ:
92 + copy_from_user(®, ifr->ifr_data, sizeof(reg));
93 + if (reg.off > REG_HQOS_MAX)
95 + reg.val = mtk_r32(eth, 0x1800 + reg.off);
96 +// printk("read reg off:%x val:%x\n", reg.off, reg.val);
97 + copy_to_user(ifr->ifr_data, ®, sizeof(reg));
100 + case RAETH_QDMA_REG_WRITE:
101 + copy_from_user(®, ifr->ifr_data, sizeof(reg));
102 + if (reg.off > REG_HQOS_MAX)
104 + mtk_w32(eth, reg.val, 0x1800 + reg.off);
105 +// printk("write reg off:%x val:%x\n", reg.off, reg.val);
111 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
112 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
114 #define MTK_QDMA_PAGE_SIZE 2048
115 #define MTK_MAX_RX_LENGTH 1536
116 #define MTK_TX_DMA_BUF_LEN 0x3fff
117 -#define MTK_DMA_SIZE 256
118 +#define MTK_DMA_SIZE 2048
119 #define MTK_NAPI_WEIGHT 64
120 #define MTK_MAC_COUNT 2
121 #define MTK_RX_ETH_HLEN (VLAN_ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN)