1 From 21d106f15262f5a2ef7531636e0703ee61c33c61 Mon Sep 17 00:00:00 2001
2 From: Sungbo Eo <mans0n@gorani.run>
3 Date: Sun, 8 Aug 2021 21:38:40 +0900
4 Subject: [PATCH 2/2] arm: dts: mt7623: add musb device nodes
6 MT7623 has an musb controller that is compatible with the one from MT2701.
8 Signed-off-by: Sungbo Eo <mans0n@gorani.run>
10 arch/arm/boot/dts/mt7623.dtsi | 34 ++++++++++++++++++++++++++++++++++
11 arch/arm/boot/dts/mt7623a.dtsi | 4 ++++
12 2 files changed, 38 insertions(+)
14 --- a/arch/arm/boot/dts/mt7623.dtsi
15 +++ b/arch/arm/boot/dts/mt7623.dtsi
20 + usb0: usb@11200000 {
21 + compatible = "mediatek,mt7623-musb",
22 + "mediatek,mtk-musb";
23 + reg = <0 0x11200000 0 0x1000>;
24 + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_LOW>;
25 + interrupt-names = "mc";
26 + phys = <&u2port2 PHY_TYPE_USB2>;
28 + clocks = <&pericfg CLK_PERI_USB0>,
29 + <&pericfg CLK_PERI_USB0_MCU>,
30 + <&pericfg CLK_PERI_USB_SLV>;
31 + clock-names = "main","mcu","univpll";
32 + power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
33 + status = "disabled";
36 + u2phy1: t-phy@11210000 {
37 + compatible = "mediatek,mt7623-tphy",
38 + "mediatek,generic-tphy-v1";
39 + reg = <0 0x11210000 0 0x0800>;
40 + #address-cells = <2>;
43 + status = "disabled";
45 + u2port2: usb-phy@11210800 {
46 + reg = <0 0x11210800 0 0x0100>;
47 + clocks = <&topckgen CLK_TOP_USB_PHY48M>;
48 + clock-names = "ref";
54 audsys: clock-controller@11220000 {
55 compatible = "mediatek,mt7623-audsys",
56 "mediatek,mt2701-audsys",
57 --- a/arch/arm/boot/dts/mt7623a.dtsi
58 +++ b/arch/arm/boot/dts/mt7623a.dtsi
60 clock-names = "ethif";
64 + power-domains = <&scpsys MT7623A_POWER_DOMAIN_IFR_MSC>;
68 power-domains = <&scpsys MT7623A_POWER_DOMAIN_HIF>;