target/linux/mediatek/patches-5.15/191-arm64-dts-mt7622-specify-the-L2-cache-topology.patch

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  71 From: Rui Salvaterra <rsalvaterra@gmail.com>
  72 To: linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org,
  73  linux-kernel@vger.kernel.org
  74 Cc: matthias.bgg@gmail.com, ryder.lee@mediatek.com, daniel@makrotopia.org,
  75  Rui Salvaterra <rsalvaterra@gmail.com>
  76 Subject: [PATCH] arm64: dts: mt7622: specify the L2 cache topology
  77 Date: Thu, 28 Apr 2022 23:57:55 +0100
  78 Message-Id: <20220428225755.785153-1-rsalvaterra@gmail.com>
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 100
 101 On an MT7622 system, the kernel complains of not being able to detect the cache
 102 hierarchy of CPU 0. Specify the shared L2 cache node in the device tree, in
 103 order to fix this.
 104
 105 Signed-off-by: Rui Salvaterra <rsalvaterra@gmail.com>
 106 ---
 107  arch/arm64/boot/dts/mediatek/mt7622.dtsi | 7 +++++++
 108  1 file changed, 7 insertions(+)
 109
 110 --- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
 111 +++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
 112 @@ -80,6 +80,7 @@
 113                         enable-method = "psci";
 114                         clock-frequency = <1300000000>;
 115                         cci-control-port = <&cci_control2>;
 116 +                       next-level-cache = <&L2>;
 117                 };
 118
 119                 cpu1: cpu@1 {
 120 @@ -94,6 +95,12 @@
 121                         enable-method = "psci";
 122                         clock-frequency = <1300000000>;
 123                         cci-control-port = <&cci_control2>;
 124 +                       next-level-cache = <&L2>;
 125 +               };
 126 +
 127 +               L2: l2-cache {
 128 +                       compatible = "cache";
 129 +                       cache-level = <2>;
 130                 };
 131         };
 132