1 --- a/drivers/clk/mediatek/clk-mtk.h
2 +++ b/drivers/clk/mediatek/clk-mtk.h
3 @@ -233,6 +233,7 @@ struct mtk_pll_data {
8 const struct mtk_pll_div_table *div_table;
9 const char *parent_name;
11 --- a/drivers/clk/mediatek/clk-pll.c
12 +++ b/drivers/clk/mediatek/clk-pll.c
13 @@ -137,7 +137,10 @@ static void mtk_pll_set_rate_regs(struct
14 pll->data->pcw_shift);
15 val |= pcw << pll->data->pcw_shift;
16 writel(val, pll->pcw_addr);
17 - chg = readl(pll->pcw_chg_addr) | PCW_CHG_MASK;
18 + if (pll->data->pcw_chg_shift)
19 + chg = readl(pll->pcw_chg_addr) | BIT(pll->data->pcw_chg_shift);
21 + chg = readl(pll->pcw_chg_addr) | PCW_CHG_MASK;
22 writel(chg, pll->pcw_chg_addr);
24 writel(val + 1, pll->tuner_addr);